scf0403_lcd.c 8.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * scf0403.c -- support for DataImage SCF0403 LCD
  4. *
  5. * Copyright (c) 2013 Adapted from Linux driver:
  6. * Copyright (c) 2012 Anders Electronics plc. All Rights Reserved.
  7. * Copyright (c) 2012 CompuLab, Ltd
  8. * Dmitry Lifshitz <lifshitz@compulab.co.il>
  9. * Ilya Ledvich <ilya@compulab.co.il>
  10. * Inspired by Alberto Panizzo <maramaopercheseimorto@gmail.com> &
  11. * Marek Vasut work in l4f00242t03.c
  12. *
  13. * U-Boot port: Nikita Kiryanov <nikita@compulab.co.il>
  14. */
  15. #include <common.h>
  16. #include <malloc.h>
  17. #include <asm/gpio.h>
  18. #include <spi.h>
  19. struct scf0403_cmd {
  20. u16 cmd;
  21. u16 *params;
  22. int count;
  23. };
  24. struct scf0403_initseq_entry {
  25. struct scf0403_cmd cmd;
  26. int delay_ms;
  27. };
  28. struct scf0403_priv {
  29. struct spi_slave *spi;
  30. unsigned int reset_gpio;
  31. u32 rddid;
  32. struct scf0403_initseq_entry *init_seq;
  33. int seq_size;
  34. };
  35. struct scf0403_priv priv;
  36. #define SCF0403852GGU04_ID 0x000080
  37. /* SCF0403526GGU20 model commands parameters */
  38. static u16 extcmd_params_sn20[] = {0xff, 0x98, 0x06};
  39. static u16 spiinttype_params_sn20[] = {0x60};
  40. static u16 bc_params_sn20[] = {
  41. 0x01, 0x10, 0x61, 0x74, 0x01, 0x01, 0x1B,
  42. 0x12, 0x71, 0x00, 0x00, 0x00, 0x01, 0x01,
  43. 0x05, 0x00, 0xFF, 0xF2, 0x01, 0x00, 0x40,
  44. };
  45. static u16 bd_params_sn20[] = {0x01, 0x23, 0x45, 0x67, 0x01, 0x23, 0x45, 0x67};
  46. static u16 be_params_sn20[] = {
  47. 0x01, 0x22, 0x22, 0xBA, 0xDC, 0x26, 0x28, 0x22, 0x22,
  48. };
  49. static u16 vcom_params_sn20[] = {0x74};
  50. static u16 vmesur_params_sn20[] = {0x7F, 0x0F, 0x00};
  51. static u16 powerctl_params_sn20[] = {0x03, 0x0b, 0x00};
  52. static u16 lvglvolt_params_sn20[] = {0x08};
  53. static u16 engsetting_params_sn20[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x20};
  54. static u16 dispfunc_params_sn20[] = {0xa0};
  55. static u16 dvddvolt_params_sn20[] = {0x74};
  56. static u16 dispinv_params_sn20[] = {0x00, 0x00, 0x00};
  57. static u16 panelres_params_sn20[] = {0x82};
  58. static u16 framerate_params_sn20[] = {0x00, 0x13, 0x13};
  59. static u16 timing_params_sn20[] = {0x80, 0x05, 0x40, 0x28};
  60. static u16 powerctl2_params_sn20[] = {0x17, 0x75, 0x79, 0x20};
  61. static u16 memaccess_params_sn20[] = {0x00};
  62. static u16 pixfmt_params_sn20[] = {0x66};
  63. static u16 pgamma_params_sn20[] = {
  64. 0x00, 0x03, 0x0b, 0x0c, 0x0e, 0x08, 0xc5, 0x04,
  65. 0x08, 0x0c, 0x13, 0x11, 0x11, 0x14, 0x0c, 0x10,
  66. };
  67. static u16 ngamma_params_sn20[] = {
  68. 0x00, 0x0d, 0x11, 0x0c, 0x0c, 0x04, 0x76, 0x03,
  69. 0x08, 0x0b, 0x16, 0x10, 0x0d, 0x16, 0x0a, 0x00,
  70. };
  71. static u16 tearing_params_sn20[] = {0x00};
  72. /* SCF0403852GGU04 model commands parameters */
  73. static u16 memaccess_params_sn04[] = {0x08};
  74. static u16 pixfmt_params_sn04[] = {0x66};
  75. static u16 modectl_params_sn04[] = {0x01};
  76. static u16 dispfunc_params_sn04[] = {0x22, 0xe2, 0xFF, 0x04};
  77. static u16 vcom_params_sn04[] = {0x00, 0x6A};
  78. static u16 pgamma_params_sn04[] = {
  79. 0x00, 0x07, 0x0d, 0x10, 0x13, 0x19, 0x0f, 0x0c,
  80. 0x05, 0x08, 0x06, 0x13, 0x0f, 0x30, 0x20, 0x1f,
  81. };
  82. static u16 ngamma_params_sn04[] = {
  83. 0x1F, 0x20, 0x30, 0x0F, 0x13, 0x06, 0x08, 0x05,
  84. 0x0C, 0x0F, 0x19, 0x13, 0x10, 0x0D, 0x07, 0x00,
  85. };
  86. static u16 dispinv_params_sn04[] = {0x02};
  87. /* Common commands */
  88. static struct scf0403_cmd scf0403_cmd_slpout = {0x11, NULL, 0};
  89. static struct scf0403_cmd scf0403_cmd_dison = {0x29, NULL, 0};
  90. /* SCF0403852GGU04 init sequence */
  91. static struct scf0403_initseq_entry scf0403_initseq_sn04[] = {
  92. {{0x36, memaccess_params_sn04, ARRAY_SIZE(memaccess_params_sn04)}, 0},
  93. {{0x3A, pixfmt_params_sn04, ARRAY_SIZE(pixfmt_params_sn04)}, 0},
  94. {{0xB6, dispfunc_params_sn04, ARRAY_SIZE(dispfunc_params_sn04)}, 0},
  95. {{0xC5, vcom_params_sn04, ARRAY_SIZE(vcom_params_sn04)}, 0},
  96. {{0xE0, pgamma_params_sn04, ARRAY_SIZE(pgamma_params_sn04)}, 0},
  97. {{0xE1, ngamma_params_sn04, ARRAY_SIZE(ngamma_params_sn04)}, 20},
  98. {{0xB0, modectl_params_sn04, ARRAY_SIZE(modectl_params_sn04)}, 0},
  99. {{0xB4, dispinv_params_sn04, ARRAY_SIZE(dispinv_params_sn04)}, 100},
  100. };
  101. /* SCF0403526GGU20 init sequence */
  102. static struct scf0403_initseq_entry scf0403_initseq_sn20[] = {
  103. {{0xff, extcmd_params_sn20, ARRAY_SIZE(extcmd_params_sn20)}, 0},
  104. {{0xba, spiinttype_params_sn20, ARRAY_SIZE(spiinttype_params_sn20)}, 0},
  105. {{0xbc, bc_params_sn20, ARRAY_SIZE(bc_params_sn20)}, 0},
  106. {{0xbd, bd_params_sn20, ARRAY_SIZE(bd_params_sn20)}, 0},
  107. {{0xbe, be_params_sn20, ARRAY_SIZE(be_params_sn20)}, 0},
  108. {{0xc7, vcom_params_sn20, ARRAY_SIZE(vcom_params_sn20)}, 0},
  109. {{0xed, vmesur_params_sn20, ARRAY_SIZE(vmesur_params_sn20)}, 0},
  110. {{0xc0, powerctl_params_sn20, ARRAY_SIZE(powerctl_params_sn20)}, 0},
  111. {{0xfc, lvglvolt_params_sn20, ARRAY_SIZE(lvglvolt_params_sn20)}, 0},
  112. {{0xb6, dispfunc_params_sn20, ARRAY_SIZE(dispfunc_params_sn20)}, 0},
  113. {{0xdf, engsetting_params_sn20, ARRAY_SIZE(engsetting_params_sn20)}, 0},
  114. {{0xf3, dvddvolt_params_sn20, ARRAY_SIZE(dvddvolt_params_sn20)}, 0},
  115. {{0xb4, dispinv_params_sn20, ARRAY_SIZE(dispinv_params_sn20)}, 0},
  116. {{0xf7, panelres_params_sn20, ARRAY_SIZE(panelres_params_sn20)}, 0},
  117. {{0xb1, framerate_params_sn20, ARRAY_SIZE(framerate_params_sn20)}, 0},
  118. {{0xf2, timing_params_sn20, ARRAY_SIZE(timing_params_sn20)}, 0},
  119. {{0xc1, powerctl2_params_sn20, ARRAY_SIZE(powerctl2_params_sn20)}, 0},
  120. {{0x36, memaccess_params_sn20, ARRAY_SIZE(memaccess_params_sn20)}, 0},
  121. {{0x3a, pixfmt_params_sn20, ARRAY_SIZE(pixfmt_params_sn20)}, 0},
  122. {{0xe0, pgamma_params_sn20, ARRAY_SIZE(pgamma_params_sn20)}, 0},
  123. {{0xe1, ngamma_params_sn20, ARRAY_SIZE(ngamma_params_sn20)}, 0},
  124. {{0x35, tearing_params_sn20, ARRAY_SIZE(tearing_params_sn20)}, 0},
  125. };
  126. static void scf0403_gpio_reset(unsigned int gpio)
  127. {
  128. if (!gpio_is_valid(gpio))
  129. return;
  130. gpio_set_value(gpio, 1);
  131. mdelay(100);
  132. gpio_set_value(gpio, 0);
  133. mdelay(40);
  134. gpio_set_value(gpio, 1);
  135. mdelay(100);
  136. }
  137. static int scf0403_spi_read_rddid(struct spi_slave *spi, u32 *rddid)
  138. {
  139. int error = 0;
  140. u8 ids_buf = 0x00;
  141. u16 dummy_buf = 0x00;
  142. u16 cmd = 0x04;
  143. error = spi_set_wordlen(spi, 9);
  144. if (error)
  145. return error;
  146. /* Here 9 bits required to transmit a command */
  147. error = spi_xfer(spi, 9, &cmd, NULL, SPI_XFER_ONCE);
  148. if (error)
  149. return error;
  150. /*
  151. * Here 8 + 1 bits required to arrange extra clock cycle
  152. * before the first data bit.
  153. * According to the datasheet - first parameter is the dummy data.
  154. */
  155. error = spi_xfer(spi, 9, NULL, &dummy_buf, SPI_XFER_ONCE);
  156. if (error)
  157. return error;
  158. error = spi_set_wordlen(spi, 8);
  159. if (error)
  160. return error;
  161. /* Read rest of the data */
  162. error = spi_xfer(spi, 8, NULL, &ids_buf, SPI_XFER_ONCE);
  163. if (error)
  164. return error;
  165. *rddid = ids_buf;
  166. return 0;
  167. }
  168. static int scf0403_spi_transfer(struct spi_slave *spi, struct scf0403_cmd *cmd)
  169. {
  170. int i, error;
  171. u32 command = cmd->cmd;
  172. u32 msg;
  173. error = spi_set_wordlen(spi, 9);
  174. if (error)
  175. return error;
  176. error = spi_xfer(spi, 9, &command, NULL, SPI_XFER_ONCE);
  177. if (error)
  178. return error;
  179. for (i = 0; i < cmd->count; i++) {
  180. msg = (cmd->params[i] | 0x100);
  181. error = spi_xfer(spi, 9, &msg, NULL, SPI_XFER_ONCE);
  182. if (error)
  183. return error;
  184. }
  185. return 0;
  186. }
  187. static void scf0403_lcd_init(struct scf0403_priv *priv)
  188. {
  189. int i;
  190. /* reset LCD */
  191. scf0403_gpio_reset(priv->reset_gpio);
  192. for (i = 0; i < priv->seq_size; i++) {
  193. if (scf0403_spi_transfer(priv->spi, &priv->init_seq[i].cmd) < 0)
  194. puts("SPI transfer failed\n");
  195. mdelay(priv->init_seq[i].delay_ms);
  196. }
  197. }
  198. static int scf0403_request_reset_gpio(unsigned gpio)
  199. {
  200. int err = gpio_request(gpio, "lcd reset");
  201. if (err)
  202. return err;
  203. err = gpio_direction_output(gpio, 0);
  204. if (err)
  205. gpio_free(gpio);
  206. return err;
  207. }
  208. int scf0403_init(int reset_gpio)
  209. {
  210. int error;
  211. if (gpio_is_valid(reset_gpio)) {
  212. error = scf0403_request_reset_gpio(reset_gpio);
  213. if (error) {
  214. printf("Failed requesting reset GPIO%d: %d\n",
  215. reset_gpio, error);
  216. return error;
  217. }
  218. }
  219. priv.reset_gpio = reset_gpio;
  220. priv.spi = spi_setup_slave(3, 0, 1000000, SPI_MODE_0);
  221. error = spi_claim_bus(priv.spi);
  222. if (error)
  223. goto bus_claim_fail;
  224. /* reset LCD */
  225. scf0403_gpio_reset(reset_gpio);
  226. error = scf0403_spi_read_rddid(priv.spi, &priv.rddid);
  227. if (error) {
  228. puts("IDs read failed\n");
  229. goto readid_fail;
  230. }
  231. if (priv.rddid == SCF0403852GGU04_ID) {
  232. priv.init_seq = scf0403_initseq_sn04;
  233. priv.seq_size = ARRAY_SIZE(scf0403_initseq_sn04);
  234. } else {
  235. priv.init_seq = scf0403_initseq_sn20;
  236. priv.seq_size = ARRAY_SIZE(scf0403_initseq_sn20);
  237. }
  238. scf0403_lcd_init(&priv);
  239. /* Start operation */
  240. scf0403_spi_transfer(priv.spi, &scf0403_cmd_dison);
  241. mdelay(100);
  242. scf0403_spi_transfer(priv.spi, &scf0403_cmd_slpout);
  243. spi_release_bus(priv.spi);
  244. return 0;
  245. readid_fail:
  246. spi_release_bus(priv.spi);
  247. bus_claim_fail:
  248. if (gpio_is_valid(priv.reset_gpio))
  249. gpio_free(priv.reset_gpio);
  250. return error;
  251. }