raydium-rm68200.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2019 STMicroelectronics - All Rights Reserved
  4. * Author(s): Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
  5. * Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
  6. *
  7. * This rm68200 panel driver is inspired from the Linux Kernel driver
  8. * drivers/gpu/drm/panel/panel-raydium-rm68200.c.
  9. */
  10. #include <common.h>
  11. #include <backlight.h>
  12. #include <dm.h>
  13. #include <mipi_dsi.h>
  14. #include <panel.h>
  15. #include <asm/gpio.h>
  16. #include <dm/device_compat.h>
  17. #include <power/regulator.h>
  18. /*** Manufacturer Command Set ***/
  19. #define MCS_CMD_MODE_SW 0xFE /* CMD Mode Switch */
  20. #define MCS_CMD1_UCS 0x00 /* User Command Set (UCS = CMD1) */
  21. #define MCS_CMD2_P0 0x01 /* Manufacture Command Set Page0 (CMD2 P0) */
  22. #define MCS_CMD2_P1 0x02 /* Manufacture Command Set Page1 (CMD2 P1) */
  23. #define MCS_CMD2_P2 0x03 /* Manufacture Command Set Page2 (CMD2 P2) */
  24. #define MCS_CMD2_P3 0x04 /* Manufacture Command Set Page3 (CMD2 P3) */
  25. /* CMD2 P0 commands (Display Options and Power) */
  26. #define MCS_STBCTR 0x12 /* TE1 Output Setting Zig-Zag Connection */
  27. #define MCS_SGOPCTR 0x16 /* Source Bias Current */
  28. #define MCS_SDCTR 0x1A /* Source Output Delay Time */
  29. #define MCS_INVCTR 0x1B /* Inversion Type */
  30. #define MCS_EXT_PWR_IC 0x24 /* External PWR IC Control */
  31. #define MCS_SETAVDD 0x27 /* PFM Control for AVDD Output */
  32. #define MCS_SETAVEE 0x29 /* PFM Control for AVEE Output */
  33. #define MCS_BT2CTR 0x2B /* DDVDL Charge Pump Control */
  34. #define MCS_BT3CTR 0x2F /* VGH Charge Pump Control */
  35. #define MCS_BT4CTR 0x34 /* VGL Charge Pump Control */
  36. #define MCS_VCMCTR 0x46 /* VCOM Output Level Control */
  37. #define MCS_SETVGN 0x52 /* VG M/S N Control */
  38. #define MCS_SETVGP 0x54 /* VG M/S P Control */
  39. #define MCS_SW_CTRL 0x5F /* Interface Control for PFM and MIPI */
  40. /* CMD2 P2 commands (GOA Timing Control) - no description in datasheet */
  41. #define GOA_VSTV1 0x00
  42. #define GOA_VSTV2 0x07
  43. #define GOA_VCLK1 0x0E
  44. #define GOA_VCLK2 0x17
  45. #define GOA_VCLK_OPT1 0x20
  46. #define GOA_BICLK1 0x2A
  47. #define GOA_BICLK2 0x37
  48. #define GOA_BICLK3 0x44
  49. #define GOA_BICLK4 0x4F
  50. #define GOA_BICLK_OPT1 0x5B
  51. #define GOA_BICLK_OPT2 0x60
  52. #define MCS_GOA_GPO1 0x6D
  53. #define MCS_GOA_GPO2 0x71
  54. #define MCS_GOA_EQ 0x74
  55. #define MCS_GOA_CLK_GALLON 0x7C
  56. #define MCS_GOA_FS_SEL0 0x7E
  57. #define MCS_GOA_FS_SEL1 0x87
  58. #define MCS_GOA_FS_SEL2 0x91
  59. #define MCS_GOA_FS_SEL3 0x9B
  60. #define MCS_GOA_BS_SEL0 0xAC
  61. #define MCS_GOA_BS_SEL1 0xB5
  62. #define MCS_GOA_BS_SEL2 0xBF
  63. #define MCS_GOA_BS_SEL3 0xC9
  64. #define MCS_GOA_BS_SEL4 0xD3
  65. /* CMD2 P3 commands (Gamma) */
  66. #define MCS_GAMMA_VP 0x60 /* Gamma VP1~VP16 */
  67. #define MCS_GAMMA_VN 0x70 /* Gamma VN1~VN16 */
  68. struct rm68200_panel_priv {
  69. struct udevice *reg;
  70. struct udevice *backlight;
  71. struct gpio_desc reset;
  72. unsigned int lanes;
  73. enum mipi_dsi_pixel_format format;
  74. unsigned long mode_flags;
  75. };
  76. static const struct display_timing default_timing = {
  77. .pixelclock.typ = 54000000,
  78. .hactive.typ = 720,
  79. .hfront_porch.typ = 48,
  80. .hback_porch.typ = 48,
  81. .hsync_len.typ = 9,
  82. .vactive.typ = 1280,
  83. .vfront_porch.typ = 12,
  84. .vback_porch.typ = 12,
  85. .vsync_len.typ = 5,
  86. };
  87. static void rm68200_dcs_write_buf(struct udevice *dev, const void *data,
  88. size_t len)
  89. {
  90. struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
  91. struct mipi_dsi_device *device = plat->device;
  92. int err;
  93. err = mipi_dsi_dcs_write_buffer(device, data, len);
  94. if (err < 0)
  95. dev_err(dev, "MIPI DSI DCS write buffer failed: %d\n", err);
  96. }
  97. static void rm68200_dcs_write_cmd(struct udevice *dev, u8 cmd, u8 value)
  98. {
  99. struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
  100. struct mipi_dsi_device *device = plat->device;
  101. int err;
  102. err = mipi_dsi_dcs_write(device, cmd, &value, 1);
  103. if (err < 0)
  104. dev_err(dev, "MIPI DSI DCS write failed: %d\n", err);
  105. }
  106. #define dcs_write_seq(ctx, seq...) \
  107. ({ \
  108. static const u8 d[] = { seq }; \
  109. \
  110. rm68200_dcs_write_buf(ctx, d, ARRAY_SIZE(d)); \
  111. })
  112. /*
  113. * This panel is not able to auto-increment all cmd addresses so for some of
  114. * them, we need to send them one by one...
  115. */
  116. #define dcs_write_cmd_seq(ctx, cmd, seq...) \
  117. ({ \
  118. static const u8 d[] = { seq }; \
  119. unsigned int i; \
  120. \
  121. for (i = 0; i < ARRAY_SIZE(d) ; i++) \
  122. rm68200_dcs_write_cmd(ctx, cmd + i, d[i]); \
  123. })
  124. static void rm68200_init_sequence(struct udevice *dev)
  125. {
  126. /* Enter CMD2 with page 0 */
  127. dcs_write_seq(dev, MCS_CMD_MODE_SW, MCS_CMD2_P0);
  128. dcs_write_cmd_seq(dev, MCS_EXT_PWR_IC, 0xC0, 0x53, 0x00);
  129. dcs_write_seq(dev, MCS_BT2CTR, 0xE5);
  130. dcs_write_seq(dev, MCS_SETAVDD, 0x0A);
  131. dcs_write_seq(dev, MCS_SETAVEE, 0x0A);
  132. dcs_write_seq(dev, MCS_SGOPCTR, 0x52);
  133. dcs_write_seq(dev, MCS_BT3CTR, 0x53);
  134. dcs_write_seq(dev, MCS_BT4CTR, 0x5A);
  135. dcs_write_seq(dev, MCS_INVCTR, 0x00);
  136. dcs_write_seq(dev, MCS_STBCTR, 0x0A);
  137. dcs_write_seq(dev, MCS_SDCTR, 0x06);
  138. dcs_write_seq(dev, MCS_VCMCTR, 0x56);
  139. dcs_write_seq(dev, MCS_SETVGN, 0xA0, 0x00);
  140. dcs_write_seq(dev, MCS_SETVGP, 0xA0, 0x00);
  141. dcs_write_seq(dev, MCS_SW_CTRL, 0x11); /* 2 data lanes, see doc */
  142. dcs_write_seq(dev, MCS_CMD_MODE_SW, MCS_CMD2_P2);
  143. dcs_write_seq(dev, GOA_VSTV1, 0x05);
  144. dcs_write_seq(dev, 0x02, 0x0B);
  145. dcs_write_seq(dev, 0x03, 0x0F);
  146. dcs_write_seq(dev, 0x04, 0x7D, 0x00, 0x50);
  147. dcs_write_cmd_seq(dev, GOA_VSTV2, 0x05, 0x16, 0x0D, 0x11, 0x7D, 0x00,
  148. 0x50);
  149. dcs_write_cmd_seq(dev, GOA_VCLK1, 0x07, 0x08, 0x01, 0x02, 0x00, 0x7D,
  150. 0x00, 0x85, 0x08);
  151. dcs_write_cmd_seq(dev, GOA_VCLK2, 0x03, 0x04, 0x05, 0x06, 0x00, 0x7D,
  152. 0x00, 0x85, 0x08);
  153. dcs_write_seq(dev, GOA_VCLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  154. 0x00, 0x00, 0x00, 0x00);
  155. dcs_write_cmd_seq(dev, GOA_BICLK1, 0x07, 0x08);
  156. dcs_write_seq(dev, 0x2D, 0x01);
  157. dcs_write_seq(dev, 0x2F, 0x02, 0x00, 0x40, 0x05, 0x08, 0x54, 0x7D,
  158. 0x00);
  159. dcs_write_cmd_seq(dev, GOA_BICLK2, 0x03, 0x04, 0x05, 0x06, 0x00);
  160. dcs_write_seq(dev, 0x3D, 0x40);
  161. dcs_write_seq(dev, 0x3F, 0x05, 0x08, 0x54, 0x7D, 0x00);
  162. dcs_write_seq(dev, GOA_BICLK3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  163. 0x00, 0x00, 0x00, 0x00, 0x00);
  164. dcs_write_seq(dev, GOA_BICLK4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  165. 0x00, 0x00);
  166. dcs_write_seq(dev, 0x58, 0x00, 0x00, 0x00);
  167. dcs_write_seq(dev, GOA_BICLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00);
  168. dcs_write_seq(dev, GOA_BICLK_OPT2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  169. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
  170. dcs_write_seq(dev, MCS_GOA_GPO1, 0x00, 0x00, 0x00, 0x00);
  171. dcs_write_seq(dev, MCS_GOA_GPO2, 0x00, 0x20, 0x00);
  172. dcs_write_seq(dev, MCS_GOA_EQ, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
  173. 0x00, 0x00);
  174. dcs_write_seq(dev, MCS_GOA_CLK_GALLON, 0x00, 0x00);
  175. dcs_write_cmd_seq(dev, MCS_GOA_FS_SEL0, 0xBF, 0x02, 0x06, 0x14, 0x10,
  176. 0x16, 0x12, 0x08, 0x3F);
  177. dcs_write_cmd_seq(dev, MCS_GOA_FS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0C,
  178. 0x0A, 0x0E, 0x3F, 0x3F, 0x00);
  179. dcs_write_cmd_seq(dev, MCS_GOA_FS_SEL2, 0x04, 0x3F, 0x3F, 0x3F, 0x3F,
  180. 0x05, 0x01, 0x3F, 0x3F, 0x0F);
  181. dcs_write_cmd_seq(dev, MCS_GOA_FS_SEL3, 0x0B, 0x0D, 0x3F, 0x3F, 0x3F,
  182. 0x3F);
  183. dcs_write_cmd_seq(dev, 0xA2, 0x3F, 0x09, 0x13, 0x17, 0x11, 0x15);
  184. dcs_write_cmd_seq(dev, 0xA9, 0x07, 0x03, 0x3F);
  185. dcs_write_cmd_seq(dev, MCS_GOA_BS_SEL0, 0x3F, 0x05, 0x01, 0x17, 0x13,
  186. 0x15, 0x11, 0x0F, 0x3F);
  187. dcs_write_cmd_seq(dev, MCS_GOA_BS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0B,
  188. 0x0D, 0x09, 0x3F, 0x3F, 0x07);
  189. dcs_write_cmd_seq(dev, MCS_GOA_BS_SEL2, 0x03, 0x3F, 0x3F, 0x3F, 0x3F,
  190. 0x02, 0x06, 0x3F, 0x3F, 0x08);
  191. dcs_write_cmd_seq(dev, MCS_GOA_BS_SEL3, 0x0C, 0x0A, 0x3F, 0x3F, 0x3F,
  192. 0x3F, 0x3F, 0x0E, 0x10, 0x14);
  193. dcs_write_cmd_seq(dev, MCS_GOA_BS_SEL4, 0x12, 0x16, 0x00, 0x04, 0x3F);
  194. dcs_write_seq(dev, 0xDC, 0x02);
  195. dcs_write_seq(dev, 0xDE, 0x12);
  196. dcs_write_seq(dev, MCS_CMD_MODE_SW, 0x0E); /* No documentation */
  197. dcs_write_seq(dev, 0x01, 0x75);
  198. dcs_write_seq(dev, MCS_CMD_MODE_SW, MCS_CMD2_P3);
  199. dcs_write_cmd_seq(dev, MCS_GAMMA_VP, 0x00, 0x0C, 0x12, 0x0E, 0x06,
  200. 0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F,
  201. 0x12, 0x0C, 0x00);
  202. dcs_write_cmd_seq(dev, MCS_GAMMA_VN, 0x00, 0x0C, 0x12, 0x0E, 0x06,
  203. 0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F,
  204. 0x12, 0x0C, 0x00);
  205. /* Exit CMD2 */
  206. dcs_write_seq(dev, MCS_CMD_MODE_SW, MCS_CMD1_UCS);
  207. }
  208. static int rm68200_panel_enable_backlight(struct udevice *dev)
  209. {
  210. struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
  211. struct mipi_dsi_device *device = plat->device;
  212. struct rm68200_panel_priv *priv = dev_get_priv(dev);
  213. int ret;
  214. ret = mipi_dsi_attach(device);
  215. if (ret < 0)
  216. return ret;
  217. rm68200_init_sequence(dev);
  218. ret = mipi_dsi_dcs_exit_sleep_mode(device);
  219. if (ret)
  220. return ret;
  221. mdelay(125);
  222. ret = mipi_dsi_dcs_set_display_on(device);
  223. if (ret)
  224. return ret;
  225. mdelay(20);
  226. ret = backlight_enable(priv->backlight);
  227. if (ret)
  228. return ret;
  229. return 0;
  230. }
  231. static int rm68200_panel_get_display_timing(struct udevice *dev,
  232. struct display_timing *timings)
  233. {
  234. struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
  235. struct mipi_dsi_device *device = plat->device;
  236. struct rm68200_panel_priv *priv = dev_get_priv(dev);
  237. memcpy(timings, &default_timing, sizeof(*timings));
  238. /* fill characteristics of DSI data link */
  239. device->lanes = priv->lanes;
  240. device->format = priv->format;
  241. device->mode_flags = priv->mode_flags;
  242. return 0;
  243. }
  244. static int rm68200_panel_ofdata_to_platdata(struct udevice *dev)
  245. {
  246. struct rm68200_panel_priv *priv = dev_get_priv(dev);
  247. int ret;
  248. if (IS_ENABLED(CONFIG_DM_REGULATOR)) {
  249. ret = device_get_supply_regulator(dev, "power-supply",
  250. &priv->reg);
  251. if (ret && ret != -ENOENT) {
  252. dev_err(dev, "Warning: cannot get power supply\n");
  253. return ret;
  254. }
  255. }
  256. ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset,
  257. GPIOD_IS_OUT);
  258. if (ret) {
  259. dev_err(dev, "Warning: cannot get reset GPIO\n");
  260. if (ret != -ENOENT)
  261. return ret;
  262. }
  263. ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
  264. "backlight", &priv->backlight);
  265. if (ret) {
  266. dev_err(dev, "Cannot get backlight: ret=%d\n", ret);
  267. return ret;
  268. }
  269. return 0;
  270. }
  271. static int rm68200_panel_probe(struct udevice *dev)
  272. {
  273. struct rm68200_panel_priv *priv = dev_get_priv(dev);
  274. int ret;
  275. if (IS_ENABLED(CONFIG_DM_REGULATOR) && priv->reg) {
  276. ret = regulator_set_enable(priv->reg, true);
  277. if (ret)
  278. return ret;
  279. }
  280. /* reset panel */
  281. dm_gpio_set_value(&priv->reset, true);
  282. mdelay(1);
  283. dm_gpio_set_value(&priv->reset, false);
  284. mdelay(10);
  285. priv->lanes = 2;
  286. priv->format = MIPI_DSI_FMT_RGB888;
  287. priv->mode_flags = MIPI_DSI_MODE_VIDEO |
  288. MIPI_DSI_MODE_VIDEO_BURST |
  289. MIPI_DSI_MODE_LPM;
  290. return 0;
  291. }
  292. static const struct panel_ops rm68200_panel_ops = {
  293. .enable_backlight = rm68200_panel_enable_backlight,
  294. .get_display_timing = rm68200_panel_get_display_timing,
  295. };
  296. static const struct udevice_id rm68200_panel_ids[] = {
  297. { .compatible = "raydium,rm68200" },
  298. { }
  299. };
  300. U_BOOT_DRIVER(rm68200_panel) = {
  301. .name = "rm68200_panel",
  302. .id = UCLASS_PANEL,
  303. .of_match = rm68200_panel_ids,
  304. .ops = &rm68200_panel_ops,
  305. .ofdata_to_platdata = rm68200_panel_ofdata_to_platdata,
  306. .probe = rm68200_panel_probe,
  307. .platdata_auto_alloc_size = sizeof(struct mipi_dsi_panel_plat),
  308. .priv_auto_alloc_size = sizeof(struct rm68200_panel_priv),
  309. };