pxa_lcd.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * PXA LCD Controller
  4. *
  5. * (C) Copyright 2001-2002
  6. * Wolfgang Denk, DENX Software Engineering -- wd@denx.de
  7. */
  8. /************************************************************************/
  9. /* ** HEADER FILES */
  10. /************************************************************************/
  11. #include <common.h>
  12. #include <asm/arch/pxa-regs.h>
  13. #include <asm/io.h>
  14. #include <lcd.h>
  15. #include <linux/types.h>
  16. #include <stdarg.h>
  17. #include <stdio_dev.h>
  18. /* #define DEBUG */
  19. #ifdef CONFIG_LCD
  20. /*----------------------------------------------------------------------*/
  21. /*
  22. * Define panel bpp, LCCR0, LCCR3 and panel_info video struct for
  23. * your display.
  24. */
  25. #ifdef CONFIG_PXA_VGA
  26. /* LCD outputs connected to a video DAC */
  27. # define LCD_BPP LCD_COLOR8
  28. /* you have to set lccr0 and lccr3 (including pcd) */
  29. # define REG_LCCR0 0x003008f8
  30. # define REG_LCCR3 0x0300FF01
  31. /* 640x480x16 @ 61 Hz */
  32. vidinfo_t panel_info = {
  33. .vl_col = 640,
  34. .vl_row = 480,
  35. .vl_width = 640,
  36. .vl_height = 480,
  37. .vl_clkp = CONFIG_SYS_HIGH,
  38. .vl_oep = CONFIG_SYS_HIGH,
  39. .vl_hsp = CONFIG_SYS_HIGH,
  40. .vl_vsp = CONFIG_SYS_HIGH,
  41. .vl_dp = CONFIG_SYS_HIGH,
  42. .vl_bpix = LCD_BPP,
  43. .vl_lbw = 0,
  44. .vl_splt = 0,
  45. .vl_clor = 0,
  46. .vl_tft = 1,
  47. .vl_hpw = 40,
  48. .vl_blw = 56,
  49. .vl_elw = 56,
  50. .vl_vpw = 20,
  51. .vl_bfw = 8,
  52. .vl_efw = 8,
  53. };
  54. #endif /* CONFIG_PXA_VIDEO */
  55. /*----------------------------------------------------------------------*/
  56. #ifdef CONFIG_SHARP_LM8V31
  57. # define LCD_BPP LCD_COLOR8
  58. # define LCD_INVERT_COLORS /* Needed for colors to be correct, but why? */
  59. /* you have to set lccr0 and lccr3 (including pcd) */
  60. # define REG_LCCR0 0x0030087C
  61. # define REG_LCCR3 0x0340FF08
  62. vidinfo_t panel_info = {
  63. .vl_col = 640,
  64. .vl_row = 480,
  65. .vl_width = 157,
  66. .vl_height = 118,
  67. .vl_clkp = CONFIG_SYS_HIGH,
  68. .vl_oep = CONFIG_SYS_HIGH,
  69. .vl_hsp = CONFIG_SYS_HIGH,
  70. .vl_vsp = CONFIG_SYS_HIGH,
  71. .vl_dp = CONFIG_SYS_HIGH,
  72. .vl_bpix = LCD_BPP,
  73. .vl_lbw = 0,
  74. .vl_splt = 1,
  75. .vl_clor = 1,
  76. .vl_tft = 0,
  77. .vl_hpw = 1,
  78. .vl_blw = 3,
  79. .vl_elw = 3,
  80. .vl_vpw = 1,
  81. .vl_bfw = 0,
  82. .vl_efw = 0,
  83. };
  84. #endif /* CONFIG_SHARP_LM8V31 */
  85. /*----------------------------------------------------------------------*/
  86. #ifdef CONFIG_VOIPAC_LCD
  87. # define LCD_BPP LCD_COLOR8
  88. # define LCD_INVERT_COLORS
  89. /* you have to set lccr0 and lccr3 (including pcd) */
  90. # define REG_LCCR0 0x043008f8
  91. # define REG_LCCR3 0x0340FF08
  92. vidinfo_t panel_info = {
  93. .vl_col = 640,
  94. .vl_row = 480,
  95. .vl_width = 157,
  96. .vl_height = 118,
  97. .vl_clkp = CONFIG_SYS_HIGH,
  98. .vl_oep = CONFIG_SYS_HIGH,
  99. .vl_hsp = CONFIG_SYS_HIGH,
  100. .vl_vsp = CONFIG_SYS_HIGH,
  101. .vl_dp = CONFIG_SYS_HIGH,
  102. .vl_bpix = LCD_BPP,
  103. .vl_lbw = 0,
  104. .vl_splt = 1,
  105. .vl_clor = 1,
  106. .vl_tft = 1,
  107. .vl_hpw = 32,
  108. .vl_blw = 144,
  109. .vl_elw = 32,
  110. .vl_vpw = 2,
  111. .vl_bfw = 13,
  112. .vl_efw = 30,
  113. };
  114. #endif /* CONFIG_VOIPAC_LCD */
  115. /*----------------------------------------------------------------------*/
  116. #ifdef CONFIG_HITACHI_SX14
  117. /* Hitachi SX14Q004-ZZA color STN LCD */
  118. #define LCD_BPP LCD_COLOR8
  119. /* you have to set lccr0 and lccr3 (including pcd) */
  120. #define REG_LCCR0 0x00301079
  121. #define REG_LCCR3 0x0340FF20
  122. vidinfo_t panel_info = {
  123. .vl_col = 320,
  124. .vl_row = 240,
  125. .vl_width = 167,
  126. .vl_height = 109,
  127. .vl_clkp = CONFIG_SYS_HIGH,
  128. .vl_oep = CONFIG_SYS_HIGH,
  129. .vl_hsp = CONFIG_SYS_HIGH,
  130. .vl_vsp = CONFIG_SYS_HIGH,
  131. .vl_dp = CONFIG_SYS_HIGH,
  132. .vl_bpix = LCD_BPP,
  133. .vl_lbw = 1,
  134. .vl_splt = 0,
  135. .vl_clor = 1,
  136. .vl_tft = 0,
  137. .vl_hpw = 1,
  138. .vl_blw = 1,
  139. .vl_elw = 1,
  140. .vl_vpw = 7,
  141. .vl_bfw = 0,
  142. .vl_efw = 0,
  143. };
  144. #endif /* CONFIG_HITACHI_SX14 */
  145. /*----------------------------------------------------------------------*/
  146. #ifdef CONFIG_LMS283GF05
  147. # define LCD_BPP LCD_COLOR8
  148. /*# define LCD_INVERT_COLORS*/
  149. /* you have to set lccr0 and lccr3 (including pcd) */
  150. # define REG_LCCR0 0x043008f8
  151. # define REG_LCCR3 0x03b00009
  152. vidinfo_t panel_info = {
  153. .vl_col = 240,
  154. .vl_row = 320,
  155. .vl_rot = 3,
  156. .vl_width = 240,
  157. .vl_height = 320,
  158. .vl_clkp = CONFIG_SYS_HIGH,
  159. .vl_oep = CONFIG_SYS_LOW,
  160. .vl_hsp = CONFIG_SYS_LOW,
  161. .vl_vsp = CONFIG_SYS_LOW,
  162. .vl_dp = CONFIG_SYS_HIGH,
  163. .vl_bpix = LCD_BPP,
  164. .vl_lbw = 0,
  165. .vl_splt = 1,
  166. .vl_clor = 1,
  167. .vl_tft = 1,
  168. .vl_hpw = 4,
  169. .vl_blw = 4,
  170. .vl_elw = 8,
  171. .vl_vpw = 4,
  172. .vl_bfw = 4,
  173. .vl_efw = 8,
  174. };
  175. #endif /* CONFIG_LMS283GF05 */
  176. /*----------------------------------------------------------------------*/
  177. #ifdef CONFIG_ACX517AKN
  178. # define LCD_BPP LCD_COLOR8
  179. /* you have to set lccr0 and lccr3 (including pcd) */
  180. # define REG_LCCR0 0x003008f9
  181. # define REG_LCCR3 0x03700006
  182. vidinfo_t panel_info = {
  183. .vl_col = 320,
  184. .vl_row = 320,
  185. .vl_width = 320,
  186. .vl_height = 320,
  187. .vl_clkp = CONFIG_SYS_HIGH,
  188. .vl_oep = CONFIG_SYS_LOW,
  189. .vl_hsp = CONFIG_SYS_LOW,
  190. .vl_vsp = CONFIG_SYS_LOW,
  191. .vl_dp = CONFIG_SYS_HIGH,
  192. .vl_bpix = LCD_BPP,
  193. .vl_lbw = 0,
  194. .vl_splt = 1,
  195. .vl_clor = 1,
  196. .vl_tft = 1,
  197. .vl_hpw = 0x04,
  198. .vl_blw = 0x1c,
  199. .vl_elw = 0x08,
  200. .vl_vpw = 0x01,
  201. .vl_bfw = 0x07,
  202. .vl_efw = 0x08,
  203. };
  204. #endif /* CONFIG_ACX517AKN */
  205. #ifdef CONFIG_ACX544AKN
  206. # define LCD_BPP LCD_COLOR16
  207. /* you have to set lccr0 and lccr3 (including pcd) */
  208. # define REG_LCCR0 0x003008f9
  209. # define REG_LCCR3 0x04700007 /* 16bpp */
  210. vidinfo_t panel_info = {
  211. .vl_col = 320,
  212. .vl_row = 320,
  213. .vl_width = 320,
  214. .vl_height = 320,
  215. .vl_clkp = CONFIG_SYS_LOW,
  216. .vl_oep = CONFIG_SYS_LOW,
  217. .vl_hsp = CONFIG_SYS_LOW,
  218. .vl_vsp = CONFIG_SYS_LOW,
  219. .vl_dp = CONFIG_SYS_LOW,
  220. .vl_bpix = LCD_BPP,
  221. .vl_lbw = 0,
  222. .vl_splt = 0,
  223. .vl_clor = 1,
  224. .vl_tft = 1,
  225. .vl_hpw = 0x05,
  226. .vl_blw = 0x13,
  227. .vl_elw = 0x08,
  228. .vl_vpw = 0x02,
  229. .vl_bfw = 0x07,
  230. .vl_efw = 0x05,
  231. };
  232. #endif /* CONFIG_ACX544AKN */
  233. /*----------------------------------------------------------------------*/
  234. #ifdef CONFIG_LQ038J7DH53
  235. # define LCD_BPP LCD_COLOR8
  236. /* you have to set lccr0 and lccr3 (including pcd) */
  237. # define REG_LCCR0 0x003008f9
  238. # define REG_LCCR3 0x03700004
  239. vidinfo_t panel_info = {
  240. .vl_col = 320,
  241. .vl_row = 480,
  242. .vl_width = 320,
  243. .vl_height = 480,
  244. .vl_clkp = CONFIG_SYS_HIGH,
  245. .vl_oep = CONFIG_SYS_LOW,
  246. .vl_hsp = CONFIG_SYS_LOW,
  247. .vl_vsp = CONFIG_SYS_LOW,
  248. .vl_dp = CONFIG_SYS_HIGH,
  249. .vl_bpix = LCD_BPP,
  250. .vl_lbw = 0,
  251. .vl_splt = 1,
  252. .vl_clor = 1,
  253. .vl_tft = 1,
  254. .vl_hpw = 0x04,
  255. .vl_blw = 0x20,
  256. .vl_elw = 0x01,
  257. .vl_vpw = 0x01,
  258. .vl_bfw = 0x04,
  259. .vl_efw = 0x01,
  260. };
  261. #endif /* CONFIG_ACX517AKN */
  262. /*----------------------------------------------------------------------*/
  263. #ifdef CONFIG_LITTLETON_LCD
  264. # define LCD_BPP LCD_COLOR8
  265. /* you have to set lccr0 and lccr3 (including pcd) */
  266. # define REG_LCCR0 0x003008f8
  267. # define REG_LCCR3 0x0300FF04
  268. vidinfo_t panel_info = {
  269. .vl_col = 480,
  270. .vl_row = 640,
  271. .vl_width = 480,
  272. .vl_height = 640,
  273. .vl_clkp = CONFIG_SYS_HIGH,
  274. .vl_oep = CONFIG_SYS_HIGH,
  275. .vl_hsp = CONFIG_SYS_HIGH,
  276. .vl_vsp = CONFIG_SYS_HIGH,
  277. .vl_dp = CONFIG_SYS_HIGH,
  278. .vl_bpix = LCD_BPP,
  279. .vl_lbw = 0,
  280. .vl_splt = 0,
  281. .vl_clor = 0,
  282. .vl_tft = 1,
  283. .vl_hpw = 9,
  284. .vl_blw = 8,
  285. .vl_elw = 24,
  286. .vl_vpw = 2,
  287. .vl_bfw = 2,
  288. .vl_efw = 4,
  289. };
  290. #endif /* CONFIG_LITTLETON_LCD */
  291. /*----------------------------------------------------------------------*/
  292. static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid);
  293. static void pxafb_setup_gpio (vidinfo_t *vid);
  294. static void pxafb_enable_controller (vidinfo_t *vid);
  295. static int pxafb_init (vidinfo_t *vid);
  296. /************************************************************************/
  297. /* --------------- PXA chipset specific functions ------------------- */
  298. /************************************************************************/
  299. ushort *configuration_get_cmap(void)
  300. {
  301. struct pxafb_info *fbi = &panel_info.pxa;
  302. return (ushort *)fbi->palette;
  303. }
  304. void lcd_ctrl_init (void *lcdbase)
  305. {
  306. pxafb_init_mem(lcdbase, &panel_info);
  307. pxafb_init(&panel_info);
  308. pxafb_setup_gpio(&panel_info);
  309. pxafb_enable_controller(&panel_info);
  310. }
  311. /*----------------------------------------------------------------------*/
  312. #if LCD_BPP == LCD_COLOR8
  313. void
  314. lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
  315. {
  316. struct pxafb_info *fbi = &panel_info.pxa;
  317. unsigned short *palette = (unsigned short *)fbi->palette;
  318. u_int val;
  319. if (regno < fbi->palette_size) {
  320. val = ((red << 8) & 0xf800);
  321. val |= ((green << 4) & 0x07e0);
  322. val |= (blue & 0x001f);
  323. #ifdef LCD_INVERT_COLORS
  324. palette[regno] = ~val;
  325. #else
  326. palette[regno] = val;
  327. #endif
  328. }
  329. debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %04X\n",
  330. regno, &palette[regno],
  331. red, green, blue,
  332. palette[regno]);
  333. }
  334. #endif /* LCD_COLOR8 */
  335. /*----------------------------------------------------------------------*/
  336. __weak void lcd_enable(void)
  337. {
  338. }
  339. /************************************************************************/
  340. /* ** PXA255 specific routines */
  341. /************************************************************************/
  342. /*
  343. * Calculate fb size for VIDEOLFB_ATAG. Size returned contains fb,
  344. * descriptors and palette areas.
  345. */
  346. ulong calc_fbsize (void)
  347. {
  348. ulong size;
  349. int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
  350. size = line_length * panel_info.vl_row;
  351. size += PAGE_SIZE;
  352. return size;
  353. }
  354. static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid)
  355. {
  356. u_long palette_mem_size;
  357. struct pxafb_info *fbi = &vid->pxa;
  358. int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
  359. fbi->screen = (u_long)lcdbase;
  360. fbi->palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16;
  361. palette_mem_size = fbi->palette_size * sizeof(u16);
  362. debug("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
  363. /* locate palette and descs at end of page following fb */
  364. fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
  365. return 0;
  366. }
  367. #ifdef CONFIG_CPU_MONAHANS
  368. static inline void pxafb_setup_gpio (vidinfo_t *vid) {}
  369. #else
  370. static void pxafb_setup_gpio (vidinfo_t *vid)
  371. {
  372. u_long lccr0;
  373. /*
  374. * setup is based on type of panel supported
  375. */
  376. lccr0 = vid->pxa.reg_lccr0;
  377. /* 4 bit interface */
  378. if ((lccr0 & LCCR0_CMS) && (lccr0 & LCCR0_SDS) && !(lccr0 & LCCR0_DPD))
  379. {
  380. debug("Setting GPIO for 4 bit data\n");
  381. /* bits 58-61 */
  382. writel(readl(GPDR1) | (0xf << 26), GPDR1);
  383. writel((readl(GAFR1_U) & ~(0xff << 20)) | (0xaa << 20),
  384. GAFR1_U);
  385. /* bits 74-77 */
  386. writel(readl(GPDR2) | (0xf << 10), GPDR2);
  387. writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
  388. GAFR2_L);
  389. }
  390. /* 8 bit interface */
  391. else if (((lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_DPD))) ||
  392. (!(lccr0 & LCCR0_CMS) && !(lccr0 & LCCR0_PAS) && !(lccr0 & LCCR0_SDS)))
  393. {
  394. debug("Setting GPIO for 8 bit data\n");
  395. /* bits 58-65 */
  396. writel(readl(GPDR1) | (0x3f << 26), GPDR1);
  397. writel(readl(GPDR2) | (0x3), GPDR2);
  398. writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
  399. GAFR1_U);
  400. writel((readl(GAFR2_L) & ~0xf) | (0xa), GAFR2_L);
  401. /* bits 74-77 */
  402. writel(readl(GPDR2) | (0xf << 10), GPDR2);
  403. writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
  404. GAFR2_L);
  405. }
  406. /* 16 bit interface */
  407. else if (!(lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_PAS)))
  408. {
  409. debug("Setting GPIO for 16 bit data\n");
  410. /* bits 58-77 */
  411. writel(readl(GPDR1) | (0x3f << 26), GPDR1);
  412. writel(readl(GPDR2) | 0x00003fff, GPDR2);
  413. writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
  414. GAFR1_U);
  415. writel((readl(GAFR2_L) & 0xf0000000) | 0x0aaaaaaa, GAFR2_L);
  416. }
  417. else
  418. {
  419. printf("pxafb_setup_gpio: unable to determine bits per pixel\n");
  420. }
  421. }
  422. #endif
  423. static void pxafb_enable_controller (vidinfo_t *vid)
  424. {
  425. debug("Enabling LCD controller\n");
  426. /* Sequence from 11.7.10 */
  427. writel(vid->pxa.reg_lccr3, LCCR3);
  428. writel(vid->pxa.reg_lccr2, LCCR2);
  429. writel(vid->pxa.reg_lccr1, LCCR1);
  430. writel(vid->pxa.reg_lccr0 & ~LCCR0_ENB, LCCR0);
  431. writel(vid->pxa.fdadr0, FDADR0);
  432. writel(vid->pxa.fdadr1, FDADR1);
  433. writel(readl(LCCR0) | LCCR0_ENB, LCCR0);
  434. #ifdef CONFIG_CPU_MONAHANS
  435. writel(readl(CKENA) | CKENA_1_LCD, CKENA);
  436. #else
  437. writel(readl(CKEN) | CKEN16_LCD, CKEN);
  438. #endif
  439. debug("FDADR0 = 0x%08x\n", readl(FDADR0));
  440. debug("FDADR1 = 0x%08x\n", readl(FDADR1));
  441. debug("LCCR0 = 0x%08x\n", readl(LCCR0));
  442. debug("LCCR1 = 0x%08x\n", readl(LCCR1));
  443. debug("LCCR2 = 0x%08x\n", readl(LCCR2));
  444. debug("LCCR3 = 0x%08x\n", readl(LCCR3));
  445. }
  446. static int pxafb_init (vidinfo_t *vid)
  447. {
  448. struct pxafb_info *fbi = &vid->pxa;
  449. debug("Configuring PXA LCD\n");
  450. fbi->reg_lccr0 = REG_LCCR0;
  451. fbi->reg_lccr3 = REG_LCCR3;
  452. debug("vid: vl_col=%d hslen=%d lm=%d rm=%d\n",
  453. vid->vl_col, vid->vl_hpw,
  454. vid->vl_blw, vid->vl_elw);
  455. debug("vid: vl_row=%d vslen=%d um=%d bm=%d\n",
  456. vid->vl_row, vid->vl_vpw,
  457. vid->vl_bfw, vid->vl_efw);
  458. fbi->reg_lccr1 =
  459. LCCR1_DisWdth(vid->vl_col) +
  460. LCCR1_HorSnchWdth(vid->vl_hpw) +
  461. LCCR1_BegLnDel(vid->vl_blw) +
  462. LCCR1_EndLnDel(vid->vl_elw);
  463. fbi->reg_lccr2 =
  464. LCCR2_DisHght(vid->vl_row) +
  465. LCCR2_VrtSnchWdth(vid->vl_vpw) +
  466. LCCR2_BegFrmDel(vid->vl_bfw) +
  467. LCCR2_EndFrmDel(vid->vl_efw);
  468. fbi->reg_lccr3 = REG_LCCR3 & ~(LCCR3_HSP | LCCR3_VSP);
  469. fbi->reg_lccr3 |= (vid->vl_hsp ? LCCR3_HorSnchL : LCCR3_HorSnchH)
  470. | (vid->vl_vsp ? LCCR3_VrtSnchL : LCCR3_VrtSnchH);
  471. /* setup dma descriptors */
  472. fbi->dmadesc_fblow = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
  473. fbi->dmadesc_fbhigh = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
  474. fbi->dmadesc_palette = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
  475. #define BYTES_PER_PANEL ((fbi->reg_lccr0 & LCCR0_SDS) ? \
  476. (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8 / 2) : \
  477. (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8))
  478. /* populate descriptors */
  479. fbi->dmadesc_fblow->fdadr = (u_long)fbi->dmadesc_fblow;
  480. fbi->dmadesc_fblow->fsadr = fbi->screen + BYTES_PER_PANEL;
  481. fbi->dmadesc_fblow->fidr = 0;
  482. fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL;
  483. fbi->fdadr1 = (u_long)fbi->dmadesc_fblow; /* only used in dual-panel mode */
  484. fbi->dmadesc_fbhigh->fsadr = fbi->screen;
  485. fbi->dmadesc_fbhigh->fidr = 0;
  486. fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL;
  487. fbi->dmadesc_palette->fsadr = fbi->palette;
  488. fbi->dmadesc_palette->fidr = 0;
  489. fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL;
  490. if( NBITS(vid->vl_bpix) < 12)
  491. {
  492. /* assume any mode with <12 bpp is palette driven */
  493. fbi->dmadesc_palette->fdadr = (u_long)fbi->dmadesc_fbhigh;
  494. fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_palette;
  495. /* flips back and forth between pal and fbhigh */
  496. fbi->fdadr0 = (u_long)fbi->dmadesc_palette;
  497. }
  498. else
  499. {
  500. /* palette shouldn't be loaded in true-color mode */
  501. fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_fbhigh;
  502. fbi->fdadr0 = (u_long)fbi->dmadesc_fbhigh; /* no pal just fbhigh */
  503. }
  504. debug("fbi->dmadesc_fblow = 0x%lx\n", (u_long)fbi->dmadesc_fblow);
  505. debug("fbi->dmadesc_fbhigh = 0x%lx\n", (u_long)fbi->dmadesc_fbhigh);
  506. debug("fbi->dmadesc_palette = 0x%lx\n", (u_long)fbi->dmadesc_palette);
  507. debug("fbi->dmadesc_fblow->fdadr = 0x%lx\n", fbi->dmadesc_fblow->fdadr);
  508. debug("fbi->dmadesc_fbhigh->fdadr = 0x%lx\n", fbi->dmadesc_fbhigh->fdadr);
  509. debug("fbi->dmadesc_palette->fdadr = 0x%lx\n", fbi->dmadesc_palette->fdadr);
  510. debug("fbi->dmadesc_fblow->fsadr = 0x%lx\n", fbi->dmadesc_fblow->fsadr);
  511. debug("fbi->dmadesc_fbhigh->fsadr = 0x%lx\n", fbi->dmadesc_fbhigh->fsadr);
  512. debug("fbi->dmadesc_palette->fsadr = 0x%lx\n", fbi->dmadesc_palette->fsadr);
  513. debug("fbi->dmadesc_fblow->ldcmd = 0x%lx\n", fbi->dmadesc_fblow->ldcmd);
  514. debug("fbi->dmadesc_fbhigh->ldcmd = 0x%lx\n", fbi->dmadesc_fbhigh->ldcmd);
  515. debug("fbi->dmadesc_palette->ldcmd = 0x%lx\n", fbi->dmadesc_palette->ldcmd);
  516. return 0;
  517. }
  518. /************************************************************************/
  519. /************************************************************************/
  520. #endif /* CONFIG_LCD */