orisetech_otm8009a.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2019 STMicroelectronics - All Rights Reserved
  4. * Author(s): Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
  5. * Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
  6. *
  7. * This otm8009a panel driver is inspired from the Linux Kernel driver
  8. * drivers/gpu/drm/panel/panel-orisetech-otm8009a.c.
  9. */
  10. #include <common.h>
  11. #include <backlight.h>
  12. #include <dm.h>
  13. #include <mipi_dsi.h>
  14. #include <panel.h>
  15. #include <asm/gpio.h>
  16. #include <dm/device_compat.h>
  17. #include <power/regulator.h>
  18. #define OTM8009A_BACKLIGHT_DEFAULT 240
  19. #define OTM8009A_BACKLIGHT_MAX 255
  20. /* Manufacturer Command Set */
  21. #define MCS_ADRSFT 0x0000 /* Address Shift Function */
  22. #define MCS_PANSET 0xB3A6 /* Panel Type Setting */
  23. #define MCS_SD_CTRL 0xC0A2 /* Source Driver Timing Setting */
  24. #define MCS_P_DRV_M 0xC0B4 /* Panel Driving Mode */
  25. #define MCS_OSC_ADJ 0xC181 /* Oscillator Adjustment for Idle/Normal mode */
  26. #define MCS_RGB_VID_SET 0xC1A1 /* RGB Video Mode Setting */
  27. #define MCS_SD_PCH_CTRL 0xC480 /* Source Driver Precharge Control */
  28. #define MCS_NO_DOC1 0xC48A /* Command not documented */
  29. #define MCS_PWR_CTRL1 0xC580 /* Power Control Setting 1 */
  30. #define MCS_PWR_CTRL2 0xC590 /* Power Control Setting 2 for Normal Mode */
  31. #define MCS_PWR_CTRL4 0xC5B0 /* Power Control Setting 4 for DC Voltage */
  32. #define MCS_PANCTRLSET1 0xCB80 /* Panel Control Setting 1 */
  33. #define MCS_PANCTRLSET2 0xCB90 /* Panel Control Setting 2 */
  34. #define MCS_PANCTRLSET3 0xCBA0 /* Panel Control Setting 3 */
  35. #define MCS_PANCTRLSET4 0xCBB0 /* Panel Control Setting 4 */
  36. #define MCS_PANCTRLSET5 0xCBC0 /* Panel Control Setting 5 */
  37. #define MCS_PANCTRLSET6 0xCBD0 /* Panel Control Setting 6 */
  38. #define MCS_PANCTRLSET7 0xCBE0 /* Panel Control Setting 7 */
  39. #define MCS_PANCTRLSET8 0xCBF0 /* Panel Control Setting 8 */
  40. #define MCS_PANU2D1 0xCC80 /* Panel U2D Setting 1 */
  41. #define MCS_PANU2D2 0xCC90 /* Panel U2D Setting 2 */
  42. #define MCS_PANU2D3 0xCCA0 /* Panel U2D Setting 3 */
  43. #define MCS_PAND2U1 0xCCB0 /* Panel D2U Setting 1 */
  44. #define MCS_PAND2U2 0xCCC0 /* Panel D2U Setting 2 */
  45. #define MCS_PAND2U3 0xCCD0 /* Panel D2U Setting 3 */
  46. #define MCS_GOAVST 0xCE80 /* GOA VST Setting */
  47. #define MCS_GOACLKA1 0xCEA0 /* GOA CLKA1 Setting */
  48. #define MCS_GOACLKA3 0xCEB0 /* GOA CLKA3 Setting */
  49. #define MCS_GOAECLK 0xCFC0 /* GOA ECLK Setting */
  50. #define MCS_NO_DOC2 0xCFD0 /* Command not documented */
  51. #define MCS_GVDDSET 0xD800 /* GVDD/NGVDD */
  52. #define MCS_VCOMDC 0xD900 /* VCOM Voltage Setting */
  53. #define MCS_GMCT2_2P 0xE100 /* Gamma Correction 2.2+ Setting */
  54. #define MCS_GMCT2_2N 0xE200 /* Gamma Correction 2.2- Setting */
  55. #define MCS_NO_DOC3 0xF5B6 /* Command not documented */
  56. #define MCS_CMD2_ENA1 0xFF00 /* Enable Access Command2 "CMD2" */
  57. #define MCS_CMD2_ENA2 0xFF80 /* Enable Access Orise Command2 */
  58. struct otm8009a_panel_priv {
  59. struct udevice *reg;
  60. struct gpio_desc reset;
  61. unsigned int lanes;
  62. enum mipi_dsi_pixel_format format;
  63. unsigned long mode_flags;
  64. };
  65. static const struct display_timing default_timing = {
  66. .pixelclock.typ = 29700000,
  67. .hactive.typ = 480,
  68. .hfront_porch.typ = 98,
  69. .hback_porch.typ = 98,
  70. .hsync_len.typ = 32,
  71. .vactive.typ = 800,
  72. .vfront_porch.typ = 15,
  73. .vback_porch.typ = 14,
  74. .vsync_len.typ = 10,
  75. };
  76. static void otm8009a_dcs_write_buf(struct udevice *dev, const void *data,
  77. size_t len)
  78. {
  79. struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
  80. struct mipi_dsi_device *device = plat->device;
  81. if (mipi_dsi_dcs_write_buffer(device, data, len) < 0)
  82. dev_err(dev, "mipi dsi dcs write buffer failed\n");
  83. }
  84. static void otm8009a_dcs_write_buf_hs(struct udevice *dev, const void *data,
  85. size_t len)
  86. {
  87. struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
  88. struct mipi_dsi_device *device = plat->device;
  89. /* data will be sent in dsi hs mode (ie. no lpm) */
  90. device->mode_flags &= ~MIPI_DSI_MODE_LPM;
  91. if (mipi_dsi_dcs_write_buffer(device, data, len) < 0)
  92. dev_err(dev, "mipi dsi dcs write buffer failed\n");
  93. /* restore back the dsi lpm mode */
  94. device->mode_flags |= MIPI_DSI_MODE_LPM;
  95. }
  96. #define dcs_write_seq(dev, seq...) \
  97. ({ \
  98. static const u8 d[] = { seq }; \
  99. otm8009a_dcs_write_buf(dev, d, ARRAY_SIZE(d)); \
  100. })
  101. #define dcs_write_seq_hs(dev, seq...) \
  102. ({ \
  103. static const u8 d[] = { seq }; \
  104. otm8009a_dcs_write_buf_hs(dev, d, ARRAY_SIZE(d)); \
  105. })
  106. #define dcs_write_cmd_at(dev, cmd, seq...) \
  107. ({ \
  108. static const u16 c = cmd; \
  109. struct udevice *device = dev; \
  110. dcs_write_seq(device, MCS_ADRSFT, (c) & 0xFF); \
  111. dcs_write_seq(device, (c) >> 8, seq); \
  112. })
  113. static int otm8009a_init_sequence(struct udevice *dev)
  114. {
  115. struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
  116. struct mipi_dsi_device *device = plat->device;
  117. int ret;
  118. /* Enter CMD2 */
  119. dcs_write_cmd_at(dev, MCS_CMD2_ENA1, 0x80, 0x09, 0x01);
  120. /* Enter Orise Command2 */
  121. dcs_write_cmd_at(dev, MCS_CMD2_ENA2, 0x80, 0x09);
  122. dcs_write_cmd_at(dev, MCS_SD_PCH_CTRL, 0x30);
  123. mdelay(10);
  124. dcs_write_cmd_at(dev, MCS_NO_DOC1, 0x40);
  125. mdelay(10);
  126. dcs_write_cmd_at(dev, MCS_PWR_CTRL4 + 1, 0xA9);
  127. dcs_write_cmd_at(dev, MCS_PWR_CTRL2 + 1, 0x34);
  128. dcs_write_cmd_at(dev, MCS_P_DRV_M, 0x50);
  129. dcs_write_cmd_at(dev, MCS_VCOMDC, 0x4E);
  130. dcs_write_cmd_at(dev, MCS_OSC_ADJ, 0x66); /* 65Hz */
  131. dcs_write_cmd_at(dev, MCS_PWR_CTRL2 + 2, 0x01);
  132. dcs_write_cmd_at(dev, MCS_PWR_CTRL2 + 5, 0x34);
  133. dcs_write_cmd_at(dev, MCS_PWR_CTRL2 + 4, 0x33);
  134. dcs_write_cmd_at(dev, MCS_GVDDSET, 0x79, 0x79);
  135. dcs_write_cmd_at(dev, MCS_SD_CTRL + 1, 0x1B);
  136. dcs_write_cmd_at(dev, MCS_PWR_CTRL1 + 2, 0x83);
  137. dcs_write_cmd_at(dev, MCS_SD_PCH_CTRL + 1, 0x83);
  138. dcs_write_cmd_at(dev, MCS_RGB_VID_SET, 0x0E);
  139. dcs_write_cmd_at(dev, MCS_PANSET, 0x00, 0x01);
  140. dcs_write_cmd_at(dev, MCS_GOAVST, 0x85, 0x01, 0x00, 0x84, 0x01, 0x00);
  141. dcs_write_cmd_at(dev, MCS_GOACLKA1, 0x18, 0x04, 0x03, 0x39, 0x00, 0x00,
  142. 0x00, 0x18, 0x03, 0x03, 0x3A, 0x00, 0x00, 0x00);
  143. dcs_write_cmd_at(dev, MCS_GOACLKA3, 0x18, 0x02, 0x03, 0x3B, 0x00, 0x00,
  144. 0x00, 0x18, 0x01, 0x03, 0x3C, 0x00, 0x00, 0x00);
  145. dcs_write_cmd_at(dev, MCS_GOAECLK, 0x01, 0x01, 0x20, 0x20, 0x00, 0x00,
  146. 0x01, 0x02, 0x00, 0x00);
  147. dcs_write_cmd_at(dev, MCS_NO_DOC2, 0x00);
  148. dcs_write_cmd_at(dev, MCS_PANCTRLSET1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
  149. dcs_write_cmd_at(dev, MCS_PANCTRLSET2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  150. 0, 0, 0, 0, 0);
  151. dcs_write_cmd_at(dev, MCS_PANCTRLSET3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  152. 0, 0, 0, 0, 0);
  153. dcs_write_cmd_at(dev, MCS_PANCTRLSET4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
  154. dcs_write_cmd_at(dev, MCS_PANCTRLSET5, 0, 4, 4, 4, 4, 4, 0, 0, 0, 0,
  155. 0, 0, 0, 0, 0);
  156. dcs_write_cmd_at(dev, MCS_PANCTRLSET6, 0, 0, 0, 0, 0, 0, 4, 4, 4, 4,
  157. 4, 0, 0, 0, 0);
  158. dcs_write_cmd_at(dev, MCS_PANCTRLSET7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
  159. dcs_write_cmd_at(dev, MCS_PANCTRLSET8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
  160. 0xFF, 0xFF, 0xFF, 0xFF, 0xFF);
  161. dcs_write_cmd_at(dev, MCS_PANU2D1, 0x00, 0x26, 0x09, 0x0B, 0x01, 0x25,
  162. 0x00, 0x00, 0x00, 0x00);
  163. dcs_write_cmd_at(dev, MCS_PANU2D2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  164. 0x00, 0x00, 0x00, 0x00, 0x00, 0x26, 0x0A, 0x0C, 0x02);
  165. dcs_write_cmd_at(dev, MCS_PANU2D3, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00,
  166. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
  167. dcs_write_cmd_at(dev, MCS_PAND2U1, 0x00, 0x25, 0x0C, 0x0A, 0x02, 0x26,
  168. 0x00, 0x00, 0x00, 0x00);
  169. dcs_write_cmd_at(dev, MCS_PAND2U2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  170. 0x00, 0x00, 0x00, 0x00, 0x00, 0x25, 0x0B, 0x09, 0x01);
  171. dcs_write_cmd_at(dev, MCS_PAND2U3, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00,
  172. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
  173. dcs_write_cmd_at(dev, MCS_PWR_CTRL1 + 1, 0x66);
  174. dcs_write_cmd_at(dev, MCS_NO_DOC3, 0x06);
  175. dcs_write_cmd_at(dev, MCS_GMCT2_2P, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10,
  176. 0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A,
  177. 0x01);
  178. dcs_write_cmd_at(dev, MCS_GMCT2_2N, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10,
  179. 0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A,
  180. 0x01);
  181. /* Exit CMD2 */
  182. dcs_write_cmd_at(dev, MCS_CMD2_ENA1, 0xFF, 0xFF, 0xFF);
  183. ret = mipi_dsi_dcs_nop(device);
  184. if (ret)
  185. return ret;
  186. ret = mipi_dsi_dcs_exit_sleep_mode(device);
  187. if (ret)
  188. return ret;
  189. /* Wait for sleep out exit */
  190. mdelay(120);
  191. /* Default portrait 480x800 rgb24 */
  192. dcs_write_seq(dev, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
  193. ret = mipi_dsi_dcs_set_column_address(device, 0,
  194. default_timing.hactive.typ - 1);
  195. if (ret)
  196. return ret;
  197. ret = mipi_dsi_dcs_set_page_address(device, 0,
  198. default_timing.vactive.typ - 1);
  199. if (ret)
  200. return ret;
  201. /* See otm8009a driver documentation for pixel format descriptions */
  202. ret = mipi_dsi_dcs_set_pixel_format(device, MIPI_DCS_PIXEL_FMT_24BIT |
  203. MIPI_DCS_PIXEL_FMT_24BIT << 4);
  204. if (ret)
  205. return ret;
  206. /* Disable CABC feature */
  207. dcs_write_seq(dev, MIPI_DCS_WRITE_POWER_SAVE, 0x00);
  208. ret = mipi_dsi_dcs_set_display_on(device);
  209. if (ret)
  210. return ret;
  211. ret = mipi_dsi_dcs_nop(device);
  212. if (ret)
  213. return ret;
  214. /* Send Command GRAM memory write (no parameters) */
  215. dcs_write_seq(dev, MIPI_DCS_WRITE_MEMORY_START);
  216. return 0;
  217. }
  218. static int otm8009a_panel_enable_backlight(struct udevice *dev)
  219. {
  220. struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
  221. struct mipi_dsi_device *device = plat->device;
  222. int ret;
  223. ret = mipi_dsi_attach(device);
  224. if (ret < 0)
  225. return ret;
  226. ret = otm8009a_init_sequence(dev);
  227. if (ret)
  228. return ret;
  229. /*
  230. * Power on the backlight with the requested brightness
  231. * Note We can not use mipi_dsi_dcs_set_display_brightness()
  232. * as otm8009a driver support only 8-bit brightness (1 param).
  233. */
  234. dcs_write_seq(dev, MIPI_DCS_SET_DISPLAY_BRIGHTNESS,
  235. OTM8009A_BACKLIGHT_DEFAULT);
  236. /* Update Brightness Control & Backlight */
  237. dcs_write_seq(dev, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x24);
  238. /* Update Brightness Control & Backlight */
  239. dcs_write_seq_hs(dev, MIPI_DCS_WRITE_CONTROL_DISPLAY);
  240. /* Need to wait a few time before sending the first image */
  241. mdelay(10);
  242. return 0;
  243. }
  244. static int otm8009a_panel_get_display_timing(struct udevice *dev,
  245. struct display_timing *timings)
  246. {
  247. struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
  248. struct mipi_dsi_device *device = plat->device;
  249. struct otm8009a_panel_priv *priv = dev_get_priv(dev);
  250. memcpy(timings, &default_timing, sizeof(*timings));
  251. /* fill characteristics of DSI data link */
  252. device->lanes = priv->lanes;
  253. device->format = priv->format;
  254. device->mode_flags = priv->mode_flags;
  255. return 0;
  256. }
  257. static int otm8009a_panel_ofdata_to_platdata(struct udevice *dev)
  258. {
  259. struct otm8009a_panel_priv *priv = dev_get_priv(dev);
  260. int ret;
  261. if (IS_ENABLED(CONFIG_DM_REGULATOR)) {
  262. ret = device_get_supply_regulator(dev, "power-supply",
  263. &priv->reg);
  264. if (ret && ret != -ENOENT) {
  265. dev_err(dev, "Warning: cannot get power supply\n");
  266. return ret;
  267. }
  268. }
  269. ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset,
  270. GPIOD_IS_OUT);
  271. if (ret) {
  272. dev_err(dev, "warning: cannot get reset GPIO\n");
  273. if (ret != -ENOENT)
  274. return ret;
  275. }
  276. return 0;
  277. }
  278. static int otm8009a_panel_probe(struct udevice *dev)
  279. {
  280. struct otm8009a_panel_priv *priv = dev_get_priv(dev);
  281. int ret;
  282. if (IS_ENABLED(CONFIG_DM_REGULATOR) && priv->reg) {
  283. dev_dbg(dev, "enable regulator '%s'\n", priv->reg->name);
  284. ret = regulator_set_enable(priv->reg, true);
  285. if (ret)
  286. return ret;
  287. }
  288. /* reset panel */
  289. dm_gpio_set_value(&priv->reset, true);
  290. mdelay(1); /* >50us */
  291. dm_gpio_set_value(&priv->reset, false);
  292. mdelay(10); /* >5ms */
  293. priv->lanes = 2;
  294. priv->format = MIPI_DSI_FMT_RGB888;
  295. priv->mode_flags = MIPI_DSI_MODE_VIDEO |
  296. MIPI_DSI_MODE_VIDEO_BURST |
  297. MIPI_DSI_MODE_LPM;
  298. return 0;
  299. }
  300. static const struct panel_ops otm8009a_panel_ops = {
  301. .enable_backlight = otm8009a_panel_enable_backlight,
  302. .get_display_timing = otm8009a_panel_get_display_timing,
  303. };
  304. static const struct udevice_id otm8009a_panel_ids[] = {
  305. { .compatible = "orisetech,otm8009a" },
  306. { }
  307. };
  308. U_BOOT_DRIVER(otm8009a_panel) = {
  309. .name = "otm8009a_panel",
  310. .id = UCLASS_PANEL,
  311. .of_match = otm8009a_panel_ids,
  312. .ops = &otm8009a_panel_ops,
  313. .ofdata_to_platdata = otm8009a_panel_ofdata_to_platdata,
  314. .probe = otm8009a_panel_probe,
  315. .platdata_auto_alloc_size = sizeof(struct mipi_dsi_panel_plat),
  316. .priv_auto_alloc_size = sizeof(struct otm8009a_panel_priv),
  317. };