mxsfb.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale i.MX23/i.MX28 LCDIF driver
  4. *
  5. * Copyright (C) 2011-2013 Marek Vasut <marex@denx.de>
  6. */
  7. #include <common.h>
  8. #include <clk.h>
  9. #include <dm.h>
  10. #include <env.h>
  11. #include <dm/device_compat.h>
  12. #include <linux/errno.h>
  13. #include <malloc.h>
  14. #include <video.h>
  15. #include <video_fb.h>
  16. #include <asm/arch/clock.h>
  17. #include <asm/arch/imx-regs.h>
  18. #include <asm/arch/sys_proto.h>
  19. #include <asm/mach-imx/dma.h>
  20. #include <asm/io.h>
  21. #include "videomodes.h"
  22. #define PS2KHZ(ps) (1000000000UL / (ps))
  23. #define HZ2PS(hz) (1000000000UL / ((hz) / 1000))
  24. #define BITS_PP 18
  25. #define BYTES_PP 4
  26. struct mxs_dma_desc desc;
  27. /**
  28. * mxsfb_system_setup() - Fine-tune LCDIF configuration
  29. *
  30. * This function is used to adjust the LCDIF configuration. This is usually
  31. * needed when driving the controller in System-Mode to operate an 8080 or
  32. * 6800 connected SmartLCD.
  33. */
  34. __weak void mxsfb_system_setup(void)
  35. {
  36. }
  37. /*
  38. * ARIES M28EVK:
  39. * setenv videomode
  40. * video=ctfb:x:800,y:480,depth:18,mode:0,pclk:30066,
  41. * le:0,ri:256,up:0,lo:45,hs:1,vs:1,sync:100663296,vmode:0
  42. *
  43. * Freescale mx23evk/mx28evk with a Seiko 4.3'' WVGA panel:
  44. * setenv videomode
  45. * video=ctfb:x:800,y:480,depth:24,mode:0,pclk:29851,
  46. * le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0
  47. */
  48. static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
  49. struct display_timing *timings, int bpp)
  50. {
  51. struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
  52. const enum display_flags flags = timings->flags;
  53. uint32_t word_len = 0, bus_width = 0;
  54. uint8_t valid_data = 0;
  55. uint32_t vdctrl0;
  56. #if CONFIG_IS_ENABLED(CLK)
  57. struct clk per_clk;
  58. int ret;
  59. ret = clk_get_by_name(dev, "per", &per_clk);
  60. if (ret) {
  61. dev_err(dev, "Failed to get mxs clk: %d\n", ret);
  62. return;
  63. }
  64. ret = clk_set_rate(&per_clk, timings->pixelclock.typ);
  65. if (ret < 0) {
  66. dev_err(dev, "Failed to set mxs clk: %d\n", ret);
  67. return;
  68. }
  69. ret = clk_enable(&per_clk);
  70. if (ret < 0) {
  71. dev_err(dev, "Failed to enable mxs clk: %d\n", ret);
  72. return;
  73. }
  74. #else
  75. /* Kick in the LCDIF clock */
  76. mxs_set_lcdclk(MXS_LCDIF_BASE, timings->pixelclock.typ / 1000);
  77. #endif
  78. /* Restart the LCDIF block */
  79. mxs_reset_block(&regs->hw_lcdif_ctrl_reg);
  80. switch (bpp) {
  81. case 24:
  82. word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
  83. bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT;
  84. valid_data = 0x7;
  85. break;
  86. case 18:
  87. word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
  88. bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT;
  89. valid_data = 0x7;
  90. break;
  91. case 16:
  92. word_len = LCDIF_CTRL_WORD_LENGTH_16BIT;
  93. bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT;
  94. valid_data = 0xf;
  95. break;
  96. case 8:
  97. word_len = LCDIF_CTRL_WORD_LENGTH_8BIT;
  98. bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT;
  99. valid_data = 0xf;
  100. break;
  101. }
  102. writel(bus_width | word_len | LCDIF_CTRL_DOTCLK_MODE |
  103. LCDIF_CTRL_BYPASS_COUNT | LCDIF_CTRL_LCDIF_MASTER,
  104. &regs->hw_lcdif_ctrl);
  105. writel(valid_data << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
  106. &regs->hw_lcdif_ctrl1);
  107. mxsfb_system_setup();
  108. writel((timings->vactive.typ << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) |
  109. timings->hactive.typ, &regs->hw_lcdif_transfer_count);
  110. vdctrl0 = LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL |
  111. LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
  112. LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
  113. timings->vsync_len.typ;
  114. if(flags & DISPLAY_FLAGS_HSYNC_HIGH)
  115. vdctrl0 |= LCDIF_VDCTRL0_HSYNC_POL;
  116. if(flags & DISPLAY_FLAGS_VSYNC_HIGH)
  117. vdctrl0 |= LCDIF_VDCTRL0_VSYNC_POL;
  118. if(flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
  119. vdctrl0 |= LCDIF_VDCTRL0_DOTCLK_POL;
  120. if(flags & DISPLAY_FLAGS_DE_HIGH)
  121. vdctrl0 |= LCDIF_VDCTRL0_ENABLE_POL;
  122. writel(vdctrl0, &regs->hw_lcdif_vdctrl0);
  123. writel(timings->vback_porch.typ + timings->vfront_porch.typ +
  124. timings->vsync_len.typ + timings->vactive.typ,
  125. &regs->hw_lcdif_vdctrl1);
  126. writel((timings->hsync_len.typ << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) |
  127. (timings->hback_porch.typ + timings->hfront_porch.typ +
  128. timings->hsync_len.typ + timings->hactive.typ),
  129. &regs->hw_lcdif_vdctrl2);
  130. writel(((timings->hback_porch.typ + timings->hsync_len.typ) <<
  131. LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) |
  132. (timings->vback_porch.typ + timings->vsync_len.typ),
  133. &regs->hw_lcdif_vdctrl3);
  134. writel((0 << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) | timings->hactive.typ,
  135. &regs->hw_lcdif_vdctrl4);
  136. writel(fb_addr, &regs->hw_lcdif_cur_buf);
  137. writel(fb_addr, &regs->hw_lcdif_next_buf);
  138. /* Flush FIFO first */
  139. writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_set);
  140. #ifndef CONFIG_VIDEO_MXS_MODE_SYSTEM
  141. /* Sync signals ON */
  142. setbits_le32(&regs->hw_lcdif_vdctrl4, LCDIF_VDCTRL4_SYNC_SIGNALS_ON);
  143. #endif
  144. /* FIFO cleared */
  145. writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_clr);
  146. /* RUN! */
  147. writel(LCDIF_CTRL_RUN, &regs->hw_lcdif_ctrl_set);
  148. }
  149. static int mxs_probe_common(struct udevice *dev, struct display_timing *timings,
  150. int bpp, u32 fb)
  151. {
  152. /* Start framebuffer */
  153. mxs_lcd_init(dev, fb, timings, bpp);
  154. #ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM
  155. /*
  156. * If the LCD runs in system mode, the LCD refresh has to be triggered
  157. * manually by setting the RUN bit in HW_LCDIF_CTRL register. To avoid
  158. * having to set this bit manually after every single change in the
  159. * framebuffer memory, we set up specially crafted circular DMA, which
  160. * sets the RUN bit, then waits until it gets cleared and repeats this
  161. * infinitelly. This way, we get smooth continuous updates of the LCD.
  162. */
  163. struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
  164. memset(&desc, 0, sizeof(struct mxs_dma_desc));
  165. desc.address = (dma_addr_t)&desc;
  166. desc.cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
  167. MXS_DMA_DESC_WAIT4END |
  168. (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
  169. desc.cmd.pio_words[0] = readl(&regs->hw_lcdif_ctrl) | LCDIF_CTRL_RUN;
  170. desc.cmd.next = (uint32_t)&desc.cmd;
  171. /* Execute the DMA chain. */
  172. mxs_dma_circ_start(MXS_DMA_CHANNEL_AHB_APBH_LCDIF, &desc);
  173. #endif
  174. return 0;
  175. }
  176. static int mxs_remove_common(u32 fb)
  177. {
  178. struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
  179. int timeout = 1000000;
  180. if (!fb)
  181. return -EINVAL;
  182. writel(fb, &regs->hw_lcdif_cur_buf_reg);
  183. writel(fb, &regs->hw_lcdif_next_buf_reg);
  184. writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, &regs->hw_lcdif_ctrl1_clr);
  185. while (--timeout) {
  186. if (readl(&regs->hw_lcdif_ctrl1_reg) &
  187. LCDIF_CTRL1_VSYNC_EDGE_IRQ)
  188. break;
  189. udelay(1);
  190. }
  191. mxs_reset_block((struct mxs_register_32 *)&regs->hw_lcdif_ctrl_reg);
  192. return 0;
  193. }
  194. #ifndef CONFIG_DM_VIDEO
  195. static GraphicDevice panel;
  196. void lcdif_power_down(void)
  197. {
  198. mxs_remove_common(panel.frameAdrs);
  199. }
  200. void *video_hw_init(void)
  201. {
  202. int bpp = -1;
  203. int ret = 0;
  204. char *penv;
  205. void *fb = NULL;
  206. struct ctfb_res_modes mode;
  207. struct display_timing timings;
  208. puts("Video: ");
  209. /* Suck display configuration from "videomode" variable */
  210. penv = env_get("videomode");
  211. if (!penv) {
  212. puts("MXSFB: 'videomode' variable not set!\n");
  213. return NULL;
  214. }
  215. bpp = video_get_params(&mode, penv);
  216. /* fill in Graphic device struct */
  217. sprintf(panel.modeIdent, "%dx%dx%d", mode.xres, mode.yres, bpp);
  218. panel.winSizeX = mode.xres;
  219. panel.winSizeY = mode.yres;
  220. panel.plnSizeX = mode.xres;
  221. panel.plnSizeY = mode.yres;
  222. switch (bpp) {
  223. case 24:
  224. case 18:
  225. panel.gdfBytesPP = 4;
  226. panel.gdfIndex = GDF_32BIT_X888RGB;
  227. break;
  228. case 16:
  229. panel.gdfBytesPP = 2;
  230. panel.gdfIndex = GDF_16BIT_565RGB;
  231. break;
  232. case 8:
  233. panel.gdfBytesPP = 1;
  234. panel.gdfIndex = GDF__8BIT_INDEX;
  235. break;
  236. default:
  237. printf("MXSFB: Invalid BPP specified! (bpp = %i)\n", bpp);
  238. return NULL;
  239. }
  240. panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP;
  241. /* Allocate framebuffer */
  242. fb = memalign(ARCH_DMA_MINALIGN,
  243. roundup(panel.memSize, ARCH_DMA_MINALIGN));
  244. if (!fb) {
  245. printf("MXSFB: Error allocating framebuffer!\n");
  246. return NULL;
  247. }
  248. /* Wipe framebuffer */
  249. memset(fb, 0, panel.memSize);
  250. panel.frameAdrs = (u32)fb;
  251. printf("%s\n", panel.modeIdent);
  252. video_ctfb_mode_to_display_timing(&mode, &timings);
  253. ret = mxs_probe_common(NULL, &timings, bpp, (u32)fb);
  254. if (ret)
  255. goto dealloc_fb;
  256. return (void *)&panel;
  257. dealloc_fb:
  258. free(fb);
  259. return NULL;
  260. }
  261. #else /* ifndef CONFIG_DM_VIDEO */
  262. static int mxs_of_get_timings(struct udevice *dev,
  263. struct display_timing *timings,
  264. u32 *bpp)
  265. {
  266. int ret = 0;
  267. u32 display_phandle;
  268. ofnode display_node;
  269. ret = ofnode_read_u32(dev_ofnode(dev), "display", &display_phandle);
  270. if (ret) {
  271. dev_err(dev, "required display property isn't provided\n");
  272. return -EINVAL;
  273. }
  274. display_node = ofnode_get_by_phandle(display_phandle);
  275. if (!ofnode_valid(display_node)) {
  276. dev_err(dev, "failed to find display subnode\n");
  277. return -EINVAL;
  278. }
  279. ret = ofnode_read_u32(display_node, "bits-per-pixel", bpp);
  280. if (ret) {
  281. dev_err(dev,
  282. "required bits-per-pixel property isn't provided\n");
  283. return -EINVAL;
  284. }
  285. ret = ofnode_decode_display_timing(display_node, 0, timings);
  286. if (ret) {
  287. dev_err(dev, "failed to get any display timings\n");
  288. return -EINVAL;
  289. }
  290. return ret;
  291. }
  292. static int mxs_video_probe(struct udevice *dev)
  293. {
  294. struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
  295. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  296. struct display_timing timings;
  297. u32 bpp = 0;
  298. u32 fb_start, fb_end;
  299. int ret;
  300. debug("%s() plat: base 0x%lx, size 0x%x\n",
  301. __func__, plat->base, plat->size);
  302. ret = mxs_of_get_timings(dev, &timings, &bpp);
  303. if (ret)
  304. return ret;
  305. ret = mxs_probe_common(dev, &timings, bpp, plat->base);
  306. if (ret)
  307. return ret;
  308. switch (bpp) {
  309. case 32:
  310. case 24:
  311. case 18:
  312. uc_priv->bpix = VIDEO_BPP32;
  313. break;
  314. case 16:
  315. uc_priv->bpix = VIDEO_BPP16;
  316. break;
  317. case 8:
  318. uc_priv->bpix = VIDEO_BPP8;
  319. break;
  320. default:
  321. dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp);
  322. return -EINVAL;
  323. }
  324. uc_priv->xsize = timings.hactive.typ;
  325. uc_priv->ysize = timings.vactive.typ;
  326. /* Enable dcache for the frame buffer */
  327. fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
  328. fb_end = plat->base + plat->size;
  329. fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
  330. mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
  331. DCACHE_WRITEBACK);
  332. video_set_flush_dcache(dev, true);
  333. gd->fb_base = plat->base;
  334. return ret;
  335. }
  336. static int mxs_video_bind(struct udevice *dev)
  337. {
  338. struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
  339. struct display_timing timings;
  340. u32 bpp = 0;
  341. u32 bytes_pp = 0;
  342. int ret;
  343. ret = mxs_of_get_timings(dev, &timings, &bpp);
  344. if (ret)
  345. return ret;
  346. switch (bpp) {
  347. case 32:
  348. case 24:
  349. case 18:
  350. bytes_pp = 4;
  351. break;
  352. case 16:
  353. bytes_pp = 2;
  354. break;
  355. case 8:
  356. bytes_pp = 1;
  357. break;
  358. default:
  359. dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp);
  360. return -EINVAL;
  361. }
  362. plat->size = timings.hactive.typ * timings.vactive.typ * bytes_pp;
  363. return 0;
  364. }
  365. static int mxs_video_remove(struct udevice *dev)
  366. {
  367. struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
  368. mxs_remove_common(plat->base);
  369. return 0;
  370. }
  371. static const struct udevice_id mxs_video_ids[] = {
  372. { .compatible = "fsl,imx23-lcdif" },
  373. { .compatible = "fsl,imx28-lcdif" },
  374. { .compatible = "fsl,imx7ulp-lcdif" },
  375. { .compatible = "fsl,imxrt-lcdif" },
  376. { /* sentinel */ }
  377. };
  378. U_BOOT_DRIVER(mxs_video) = {
  379. .name = "mxs_video",
  380. .id = UCLASS_VIDEO,
  381. .of_match = mxs_video_ids,
  382. .bind = mxs_video_bind,
  383. .probe = mxs_video_probe,
  384. .remove = mxs_video_remove,
  385. .flags = DM_FLAG_PRE_RELOC | DM_FLAG_OS_PREPARE,
  386. };
  387. #endif /* ifndef CONFIG_DM_VIDEO */