mx3fb.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2009
  4. * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
  5. * Copyright (C) 2011
  6. * HALE electronic GmbH, <helmut.raiger@hale.at>
  7. */
  8. #include <common.h>
  9. #include <env.h>
  10. #include <malloc.h>
  11. #include <video_fb.h>
  12. #include <asm/arch/imx-regs.h>
  13. #include <asm/arch/clock.h>
  14. #include <linux/errno.h>
  15. #include <asm/io.h>
  16. #include "videomodes.h"
  17. /* this might need panel specific set-up as-well */
  18. #define IF_CONF 0
  19. /* -------------- controller specific stuff -------------- */
  20. /* IPU DMA Controller channel definitions. */
  21. enum ipu_channel {
  22. IDMAC_IC_0 = 0, /* IC (encoding task) to memory */
  23. IDMAC_IC_1 = 1, /* IC (viewfinder task) to memory */
  24. IDMAC_ADC_0 = 1,
  25. IDMAC_IC_2 = 2,
  26. IDMAC_ADC_1 = 2,
  27. IDMAC_IC_3 = 3,
  28. IDMAC_IC_4 = 4,
  29. IDMAC_IC_5 = 5,
  30. IDMAC_IC_6 = 6,
  31. IDMAC_IC_7 = 7, /* IC (sensor data) to memory */
  32. IDMAC_IC_8 = 8,
  33. IDMAC_IC_9 = 9,
  34. IDMAC_IC_10 = 10,
  35. IDMAC_IC_11 = 11,
  36. IDMAC_IC_12 = 12,
  37. IDMAC_IC_13 = 13,
  38. IDMAC_SDC_0 = 14, /* Background synchronous display data */
  39. IDMAC_SDC_1 = 15, /* Foreground data (overlay) */
  40. IDMAC_SDC_2 = 16,
  41. IDMAC_SDC_3 = 17,
  42. IDMAC_ADC_2 = 18,
  43. IDMAC_ADC_3 = 19,
  44. IDMAC_ADC_4 = 20,
  45. IDMAC_ADC_5 = 21,
  46. IDMAC_ADC_6 = 22,
  47. IDMAC_ADC_7 = 23,
  48. IDMAC_PF_0 = 24,
  49. IDMAC_PF_1 = 25,
  50. IDMAC_PF_2 = 26,
  51. IDMAC_PF_3 = 27,
  52. IDMAC_PF_4 = 28,
  53. IDMAC_PF_5 = 29,
  54. IDMAC_PF_6 = 30,
  55. IDMAC_PF_7 = 31,
  56. };
  57. /* More formats can be copied from the Linux driver if needed */
  58. enum pixel_fmt {
  59. /* 2 bytes */
  60. IPU_PIX_FMT_RGB565,
  61. IPU_PIX_FMT_RGB666,
  62. IPU_PIX_FMT_BGR666,
  63. /* 3 bytes */
  64. IPU_PIX_FMT_RGB24,
  65. };
  66. struct pixel_fmt_cfg {
  67. u32 b0;
  68. u32 b1;
  69. u32 b2;
  70. u32 acc;
  71. };
  72. static struct pixel_fmt_cfg fmt_cfg[] = {
  73. [IPU_PIX_FMT_RGB24] = {
  74. 0x1600AAAA, 0x00E05555, 0x00070000, 3,
  75. },
  76. [IPU_PIX_FMT_RGB666] = {
  77. 0x0005000F, 0x000B000F, 0x0011000F, 1,
  78. },
  79. [IPU_PIX_FMT_BGR666] = {
  80. 0x0011000F, 0x000B000F, 0x0005000F, 1,
  81. },
  82. [IPU_PIX_FMT_RGB565] = {
  83. 0x0004003F, 0x000A000F, 0x000F003F, 1,
  84. }
  85. };
  86. enum ipu_panel {
  87. IPU_PANEL_SHARP_TFT,
  88. IPU_PANEL_TFT,
  89. };
  90. /* IPU Common registers */
  91. /* IPU_CONF and its bits already defined in imx-regs.h */
  92. #define IPU_CHA_BUF0_RDY (0x04 + IPU_BASE)
  93. #define IPU_CHA_BUF1_RDY (0x08 + IPU_BASE)
  94. #define IPU_CHA_DB_MODE_SEL (0x0C + IPU_BASE)
  95. #define IPU_CHA_CUR_BUF (0x10 + IPU_BASE)
  96. #define IPU_FS_PROC_FLOW (0x14 + IPU_BASE)
  97. #define IPU_FS_DISP_FLOW (0x18 + IPU_BASE)
  98. #define IPU_TASKS_STAT (0x1C + IPU_BASE)
  99. #define IPU_IMA_ADDR (0x20 + IPU_BASE)
  100. #define IPU_IMA_DATA (0x24 + IPU_BASE)
  101. #define IPU_INT_CTRL_1 (0x28 + IPU_BASE)
  102. #define IPU_INT_CTRL_2 (0x2C + IPU_BASE)
  103. #define IPU_INT_CTRL_3 (0x30 + IPU_BASE)
  104. #define IPU_INT_CTRL_4 (0x34 + IPU_BASE)
  105. #define IPU_INT_CTRL_5 (0x38 + IPU_BASE)
  106. #define IPU_INT_STAT_1 (0x3C + IPU_BASE)
  107. #define IPU_INT_STAT_2 (0x40 + IPU_BASE)
  108. #define IPU_INT_STAT_3 (0x44 + IPU_BASE)
  109. #define IPU_INT_STAT_4 (0x48 + IPU_BASE)
  110. #define IPU_INT_STAT_5 (0x4C + IPU_BASE)
  111. #define IPU_BRK_CTRL_1 (0x50 + IPU_BASE)
  112. #define IPU_BRK_CTRL_2 (0x54 + IPU_BASE)
  113. #define IPU_BRK_STAT (0x58 + IPU_BASE)
  114. #define IPU_DIAGB_CTRL (0x5C + IPU_BASE)
  115. /* Image Converter Registers */
  116. #define IC_CONF (0x88 + IPU_BASE)
  117. #define IC_PRP_ENC_RSC (0x8C + IPU_BASE)
  118. #define IC_PRP_VF_RSC (0x90 + IPU_BASE)
  119. #define IC_PP_RSC (0x94 + IPU_BASE)
  120. #define IC_CMBP_1 (0x98 + IPU_BASE)
  121. #define IC_CMBP_2 (0x9C + IPU_BASE)
  122. #define PF_CONF (0xA0 + IPU_BASE)
  123. #define IDMAC_CONF (0xA4 + IPU_BASE)
  124. #define IDMAC_CHA_EN (0xA8 + IPU_BASE)
  125. #define IDMAC_CHA_PRI (0xAC + IPU_BASE)
  126. #define IDMAC_CHA_BUSY (0xB0 + IPU_BASE)
  127. /* Image Converter Register bits */
  128. #define IC_CONF_PRPENC_EN 0x00000001
  129. #define IC_CONF_PRPENC_CSC1 0x00000002
  130. #define IC_CONF_PRPENC_ROT_EN 0x00000004
  131. #define IC_CONF_PRPVF_EN 0x00000100
  132. #define IC_CONF_PRPVF_CSC1 0x00000200
  133. #define IC_CONF_PRPVF_CSC2 0x00000400
  134. #define IC_CONF_PRPVF_CMB 0x00000800
  135. #define IC_CONF_PRPVF_ROT_EN 0x00001000
  136. #define IC_CONF_PP_EN 0x00010000
  137. #define IC_CONF_PP_CSC1 0x00020000
  138. #define IC_CONF_PP_CSC2 0x00040000
  139. #define IC_CONF_PP_CMB 0x00080000
  140. #define IC_CONF_PP_ROT_EN 0x00100000
  141. #define IC_CONF_IC_GLB_LOC_A 0x10000000
  142. #define IC_CONF_KEY_COLOR_EN 0x20000000
  143. #define IC_CONF_RWS_EN 0x40000000
  144. #define IC_CONF_CSI_MEM_WR_EN 0x80000000
  145. /* SDC Registers */
  146. #define SDC_COM_CONF (0xB4 + IPU_BASE)
  147. #define SDC_GW_CTRL (0xB8 + IPU_BASE)
  148. #define SDC_FG_POS (0xBC + IPU_BASE)
  149. #define SDC_BG_POS (0xC0 + IPU_BASE)
  150. #define SDC_CUR_POS (0xC4 + IPU_BASE)
  151. #define SDC_PWM_CTRL (0xC8 + IPU_BASE)
  152. #define SDC_CUR_MAP (0xCC + IPU_BASE)
  153. #define SDC_HOR_CONF (0xD0 + IPU_BASE)
  154. #define SDC_VER_CONF (0xD4 + IPU_BASE)
  155. #define SDC_SHARP_CONF_1 (0xD8 + IPU_BASE)
  156. #define SDC_SHARP_CONF_2 (0xDC + IPU_BASE)
  157. /* Register bits */
  158. #define SDC_COM_TFT_COLOR 0x00000001UL
  159. #define SDC_COM_FG_EN 0x00000010UL
  160. #define SDC_COM_GWSEL 0x00000020UL
  161. #define SDC_COM_GLB_A 0x00000040UL
  162. #define SDC_COM_KEY_COLOR_G 0x00000080UL
  163. #define SDC_COM_BG_EN 0x00000200UL
  164. #define SDC_COM_SHARP 0x00001000UL
  165. #define SDC_V_SYNC_WIDTH_L 0x00000001UL
  166. /* Display Interface registers */
  167. #define DI_DISP_IF_CONF (0x0124 + IPU_BASE)
  168. #define DI_DISP_SIG_POL (0x0128 + IPU_BASE)
  169. #define DI_SER_DISP1_CONF (0x012C + IPU_BASE)
  170. #define DI_SER_DISP2_CONF (0x0130 + IPU_BASE)
  171. #define DI_HSP_CLK_PER (0x0134 + IPU_BASE)
  172. #define DI_DISP0_TIME_CONF_1 (0x0138 + IPU_BASE)
  173. #define DI_DISP0_TIME_CONF_2 (0x013C + IPU_BASE)
  174. #define DI_DISP0_TIME_CONF_3 (0x0140 + IPU_BASE)
  175. #define DI_DISP1_TIME_CONF_1 (0x0144 + IPU_BASE)
  176. #define DI_DISP1_TIME_CONF_2 (0x0148 + IPU_BASE)
  177. #define DI_DISP1_TIME_CONF_3 (0x014C + IPU_BASE)
  178. #define DI_DISP2_TIME_CONF_1 (0x0150 + IPU_BASE)
  179. #define DI_DISP2_TIME_CONF_2 (0x0154 + IPU_BASE)
  180. #define DI_DISP2_TIME_CONF_3 (0x0158 + IPU_BASE)
  181. #define DI_DISP3_TIME_CONF (0x015C + IPU_BASE)
  182. #define DI_DISP0_DB0_MAP (0x0160 + IPU_BASE)
  183. #define DI_DISP0_DB1_MAP (0x0164 + IPU_BASE)
  184. #define DI_DISP0_DB2_MAP (0x0168 + IPU_BASE)
  185. #define DI_DISP0_CB0_MAP (0x016C + IPU_BASE)
  186. #define DI_DISP0_CB1_MAP (0x0170 + IPU_BASE)
  187. #define DI_DISP0_CB2_MAP (0x0174 + IPU_BASE)
  188. #define DI_DISP1_DB0_MAP (0x0178 + IPU_BASE)
  189. #define DI_DISP1_DB1_MAP (0x017C + IPU_BASE)
  190. #define DI_DISP1_DB2_MAP (0x0180 + IPU_BASE)
  191. #define DI_DISP1_CB0_MAP (0x0184 + IPU_BASE)
  192. #define DI_DISP1_CB1_MAP (0x0188 + IPU_BASE)
  193. #define DI_DISP1_CB2_MAP (0x018C + IPU_BASE)
  194. #define DI_DISP2_DB0_MAP (0x0190 + IPU_BASE)
  195. #define DI_DISP2_DB1_MAP (0x0194 + IPU_BASE)
  196. #define DI_DISP2_DB2_MAP (0x0198 + IPU_BASE)
  197. #define DI_DISP2_CB0_MAP (0x019C + IPU_BASE)
  198. #define DI_DISP2_CB1_MAP (0x01A0 + IPU_BASE)
  199. #define DI_DISP2_CB2_MAP (0x01A4 + IPU_BASE)
  200. #define DI_DISP3_B0_MAP (0x01A8 + IPU_BASE)
  201. #define DI_DISP3_B1_MAP (0x01AC + IPU_BASE)
  202. #define DI_DISP3_B2_MAP (0x01B0 + IPU_BASE)
  203. #define DI_DISP_ACC_CC (0x01B4 + IPU_BASE)
  204. #define DI_DISP_LLA_CONF (0x01B8 + IPU_BASE)
  205. #define DI_DISP_LLA_DATA (0x01BC + IPU_BASE)
  206. /* DI_DISP_SIG_POL bits */
  207. #define DI_D3_VSYNC_POL (1 << 28)
  208. #define DI_D3_HSYNC_POL (1 << 27)
  209. #define DI_D3_DRDY_SHARP_POL (1 << 26)
  210. #define DI_D3_CLK_POL (1 << 25)
  211. #define DI_D3_DATA_POL (1 << 24)
  212. /* DI_DISP_IF_CONF bits */
  213. #define DI_D3_CLK_IDLE (1 << 26)
  214. #define DI_D3_CLK_SEL (1 << 25)
  215. #define DI_D3_DATAMSK (1 << 24)
  216. #define IOMUX_PADNUM_MASK 0x1ff
  217. #define IOMUX_GPIONUM_SHIFT 9
  218. #define IOMUX_GPIONUM_MASK (0xff << IOMUX_GPIONUM_SHIFT)
  219. #define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK)
  220. #define IOMUX_MODE_L(pin, mode) IOMUX_MODE(((pin) + 0xc) ^ 3, mode)
  221. struct chan_param_mem_planar {
  222. /* Word 0 */
  223. u32 xv:10;
  224. u32 yv:10;
  225. u32 xb:12;
  226. u32 yb:12;
  227. u32 res1:2;
  228. u32 nsb:1;
  229. u32 lnpb:6;
  230. u32 ubo_l:11;
  231. u32 ubo_h:15;
  232. u32 vbo_l:17;
  233. u32 vbo_h:9;
  234. u32 res2:3;
  235. u32 fw:12;
  236. u32 fh_l:8;
  237. u32 fh_h:4;
  238. u32 res3:28;
  239. /* Word 1 */
  240. u32 eba0;
  241. u32 eba1;
  242. u32 bpp:3;
  243. u32 sl:14;
  244. u32 pfs:3;
  245. u32 bam:3;
  246. u32 res4:2;
  247. u32 npb:6;
  248. u32 res5:1;
  249. u32 sat:2;
  250. u32 res6:30;
  251. } __attribute__ ((packed));
  252. struct chan_param_mem_interleaved {
  253. /* Word 0 */
  254. u32 xv:10;
  255. u32 yv:10;
  256. u32 xb:12;
  257. u32 yb:12;
  258. u32 sce:1;
  259. u32 res1:1;
  260. u32 nsb:1;
  261. u32 lnpb:6;
  262. u32 sx:10;
  263. u32 sy_l:1;
  264. u32 sy_h:9;
  265. u32 ns:10;
  266. u32 sm:10;
  267. u32 sdx_l:3;
  268. u32 sdx_h:2;
  269. u32 sdy:5;
  270. u32 sdrx:1;
  271. u32 sdry:1;
  272. u32 sdr1:1;
  273. u32 res2:2;
  274. u32 fw:12;
  275. u32 fh_l:8;
  276. u32 fh_h:4;
  277. u32 res3:28;
  278. /* Word 1 */
  279. u32 eba0;
  280. u32 eba1;
  281. u32 bpp:3;
  282. u32 sl:14;
  283. u32 pfs:3;
  284. u32 bam:3;
  285. u32 res4:2;
  286. u32 npb:6;
  287. u32 res5:1;
  288. u32 sat:2;
  289. u32 scc:1;
  290. u32 ofs0:5;
  291. u32 ofs1:5;
  292. u32 ofs2:5;
  293. u32 ofs3:5;
  294. u32 wid0:3;
  295. u32 wid1:3;
  296. u32 wid2:3;
  297. u32 wid3:3;
  298. u32 dec_sel:1;
  299. u32 res6:28;
  300. } __attribute__ ((packed));
  301. union chan_param_mem {
  302. struct chan_param_mem_planar pp;
  303. struct chan_param_mem_interleaved ip;
  304. };
  305. /* graphics setup */
  306. static GraphicDevice panel;
  307. static struct ctfb_res_modes *mode;
  308. static struct ctfb_res_modes var_mode;
  309. /*
  310. * sdc_init_panel() - initialize a synchronous LCD panel.
  311. * @width: width of panel in pixels.
  312. * @height: height of panel in pixels.
  313. * @di_setup: pixel format of the frame buffer
  314. * @di_panel: either SHARP or normal TFT
  315. * @return: 0 on success or negative error code on failure.
  316. */
  317. static int sdc_init_panel(u16 width, u16 height,
  318. enum pixel_fmt di_setup, enum ipu_panel di_panel)
  319. {
  320. u32 reg, div;
  321. uint32_t old_conf;
  322. int clock;
  323. debug("%s(width=%d, height=%d)\n", __func__, width, height);
  324. /* Init clocking, the IPU receives its clock from the hsp divder */
  325. clock = mxc_get_clock(MXC_IPU_CLK);
  326. if (clock < 0)
  327. return -EACCES;
  328. /* Init panel size and blanking periods */
  329. reg = width + mode->left_margin + mode->right_margin - 1;
  330. if (reg > 1023) {
  331. printf("mx3fb: Display width too large, coerced to 1023!");
  332. reg = 1023;
  333. }
  334. reg = ((mode->hsync_len - 1) << 26) | (reg << 16);
  335. writel(reg, SDC_HOR_CONF);
  336. reg = height + mode->upper_margin + mode->lower_margin - 1;
  337. if (reg > 1023) {
  338. printf("mx3fb: Display height too large, coerced to 1023!");
  339. reg = 1023;
  340. }
  341. reg = ((mode->vsync_len - 1) << 26) | SDC_V_SYNC_WIDTH_L | (reg << 16);
  342. writel(reg, SDC_VER_CONF);
  343. switch (di_panel) {
  344. case IPU_PANEL_SHARP_TFT:
  345. writel(0x00FD0102L, SDC_SHARP_CONF_1);
  346. writel(0x00F500F4L, SDC_SHARP_CONF_2);
  347. writel(SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF);
  348. /* TODO: probably IF_CONF must be adapted (see below)! */
  349. break;
  350. case IPU_PANEL_TFT:
  351. writel(SDC_COM_TFT_COLOR, SDC_COM_CONF);
  352. break;
  353. default:
  354. return -EINVAL;
  355. }
  356. /*
  357. * Calculate divider: The fractional part is 4 bits so simply
  358. * multiple by 2^4 to get it.
  359. *
  360. * Opposed to the kernel driver mode->pixclock is the time of one
  361. * pixel in pico seconds, so:
  362. * pixel_clk = 1e12 / mode->pixclock
  363. * div = ipu_clk * 16 / pixel_clk
  364. * leads to:
  365. * div = ipu_clk * 16 / (1e12 / mode->pixclock)
  366. * or:
  367. * div = ipu_clk * 16 * mode->pixclock / 1e12
  368. *
  369. * To avoid integer overflows this is split into 2 shifts and
  370. * one divide with sufficient accuracy:
  371. * 16*1024*128*476837 = 0.9999996682e12
  372. */
  373. div = ((clock/1024) * (mode->pixclock/128)) / 476837;
  374. debug("hsp_clk is %d, div=%d\n", clock, div);
  375. /* coerce to not less than 4.0, not more than 255.9375 */
  376. if (div < 0x40)
  377. div = 0x40;
  378. else if (div > 0xFFF)
  379. div = 0xFFF;
  380. /* DISP3_IF_CLK_DOWN_WR is half the divider value and 2 less
  381. * fraction bits. Subtract 1 extra from DISP3_IF_CLK_DOWN_WR
  382. * based on timing debug DISP3_IF_CLK_UP_WR is 0
  383. */
  384. writel((((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF);
  385. /* DI settings for display 3: clock idle (bit 26) during vsync */
  386. old_conf = readl(DI_DISP_IF_CONF) & 0x78FFFFFF;
  387. writel(old_conf | IF_CONF, DI_DISP_IF_CONF);
  388. /* only set display 3 polarity bits */
  389. old_conf = readl(DI_DISP_SIG_POL) & 0xE0FFFFFF;
  390. writel(old_conf | mode->sync, DI_DISP_SIG_POL);
  391. writel(fmt_cfg[di_setup].b0, DI_DISP3_B0_MAP);
  392. writel(fmt_cfg[di_setup].b1, DI_DISP3_B1_MAP);
  393. writel(fmt_cfg[di_setup].b2, DI_DISP3_B2_MAP);
  394. writel(readl(DI_DISP_ACC_CC) |
  395. ((fmt_cfg[di_setup].acc - 1) << 12), DI_DISP_ACC_CC);
  396. debug("DI_DISP_IF_CONF = 0x%08X\n", readl(DI_DISP_IF_CONF));
  397. debug("DI_DISP_SIG_POL = 0x%08X\n", readl(DI_DISP_SIG_POL));
  398. debug("DI_DISP3_TIME_CONF = 0x%08X\n", readl(DI_DISP3_TIME_CONF));
  399. debug("SDC_HOR_CONF = 0x%08X\n", readl(SDC_HOR_CONF));
  400. debug("SDC_VER_CONF = 0x%08X\n", readl(SDC_VER_CONF));
  401. return 0;
  402. }
  403. static void ipu_ch_param_set_size(union chan_param_mem *params,
  404. uint pixelfmt, uint16_t width,
  405. uint16_t height, uint16_t stride)
  406. {
  407. debug("%s(pixelfmt=%d, width=%d, height=%d, stride=%d)\n",
  408. __func__, pixelfmt, width, height, stride);
  409. params->pp.fw = width - 1;
  410. params->pp.fh_l = height - 1;
  411. params->pp.fh_h = (height - 1) >> 8;
  412. params->pp.sl = stride - 1;
  413. /* See above, for further formats see the Linux driver */
  414. switch (pixelfmt) {
  415. case GDF_16BIT_565RGB:
  416. params->ip.bpp = 2;
  417. params->ip.pfs = 4;
  418. params->ip.npb = 7;
  419. params->ip.sat = 2; /* SAT = 32-bit access */
  420. params->ip.ofs0 = 0; /* Red bit offset */
  421. params->ip.ofs1 = 5; /* Green bit offset */
  422. params->ip.ofs2 = 11; /* Blue bit offset */
  423. params->ip.ofs3 = 16; /* Alpha bit offset */
  424. params->ip.wid0 = 4; /* Red bit width - 1 */
  425. params->ip.wid1 = 5; /* Green bit width - 1 */
  426. params->ip.wid2 = 4; /* Blue bit width - 1 */
  427. break;
  428. case GDF_32BIT_X888RGB:
  429. params->ip.bpp = 1; /* 24 BPP & RGB PFS */
  430. params->ip.pfs = 4;
  431. params->ip.npb = 7;
  432. params->ip.sat = 2; /* SAT = 32-bit access */
  433. params->ip.ofs0 = 16; /* Red bit offset */
  434. params->ip.ofs1 = 8; /* Green bit offset */
  435. params->ip.ofs2 = 0; /* Blue bit offset */
  436. params->ip.ofs3 = 24; /* Alpha bit offset */
  437. params->ip.wid0 = 7; /* Red bit width - 1 */
  438. params->ip.wid1 = 7; /* Green bit width - 1 */
  439. params->ip.wid2 = 7; /* Blue bit width - 1 */
  440. break;
  441. default:
  442. printf("mx3fb: Pixel format not supported!\n");
  443. break;
  444. }
  445. params->pp.nsb = 1;
  446. }
  447. static void ipu_ch_param_set_buffer(union chan_param_mem *params,
  448. void *buf0, void *buf1)
  449. {
  450. params->pp.eba0 = (u32)buf0;
  451. params->pp.eba1 = (u32)buf1;
  452. }
  453. static void ipu_write_param_mem(uint32_t addr, uint32_t *data,
  454. uint32_t num_words)
  455. {
  456. for (; num_words > 0; num_words--) {
  457. writel(addr, IPU_IMA_ADDR);
  458. writel(*data++, IPU_IMA_DATA);
  459. addr++;
  460. if ((addr & 0x7) == 5) {
  461. addr &= ~0x7; /* set to word 0 */
  462. addr += 8; /* increment to next row */
  463. }
  464. }
  465. }
  466. static uint32_t dma_param_addr(enum ipu_channel channel)
  467. {
  468. /* Channel Parameter Memory */
  469. return 0x10000 | (channel << 4);
  470. }
  471. static void ipu_init_channel_buffer(enum ipu_channel channel, void *fbmem)
  472. {
  473. union chan_param_mem params = {};
  474. uint32_t reg;
  475. uint32_t stride_bytes;
  476. stride_bytes = (panel.plnSizeX * panel.gdfBytesPP + 3) & ~3;
  477. debug("%s(channel=%d, fbmem=%p)\n", __func__, channel, fbmem);
  478. /* Build parameter memory data for DMA channel */
  479. ipu_ch_param_set_size(&params, panel.gdfIndex,
  480. panel.plnSizeX, panel.plnSizeY, stride_bytes);
  481. ipu_ch_param_set_buffer(&params, fbmem, NULL);
  482. params.pp.bam = 0;
  483. /* Some channels (rotation) have restriction on burst length */
  484. switch (channel) {
  485. case IDMAC_SDC_0:
  486. /* In original code only IPU_PIX_FMT_RGB565 was setting burst */
  487. params.pp.npb = 16 - 1;
  488. break;
  489. default:
  490. break;
  491. }
  492. ipu_write_param_mem(dma_param_addr(channel), (uint32_t *)&params, 10);
  493. /* Disable double-buffering */
  494. reg = readl(IPU_CHA_DB_MODE_SEL);
  495. reg &= ~(1UL << channel);
  496. writel(reg, IPU_CHA_DB_MODE_SEL);
  497. }
  498. static void ipu_channel_set_priority(enum ipu_channel channel,
  499. int prio)
  500. {
  501. u32 reg = readl(IDMAC_CHA_PRI);
  502. if (prio)
  503. reg |= 1UL << channel;
  504. else
  505. reg &= ~(1UL << channel);
  506. writel(reg, IDMAC_CHA_PRI);
  507. }
  508. /*
  509. * ipu_enable_channel() - enable an IPU channel.
  510. * @channel: channel ID.
  511. * @return: 0 on success or negative error code on failure.
  512. */
  513. static int ipu_enable_channel(enum ipu_channel channel)
  514. {
  515. uint32_t reg;
  516. /* Reset to buffer 0 */
  517. writel(1UL << channel, IPU_CHA_CUR_BUF);
  518. switch (channel) {
  519. case IDMAC_SDC_0:
  520. ipu_channel_set_priority(channel, 1);
  521. break;
  522. default:
  523. break;
  524. }
  525. reg = readl(IDMAC_CHA_EN);
  526. writel(reg | (1UL << channel), IDMAC_CHA_EN);
  527. return 0;
  528. }
  529. static int ipu_update_channel_buffer(enum ipu_channel channel, void *buf)
  530. {
  531. uint32_t reg;
  532. reg = readl(IPU_CHA_BUF0_RDY);
  533. if (reg & (1UL << channel))
  534. return -EACCES;
  535. /* 44.3.3.1.9 - Row Number 1 (WORD1, offset 0) */
  536. writel(dma_param_addr(channel) + 0x0008UL, IPU_IMA_ADDR);
  537. writel((u32)buf, IPU_IMA_DATA);
  538. return 0;
  539. }
  540. static int idmac_tx_submit(enum ipu_channel channel, void *buf)
  541. {
  542. int ret;
  543. ipu_init_channel_buffer(channel, buf);
  544. /* ipu_idmac.c::ipu_submit_channel_buffers() */
  545. ret = ipu_update_channel_buffer(channel, buf);
  546. if (ret < 0)
  547. return ret;
  548. /* ipu_idmac.c::ipu_select_buffer() */
  549. /* Mark buffer 0 as ready. */
  550. writel(1UL << channel, IPU_CHA_BUF0_RDY);
  551. ret = ipu_enable_channel(channel);
  552. return ret;
  553. }
  554. static void sdc_enable_channel(void *fbmem)
  555. {
  556. int ret;
  557. u32 reg;
  558. ret = idmac_tx_submit(IDMAC_SDC_0, fbmem);
  559. /* mx3fb.c::sdc_fb_init() */
  560. if (ret >= 0) {
  561. reg = readl(SDC_COM_CONF);
  562. writel(reg | SDC_COM_BG_EN, SDC_COM_CONF);
  563. }
  564. /*
  565. * Attention! Without this msleep the channel keeps generating
  566. * interrupts. Next sdc_set_brightness() is going to be called
  567. * from mx3fb_blank().
  568. */
  569. udelay(2000);
  570. }
  571. /*
  572. * mx3fb_set_par() - set framebuffer parameters and change the operating mode.
  573. * @return: 0 on success or negative error code on failure.
  574. * TODO: currently only 666 and TFT as DI setup supported
  575. */
  576. static int mx3fb_set_par(void)
  577. {
  578. int ret;
  579. ret = sdc_init_panel(panel.plnSizeX, panel.plnSizeY,
  580. IPU_PIX_FMT_RGB666, IPU_PANEL_TFT);
  581. if (ret < 0)
  582. return ret;
  583. writel((mode->left_margin << 16) | mode->upper_margin, SDC_BG_POS);
  584. return 0;
  585. }
  586. static void ll_disp3_enable(void *base)
  587. {
  588. u32 reg;
  589. debug("%s(base=0x%x)\n", __func__, (u32) base);
  590. /* pcm037.c::mxc_board_init() */
  591. /* Display Interface #3 */
  592. mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD0, MUX_CTL_FUNC));
  593. mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD1, MUX_CTL_FUNC));
  594. mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD2, MUX_CTL_FUNC));
  595. mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD3, MUX_CTL_FUNC));
  596. mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD4, MUX_CTL_FUNC));
  597. mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD5, MUX_CTL_FUNC));
  598. mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD6, MUX_CTL_FUNC));
  599. mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD7, MUX_CTL_FUNC));
  600. mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD8, MUX_CTL_FUNC));
  601. mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD9, MUX_CTL_FUNC));
  602. mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD10, MUX_CTL_FUNC));
  603. mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD11, MUX_CTL_FUNC));
  604. mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD12, MUX_CTL_FUNC));
  605. mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD13, MUX_CTL_FUNC));
  606. mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD14, MUX_CTL_FUNC));
  607. mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD15, MUX_CTL_FUNC));
  608. mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD16, MUX_CTL_FUNC));
  609. mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD17, MUX_CTL_FUNC));
  610. mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_VSYNC3, MUX_CTL_FUNC));
  611. mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_HSYNC, MUX_CTL_FUNC));
  612. mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_FPSHIFT, MUX_CTL_FUNC));
  613. mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_DRDY0, MUX_CTL_FUNC));
  614. mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_REV, MUX_CTL_FUNC));
  615. mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_CONTRAST, MUX_CTL_FUNC));
  616. mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_SPL, MUX_CTL_FUNC));
  617. mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_CLS, MUX_CTL_FUNC));
  618. /* ipu_idmac.c::ipu_probe() */
  619. /* Start the clock */
  620. __REG(CCM_CGR1) = __REG(CCM_CGR1) | (3 << 22);
  621. /* ipu_idmac.c::ipu_idmac_init() */
  622. /* Service request counter to maximum - shouldn't be needed */
  623. writel(0x00000070, IDMAC_CONF);
  624. /* ipu_idmac.c::ipu_init_channel() */
  625. /* Enable IPU sub modules */
  626. reg = readl(IPU_CONF) | IPU_CONF_SDC_EN | IPU_CONF_DI_EN;
  627. writel(reg, IPU_CONF);
  628. /* mx3fb.c::init_fb_chan() */
  629. /* set Display Interface clock period */
  630. writel(0x00100010L, DI_HSP_CLK_PER);
  631. /* Might need to trigger HSP clock change - see 44.3.3.8.5 */
  632. /* mx3fb.c::sdc_set_brightness() */
  633. /* This might be board-specific */
  634. writel(0x03000000UL | 255 << 16, SDC_PWM_CTRL);
  635. /* mx3fb.c::sdc_set_global_alpha() */
  636. /* Use global - not per-pixel - Alpha-blending */
  637. reg = readl(SDC_GW_CTRL) & 0x00FFFFFFL;
  638. writel(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL);
  639. reg = readl(SDC_COM_CONF);
  640. writel(reg | SDC_COM_GLB_A, SDC_COM_CONF);
  641. /* mx3fb.c::sdc_set_color_key() */
  642. /* Disable colour-keying for background */
  643. reg = readl(SDC_COM_CONF) &
  644. ~(SDC_COM_GWSEL | SDC_COM_KEY_COLOR_G);
  645. writel(reg, SDC_COM_CONF);
  646. mx3fb_set_par();
  647. sdc_enable_channel(base);
  648. /*
  649. * Linux driver calls sdc_set_brightness() here again,
  650. * once is enough for us
  651. */
  652. debug("%s() done\n", __func__);
  653. }
  654. /* ------------------------ public part ------------------- */
  655. ulong calc_fbsize(void)
  656. {
  657. return panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP;
  658. }
  659. /*
  660. * The current implementation is only tested for GDF_16BIT_565RGB!
  661. * It was switched from the original CONFIG_LCD setup to CONFIG_VIDEO,
  662. * because the lcd code seemed loaded with color table stuff, that
  663. * does not relate to most modern TFTs. cfb_console.c looks more
  664. * straight forward.
  665. * This is the environment setting for the original setup
  666. * "unknown=video=ctfb:x:240,y:320,depth:16,mode:0,pclk:185925,le:9,ri:17,
  667. * up:7,lo:10,hs:1,vs:1,sync:100663296,vmode:0"
  668. * "videomode=unknown"
  669. *
  670. * Settings for VBEST VGG322403 display:
  671. * "videomode=video=ctfb:x:320,y:240,depth:16,mode:0,pclk:156000,
  672. * "le:20,ri:68,up:7,lo:29,hs:30,vs:3,sync:100663296,vmode:0"
  673. *
  674. * Settings for COM57H5M10XRC display:
  675. * "videomode=video=ctfb:x:640,y:480,depth:16,mode:0,pclk:40000,
  676. * "le:120,ri:40,up:35,lo:10,hs:30,vs:3,sync:100663296,vmode:0"
  677. */
  678. void *video_hw_init(void)
  679. {
  680. char *penv;
  681. u32 memsize;
  682. unsigned long t1, hsynch, vsynch;
  683. int bits_per_pixel, i, tmp, videomode;
  684. tmp = 0;
  685. puts("Video: ");
  686. videomode = CONFIG_SYS_DEFAULT_VIDEO_MODE;
  687. /* get video mode via environment */
  688. penv = env_get("videomode");
  689. if (penv) {
  690. /* decide if it is a string */
  691. if (penv[0] <= '9') {
  692. videomode = (int) simple_strtoul(penv, NULL, 16);
  693. tmp = 1;
  694. }
  695. } else {
  696. tmp = 1;
  697. }
  698. if (tmp) {
  699. /* parameter are vesa modes */
  700. /* search params */
  701. for (i = 0; i < VESA_MODES_COUNT; i++) {
  702. if (vesa_modes[i].vesanr == videomode)
  703. break;
  704. }
  705. if (i == VESA_MODES_COUNT) {
  706. printf("No VESA Mode found, switching to mode 0x%x ",
  707. CONFIG_SYS_DEFAULT_VIDEO_MODE);
  708. i = 0;
  709. }
  710. mode = (struct ctfb_res_modes *)
  711. &res_mode_init[vesa_modes[i].resindex];
  712. bits_per_pixel = vesa_modes[i].bits_per_pixel;
  713. } else {
  714. mode = (struct ctfb_res_modes *) &var_mode;
  715. bits_per_pixel = video_get_params(mode, penv);
  716. }
  717. /* calculate hsynch and vsynch freq (info only) */
  718. t1 = (mode->left_margin + mode->xres +
  719. mode->right_margin + mode->hsync_len) / 8;
  720. t1 *= 8;
  721. t1 *= mode->pixclock;
  722. t1 /= 1000;
  723. hsynch = 1000000000L / t1;
  724. t1 *= (mode->upper_margin + mode->yres +
  725. mode->lower_margin + mode->vsync_len);
  726. t1 /= 1000;
  727. vsynch = 1000000000L / t1;
  728. /* fill in Graphic device struct */
  729. sprintf(panel.modeIdent, "%dx%dx%d %ldkHz %ldHz",
  730. mode->xres, mode->yres,
  731. bits_per_pixel, (hsynch / 1000), (vsynch / 1000));
  732. printf("%s\n", panel.modeIdent);
  733. panel.winSizeX = mode->xres;
  734. panel.winSizeY = mode->yres;
  735. panel.plnSizeX = mode->xres;
  736. panel.plnSizeY = mode->yres;
  737. switch (bits_per_pixel) {
  738. case 24:
  739. panel.gdfBytesPP = 4;
  740. panel.gdfIndex = GDF_32BIT_X888RGB;
  741. break;
  742. case 16:
  743. panel.gdfBytesPP = 2;
  744. panel.gdfIndex = GDF_16BIT_565RGB;
  745. break;
  746. default:
  747. panel.gdfBytesPP = 1;
  748. panel.gdfIndex = GDF__8BIT_INDEX;
  749. break;
  750. }
  751. /* set up Hardware */
  752. memsize = calc_fbsize();
  753. debug("%s() allocating %d bytes\n", __func__, memsize);
  754. /* fill in missing Graphic device struct */
  755. panel.frameAdrs = (u32) malloc(memsize);
  756. if (panel.frameAdrs == 0) {
  757. printf("%s() malloc(%d) failed\n", __func__, memsize);
  758. return 0;
  759. }
  760. panel.memSize = memsize;
  761. ll_disp3_enable((void *) panel.frameAdrs);
  762. memset((void *) panel.frameAdrs, 0, memsize);
  763. debug("%s() done, framebuffer at 0x%x, size=%d cleared\n",
  764. __func__, panel.frameAdrs, memsize);
  765. return (void *) &panel;
  766. }