mvebu_lcd.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Video driver for Marvell Armada XP SoC
  4. *
  5. * Initialization of LCD interface and setup of SPLASH screen image
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <video.h>
  10. #include <dm/device_compat.h>
  11. #include <linux/mbus.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/cpu.h>
  14. #include <asm/arch/soc.h>
  15. #define MVEBU_LCD_WIN_CONTROL(w) (0xf000 + ((w) << 4))
  16. #define MVEBU_LCD_WIN_BASE(w) (0xf004 + ((w) << 4))
  17. #define MVEBU_LCD_WIN_REMAP(w) (0xf00c + ((w) << 4))
  18. #define MVEBU_LCD_CFG_DMA_START_ADDR_0 0x00cc
  19. #define MVEBU_LCD_CFG_DMA_START_ADDR_1 0x00dc
  20. #define MVEBU_LCD_CFG_GRA_START_ADDR0 0x00f4
  21. #define MVEBU_LCD_CFG_GRA_START_ADDR1 0x00f8
  22. #define MVEBU_LCD_CFG_GRA_PITCH 0x00fc
  23. #define MVEBU_LCD_SPU_GRA_OVSA_HPXL_VLN 0x0100
  24. #define MVEBU_LCD_SPU_GRA_HPXL_VLN 0x0104
  25. #define MVEBU_LCD_SPU_GZM_HPXL_VLN 0x0108
  26. #define MVEBU_LCD_SPU_HWC_OVSA_HPXL_VLN 0x010c
  27. #define MVEBU_LCD_SPU_HWC_HPXL_VLN 0x0110
  28. #define MVEBU_LCD_SPUT_V_H_TOTAL 0x0114
  29. #define MVEBU_LCD_SPU_V_H_ACTIVE 0x0118
  30. #define MVEBU_LCD_SPU_H_PORCH 0x011c
  31. #define MVEBU_LCD_SPU_V_PORCH 0x0120
  32. #define MVEBU_LCD_SPU_BLANKCOLOR 0x0124
  33. #define MVEBU_LCD_SPU_ALPHA_COLOR1 0x0128
  34. #define MVEBU_LCD_SPU_ALPHA_COLOR2 0x012c
  35. #define MVEBU_LCD_SPU_COLORKEY_Y 0x0130
  36. #define MVEBU_LCD_SPU_COLORKEY_U 0x0134
  37. #define MVEBU_LCD_SPU_COLORKEY_V 0x0138
  38. #define MVEBU_LCD_CFG_RDREG4F 0x013c
  39. #define MVEBU_LCD_SPU_SPI_RXDATA 0x0140
  40. #define MVEBU_LCD_SPU_ISA_RXDATA 0x0144
  41. #define MVEBU_LCD_SPU_DBG_ISA 0x0148
  42. #define MVEBU_LCD_SPU_HWC_RDDAT 0x0158
  43. #define MVEBU_LCD_SPU_GAMMA_RDDAT 0x015c
  44. #define MVEBU_LCD_SPU_PALETTE_RDDAT 0x0160
  45. #define MVEBU_LCD_SPU_IOPAD_IN 0x0178
  46. #define MVEBU_LCD_FRAME_COUNT 0x017c
  47. #define MVEBU_LCD_SPU_DMA_CTRL0 0x0190
  48. #define MVEBU_LCD_SPU_DMA_CTRL1 0x0194
  49. #define MVEBU_LCD_SPU_SRAM_CTRL 0x0198
  50. #define MVEBU_LCD_SPU_SRAM_WRDAT 0x019c
  51. #define MVEBU_LCD_SPU_SRAM_PARA0 0x01a0
  52. #define MVEBU_LCD_SPU_SRAM_PARA1 0x01a4
  53. #define MVEBU_LCD_CFG_SCLK_DIV 0x01a8
  54. #define MVEBU_LCD_SPU_CONTRAST 0x01ac
  55. #define MVEBU_LCD_SPU_SATURATION 0x01b0
  56. #define MVEBU_LCD_SPU_CBSH_HUE 0x01b4
  57. #define MVEBU_LCD_SPU_DUMB_CTRL 0x01b8
  58. #define MVEBU_LCD_SPU_IOPAD_CONTROL 0x01bc
  59. #define MVEBU_LCD_SPU_IRQ_ENA_2 0x01d8
  60. #define MVEBU_LCD_SPU_IRQ_ISR_2 0x01dc
  61. #define MVEBU_LCD_SPU_IRQ_ENA 0x01c0
  62. #define MVEBU_LCD_SPU_IRQ_ISR 0x01c4
  63. #define MVEBU_LCD_ADLL_CTRL 0x01c8
  64. #define MVEBU_LCD_CLK_DIS 0x01cc
  65. #define MVEBU_LCD_VGA_HVSYNC_DELAY 0x01d4
  66. #define MVEBU_LCD_CLK_CFG_0 0xf0a0
  67. #define MVEBU_LCD_CLK_CFG_1 0xf0a4
  68. #define MVEBU_LCD_LVDS_CLK_CFG 0xf0ac
  69. #define MVEBU_LVDS_PADS_REG (MVEBU_SYSTEM_REG_BASE + 0xf0)
  70. enum {
  71. /* Maximum LCD size we support */
  72. LCD_MAX_WIDTH = 640,
  73. LCD_MAX_HEIGHT = 480,
  74. LCD_MAX_LOG2_BPP = VIDEO_BPP16,
  75. };
  76. struct mvebu_lcd_info {
  77. u32 fb_base;
  78. int x_res;
  79. int y_res;
  80. int x_fp;
  81. int y_fp;
  82. int x_bp;
  83. int y_bp;
  84. };
  85. struct mvebu_video_priv {
  86. uintptr_t regs;
  87. };
  88. /* Setup Mbus Bridge Windows for LCD */
  89. static void mvebu_lcd_conf_mbus_registers(uintptr_t regs)
  90. {
  91. const struct mbus_dram_target_info *dram;
  92. int i;
  93. dram = mvebu_mbus_dram_info();
  94. /* Disable windows, set size/base/remap to 0 */
  95. for (i = 0; i < 6; i++) {
  96. writel(0, regs + MVEBU_LCD_WIN_CONTROL(i));
  97. writel(0, regs + MVEBU_LCD_WIN_BASE(i));
  98. writel(0, regs + MVEBU_LCD_WIN_REMAP(i));
  99. }
  100. /* Write LCD bridge window registers */
  101. for (i = 0; i < dram->num_cs; i++) {
  102. const struct mbus_dram_window *cs = dram->cs + i;
  103. writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
  104. (dram->mbus_dram_target_id << 4) | 1,
  105. regs + MVEBU_LCD_WIN_CONTROL(i));
  106. writel(cs->base & 0xffff0000, regs + MVEBU_LCD_WIN_BASE(i));
  107. }
  108. }
  109. /* Initialize LCD registers */
  110. static void mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info,
  111. uintptr_t regs)
  112. {
  113. /* Local variable for easier handling */
  114. int x = lcd_info->x_res;
  115. int y = lcd_info->y_res;
  116. u32 val;
  117. /* Setup Mbus Bridge Windows */
  118. mvebu_lcd_conf_mbus_registers(regs);
  119. /*
  120. * Set LVDS Pads Control Register
  121. * wr 0 182F0 FFE00000
  122. */
  123. clrbits_le32(MVEBU_LVDS_PADS_REG, 0x1f << 16);
  124. /*
  125. * Set the LCD_CFG_GRA_START_ADDR0/1 Registers
  126. * This is supposed to point to the "physical" memory at memory
  127. * end (currently 1GB-64MB but also may be 2GB-64MB).
  128. * See also the Window 0 settings!
  129. */
  130. writel(lcd_info->fb_base, regs + MVEBU_LCD_CFG_GRA_START_ADDR0);
  131. writel(lcd_info->fb_base, regs + MVEBU_LCD_CFG_GRA_START_ADDR1);
  132. /*
  133. * Set the LCD_CFG_GRA_PITCH Register
  134. * Bits 31-28: Duty Cycle of Backlight. value/16=High (0x8=Mid Setting)
  135. * Bits 25-16: Backlight divider from 32kHz Clock
  136. * (here 16=0x10 for 1kHz)
  137. * Bits 15-00: Line Length in Bytes
  138. * 240*2 (for RGB1555)=480=0x1E0
  139. */
  140. writel(0x80100000 + 2 * x, regs + MVEBU_LCD_CFG_GRA_PITCH);
  141. /*
  142. * Set the LCD_SPU_GRA_OVSA_HPXL_VLN Register
  143. * Bits 31-16: Vertical start of graphical overlay on screen
  144. * Bits 15-00: Horizontal start of graphical overlay on screen
  145. */
  146. writel(0x00000000, regs + MVEBU_LCD_SPU_GRA_OVSA_HPXL_VLN);
  147. /*
  148. * Set the LCD_SPU_GRA_HPXL_VLN Register
  149. * Bits 31-16: Vertical size of graphical overlay 320=0x140
  150. * Bits 15-00: Horizontal size of graphical overlay 240=0xF0
  151. * Values before zooming
  152. */
  153. writel((y << 16) | x, regs + MVEBU_LCD_SPU_GRA_HPXL_VLN);
  154. /*
  155. * Set the LCD_SPU_GZM_HPXL_VLN Register
  156. * Bits 31-16: Vertical size of graphical overlay 320=0x140
  157. * Bits 15-00: Horizontal size of graphical overlay 240=0xF0
  158. * Values after zooming
  159. */
  160. writel((y << 16) | x, regs + MVEBU_LCD_SPU_GZM_HPXL_VLN);
  161. /*
  162. * Set the LCD_SPU_HWC_OVSA_HPXL_VLN Register
  163. * Bits 31-16: Vertical position of HW Cursor 320=0x140
  164. * Bits 15-00: Horizontal position of HW Cursor 240=0xF0
  165. */
  166. writel((y << 16) | x, regs + MVEBU_LCD_SPU_HWC_OVSA_HPXL_VLN);
  167. /*
  168. * Set the LCD_SPU_HWC_OVSA_HPXL_VLN Register
  169. * Bits 31-16: Vertical size of HW Cursor
  170. * Bits 15-00: Horizontal size of HW Cursor
  171. */
  172. writel(0x00000000, regs + MVEBU_LCD_SPU_HWC_HPXL_VLN);
  173. /*
  174. * Set the LCD_SPU_HWC_OVSA_HPXL_VLN Register
  175. * Bits 31-16: Screen total vertical lines:
  176. * VSYNC = 1
  177. * Vertical Front Porch = 2
  178. * Vertical Lines = 320
  179. * Vertical Back Porch = 2
  180. * SUM = 325 = 0x0145
  181. * Bits 15-00: Screen total horizontal pixels:
  182. * HSYNC = 1
  183. * Horizontal Front Porch = 44
  184. * Horizontal Lines = 240
  185. * Horizontal Back Porch = 2
  186. * SUM = 287 = 0x011F
  187. * Note: For the display the backporch is between SYNC and
  188. * the start of the pixels.
  189. * This is not certain for the Marvell (!?)
  190. */
  191. val = ((y + lcd_info->y_fp + lcd_info->y_bp + 1) << 16) |
  192. (x + lcd_info->x_fp + lcd_info->x_bp + 1);
  193. writel(val, regs + MVEBU_LCD_SPUT_V_H_TOTAL);
  194. /*
  195. * Set the LCD_SPU_V_H_ACTIVE Register
  196. * Bits 31-16: Screen active vertical lines 320=0x140
  197. * Bits 15-00: Screen active horizontakl pixels 240=0x00F0
  198. */
  199. writel((y << 16) | x, regs + MVEBU_LCD_SPU_V_H_ACTIVE);
  200. /*
  201. * Set the LCD_SPU_H_PORCH Register
  202. * Bits 31-16: Screen horizontal backporch 44=0x2c
  203. * Bits 15-00: Screen horizontal frontporch 2=0x02
  204. * Note: The terms "front" and "back" for the Marvell seem to be
  205. * exactly opposite to the display.
  206. */
  207. writel((lcd_info->x_fp << 16) | lcd_info->x_bp,
  208. regs + MVEBU_LCD_SPU_H_PORCH);
  209. /*
  210. * Set the LCD_SPU_V_PORCH Register
  211. * Bits 31-16: Screen vertical backporch 2=0x02
  212. * Bits 15-00: Screen vertical frontporch 2=0x02
  213. * Note: The terms "front" and "back" for the Marvell seem to be exactly
  214. * opposite to the display.
  215. */
  216. writel((lcd_info->y_fp << 16) | lcd_info->y_bp,
  217. regs + MVEBU_LCD_SPU_V_PORCH);
  218. /*
  219. * Set the LCD_SPU_BLANKCOLOR Register
  220. * This should be black = 0
  221. * For tests this is magenta=00FF00FF
  222. */
  223. writel(0x00FF00FF, regs + MVEBU_LCD_SPU_BLANKCOLOR);
  224. /*
  225. * Registers in the range of 0x0128 to 0x012C are colors for the cursor
  226. * Registers in the range of 0x0130 to 0x0138 are colors for video
  227. * color keying
  228. */
  229. /*
  230. * Set the LCD_SPU_RDREG4F Register
  231. * Bits 31-12: Reservd
  232. * Bit 11: SRAM Wait
  233. * Bit 10: Smart display fast TX (must be 1)
  234. * Bit 9: DMA Arbitration Video/Graphics overlay: 0=interleaved
  235. * Bit 8: FIFO watermark for DMA: 0=disable
  236. * Bits 07-00: Empty 8B FIFO entries to trigger DMA, default=0x80
  237. */
  238. writel(0x00000780, regs + MVEBU_LCD_CFG_RDREG4F);
  239. /*
  240. * Set the LCD_SPU_DMACTRL 0 Register
  241. * Bit 31: Disable overlay blending 1=disable
  242. * Bit 30: Gamma correction enable, 0=disable
  243. * Bit 29: Video Contrast/Saturation/Hue Adjust enable, 0=disable
  244. * Bit 28: Color palette enable, 0=disable
  245. * Bit 27: DMA AXI Arbiter, 1=default
  246. * Bit 26: HW Cursor 1-bit mode
  247. * Bit 25: HW Cursor or 1- or 2-bit mode
  248. * Bit 24: HW Cursor enabled, 0=disable
  249. * Bits 23-20: Graphics Memory Color Format: 0x1=RGB1555
  250. * Bits 19-16: Video Memory Color Format: 0x1=RGB1555
  251. * Bit 15: Memory Toggle between frame 0 and 1: 0=disable
  252. * Bit 14: Graphics horizontal scaling enable: 0=disable
  253. * Bit 13: Graphics test mode: 0=disable
  254. * Bit 12: Graphics SWAP R and B: 0=disable
  255. * Bit 11: Graphics SWAP U and V: 0=disable
  256. * Bit 10: Graphics SWAP Y and U/V: 0=disable
  257. * Bit 09: Graphic YUV to RGB Conversion: 0=disable
  258. * Bit 08: Graphic Transfer: 1=enable
  259. * Bit 07: Memory Toggle: 0=disable
  260. * Bit 06: Video horizontal scaling enable: 0=disable
  261. * Bit 05: Video test mode: 0=disable
  262. * Bit 04: Video SWAP R and B: 0=disable
  263. * Bit 03: Video SWAP U and V: 0=disable
  264. * Bit 02: Video SWAP Y and U/V: 0=disable
  265. * Bit 01: Video YUV to RGB Conversion: 0=disable
  266. * Bit 00: Video Transfer: 0=disable
  267. */
  268. writel(0x88111100, regs + MVEBU_LCD_SPU_DMA_CTRL0);
  269. /*
  270. * Set the LCD_SPU_DMA_CTRL1 Register
  271. * Bit 31: Manual DMA Trigger = 0
  272. * Bits 30-28: DMA Trigger Source: 0x2 VSYNC
  273. * Bit 28: VSYNC_INV: 0=Rising Edge, 1=Falling Edge
  274. * Bits 26-24: Color Key Mode: 0=disable
  275. * Bit 23: Fill low bits: 0=fill with zeroes
  276. * Bit 22: Reserved
  277. * Bit 21: Gated Clock: 0=disable
  278. * Bit 20: Power Save enable: 0=disable
  279. * Bits 19-18: Reserved
  280. * Bits 17-16: Configure Video/Graphic Path: 0x1: Graphic path alpha.
  281. * Bits 15-08: Configure Alpha: 0x00.
  282. * Bits 07-00: Reserved.
  283. */
  284. writel(0x20010000, regs + MVEBU_LCD_SPU_DMA_CTRL1);
  285. /*
  286. * Set the LCD_SPU_SRAM_CTRL Register
  287. * Reset to default = 0000C000
  288. * Bits 15-14: SRAM control: init=0x3, Read=0, Write=2
  289. * Bits 11-08: SRAM address ID: 0=gamma_yr, 1=gammy_ug, 2=gamma_vb,
  290. * 3=palette, 15=cursor
  291. */
  292. writel(0x0000C000, regs + MVEBU_LCD_SPU_SRAM_CTRL);
  293. /*
  294. * LCD_SPU_SRAM_WRDAT register: 019C
  295. * LCD_SPU_SRAM_PARA0 register: 01A0
  296. * LCD_SPU_SRAM_PARA1 register: 01A4 - Cursor control/Power settings
  297. */
  298. writel(0x00000000, regs + MVEBU_LCD_SPU_SRAM_PARA1);
  299. /* Clock settings in the at 01A8 and in the range F0A0 see below */
  300. /*
  301. * Set LCD_SPU_CONTRAST
  302. * Bits 31-16: Brightness sign ext. 8-bit value +255 to -255: default=0
  303. * Bits 15-00: Contrast sign ext. 8-bit value +255 to -255: default=0
  304. */
  305. writel(0x00000000, regs + MVEBU_LCD_SPU_CONTRAST);
  306. /*
  307. * Set LCD_SPU_SATURATION
  308. * Bits 31-16: Multiplier signed 4.12 fixed point value
  309. * Bits 15-00: Saturation signed 4.12 fixed point value
  310. */
  311. writel(0x10001000, regs + MVEBU_LCD_SPU_SATURATION);
  312. /*
  313. * Set LCD_SPU_HUE
  314. * Bits 31-16: Sine signed 2.14 fixed point value
  315. * Bits 15-00: Cosine signed 2.14 fixed point value
  316. */
  317. writel(0x00000000, regs + MVEBU_LCD_SPU_CBSH_HUE);
  318. /*
  319. * Set LCD_SPU_DUMB_CTRL
  320. * Bits 31-28: LCD Type: 3=18 bit RGB | 6=24 bit RGB888
  321. * Bits 27-12: Reserved
  322. * Bit 11: LCD DMA Pipeline Enable: 1=Enable
  323. * Bits 10-09: Reserved
  324. * Bit 8: LCD GPIO pin (??)
  325. * Bit 7: Reverse RGB
  326. * Bit 6: Invert composite blank signal DE/EN (??)
  327. * Bit 5: Invert composite sync signal
  328. * Bit 4: Invert Pixel Valid Enable DE/EN (??)
  329. * Bit 3: Invert VSYNC
  330. * Bit 2: Invert HSYNC
  331. * Bit 1: Invert Pixel Clock
  332. * Bit 0: Enable LCD Panel: 1=Enable
  333. * Question: Do we have to disable Smart and Dumb LCD
  334. * and separately enable LVDS?
  335. */
  336. writel(0x6000080F, regs + MVEBU_LCD_SPU_DUMB_CTRL);
  337. /*
  338. * Set LCD_SPU_IOPAD_CTRL
  339. * Bits 31-20: Reserved
  340. * Bits 19-18: Vertical Interpolation: 0=Disable
  341. * Bits 17-16: Reserved
  342. * Bit 15: Graphics Vertical Mirror enable: 0=disable
  343. * Bit 14: Reserved
  344. * Bit 13: Video Vertical Mirror enable: 0=disable
  345. * Bit 12: Reserved
  346. * Bit 11: Command Vertical Mirror enable: 0=disable
  347. * Bit 10: Reserved
  348. * Bits 09-08: YUV to RGB Color space conversion: 0 (Not used)
  349. * Bits 07-04: AXI Bus Master: 0x4: no crossing of 4k boundary,
  350. * 128 Bytes burst
  351. * Bits 03-00: LCD pins: ??? 0=24-bit Dump panel ??
  352. */
  353. writel(0x000000C0, regs + MVEBU_LCD_SPU_IOPAD_CONTROL);
  354. /*
  355. * Set SUP_IRQ_ENA_2: Disable all interrupts
  356. */
  357. writel(0x00000000, regs + MVEBU_LCD_SPU_IRQ_ENA_2);
  358. /*
  359. * Set SUP_IRQ_ENA: Disable all interrupts.
  360. */
  361. writel(0x00000000, regs + MVEBU_LCD_SPU_IRQ_ENA);
  362. /*
  363. * Set up ADDL Control Register
  364. * Bits 31-29: 0x0 = Fastest Delay Line (default)
  365. * 0x3 = Slowest Delay Line (default)
  366. * Bit 28: Calibration done status.
  367. * Bit 27: Reserved
  368. * Bit 26: Set Pixel Clock to ADDL output
  369. * Bit 25: Reduce CAL Enable
  370. * Bits 24-22: Manual calibration value.
  371. * Bit 21: Manual calibration enable.
  372. * Bit 20: Restart Auto Cal
  373. * Bits 19-16: Calibration Threshold voltage, default= 0x2
  374. * Bite 15-14: Reserved
  375. * Bits 13-11: Divisor for ADDL Clock: 0x1=/2, 0x3=/8, 0x5=/16
  376. * Bit 10: Power Down ADDL module, default = 1!
  377. * Bits 09-08: Test point configuration: 0x2=Bias, 0x3=High-z
  378. * Bit 07: Reset ADDL
  379. * Bit 06: Invert ADLL Clock
  380. * Bits 05-00: Delay taps, 0x3F=Half Cycle, 0x00=No delay
  381. * Note: ADLL is used for a VGA interface with DAC - not used here
  382. */
  383. writel(0x00000000, regs + MVEBU_LCD_ADLL_CTRL);
  384. /*
  385. * Set the LCD_CLK_DIS Register:
  386. * Bits 3 and 4 must be 1
  387. */
  388. writel(0x00000018, regs + MVEBU_LCD_CLK_DIS);
  389. /*
  390. * Set the LCD_VGA_HSYNC/VSYNC Delay Register:
  391. * Bits 03-00: Sets the delay for the HSYNC and VSYNC signals
  392. */
  393. writel(0x00000000, regs + MVEBU_LCD_VGA_HVSYNC_DELAY);
  394. /*
  395. * Clock registers
  396. * See page 475 in the functional spec.
  397. */
  398. /* Step 1 and 2: Disable the PLL */
  399. /*
  400. * Disable PLL, see "LCD Clock Configuration 1 Register" below
  401. */
  402. writel(0x8FF40007, regs + MVEBU_LCD_CLK_CFG_1);
  403. /*
  404. * Powerdown, see "LCD Clock Configuration 0 Register" below
  405. */
  406. writel(0x94000174, regs + MVEBU_LCD_CLK_CFG_0);
  407. /*
  408. * Set the LCD_CFG_SCLK_DIV Register
  409. * This is set fix to 0x40000001 for the LVDS output:
  410. * Bits 31-30: SCLCK Source: 0=AXIBus, 1=AHBus, 2=PLLDivider0
  411. * Bits 15-01: Clock Divider: Bypass for LVDS=0x0001
  412. * See page 475 in section 28.5.
  413. */
  414. writel(0x80000001, regs + MVEBU_LCD_CFG_SCLK_DIV);
  415. /*
  416. * Set the LCD Clock Configuration 0 Register:
  417. * Bit 31: Powerdown: 0=Power up
  418. * Bits 30-29: Reserved
  419. * Bits 28-26: PLL_KDIV: This encodes K
  420. * K=16 => 0x5
  421. * Bits 25-17: PLL_MDIV: This is M-1:
  422. * M=1 => 0x0
  423. * Bits 16-13: VCO band: 0x1 for 700-920MHz
  424. * Bits 12-04: PLL_NDIV: This is N-1 and corresponds to R1_CTRL!
  425. * N=28=0x1C => 0x1B
  426. * Bits 03-00: R1_CTRL (for N=28 => 0x4)
  427. */
  428. writel(0x940021B4, regs + MVEBU_LCD_CLK_CFG_0);
  429. /*
  430. * Set the LCD Clock Configuration 1 Register:
  431. * Bits 31-19: Reserved
  432. * Bit 18: Select PLL: Core PLL, 1=Dedicated PPL
  433. * Bit 17: Clock Output Enable: 0=disable, 1=enable
  434. * Bit 16: Select RefClk: 0=RefClk (25MHz), 1=External
  435. * Bit 15: Half-Div, Device Clock by DIV+0.5*Half-Dev
  436. * Bits 14-13: Reserved
  437. * Bits 12-00: PLL Full Divider [Note: Assumed to be the Post-Divider
  438. * M' for LVDS=7!]
  439. */
  440. writel(0x8FF40007, regs + MVEBU_LCD_CLK_CFG_1);
  441. /*
  442. * Set the LVDS Clock Configuration Register:
  443. * Bit 31: Clock Gating for the input clock to the LVDS
  444. * Bit 30: LVDS Serializer enable: 1=Enabled
  445. * Bits 29-11: Reserved
  446. * Bit 11-08: LVDS Clock delay: 0x02 (default): by 2 pixel clock/7
  447. * Bits 07-02: Reserved
  448. * Bit 01: 24bbp Option: 0=Option_1,1=Option2
  449. * Bit 00: 1=24bbp Panel: 0=18bpp Panel
  450. * Note: Bits 0 and must be verified with the help of the
  451. * Interface/display
  452. */
  453. writel(0xC0000201, regs + MVEBU_LCD_LVDS_CLK_CFG);
  454. /*
  455. * Power up PLL (Clock Config 0)
  456. */
  457. writel(0x140021B4, regs + MVEBU_LCD_CLK_CFG_0);
  458. /* wait 10 ms */
  459. mdelay(10);
  460. /*
  461. * Enable PLL (Clock Config 1)
  462. */
  463. writel(0x8FF60007, regs + MVEBU_LCD_CLK_CFG_1);
  464. }
  465. static int mvebu_video_probe(struct udevice *dev)
  466. {
  467. struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
  468. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  469. struct mvebu_video_priv *priv = dev_get_priv(dev);
  470. struct mvebu_lcd_info lcd_info;
  471. struct display_timing timings;
  472. u32 fb_start, fb_end;
  473. int ret;
  474. priv->regs = dev_read_addr(dev);
  475. if (priv->regs == FDT_ADDR_T_NONE) {
  476. dev_err(dev, "failed to get LCD address\n");
  477. return -ENXIO;
  478. }
  479. ret = ofnode_decode_display_timing(dev_ofnode(dev), 0, &timings);
  480. if (ret) {
  481. dev_err(dev, "failed to get any display timings\n");
  482. return -EINVAL;
  483. }
  484. /* Use DT timing (resolution) in internal info struct */
  485. lcd_info.fb_base = plat->base;
  486. lcd_info.x_res = timings.hactive.typ;
  487. lcd_info.x_fp = timings.hfront_porch.typ;
  488. lcd_info.x_bp = timings.hback_porch.typ;
  489. lcd_info.y_res = timings.vactive.typ;
  490. lcd_info.y_fp = timings.vfront_porch.typ;
  491. lcd_info.y_bp = timings.vback_porch.typ;
  492. /* Initialize the LCD controller */
  493. mvebu_lcd_register_init(&lcd_info, priv->regs);
  494. /* Enable dcache for the frame buffer */
  495. fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
  496. fb_end = plat->base + plat->size;
  497. fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
  498. mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
  499. DCACHE_WRITEBACK);
  500. video_set_flush_dcache(dev, true);
  501. uc_priv->xsize = lcd_info.x_res;
  502. uc_priv->ysize = lcd_info.y_res;
  503. uc_priv->bpix = VIDEO_BPP16; /* Uses RGB555 format */
  504. return 0;
  505. }
  506. static int mvebu_video_bind(struct udevice *dev)
  507. {
  508. struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
  509. plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
  510. (1 << LCD_MAX_LOG2_BPP) / 8;
  511. return 0;
  512. }
  513. static const struct udevice_id mvebu_video_ids[] = {
  514. { .compatible = "marvell,armada-xp-lcd" },
  515. { }
  516. };
  517. U_BOOT_DRIVER(mvebu_video) = {
  518. .name = "mvebu_video",
  519. .id = UCLASS_VIDEO,
  520. .of_match = mvebu_video_ids,
  521. .bind = mvebu_video_bind,
  522. .probe = mvebu_video_probe,
  523. .priv_auto_alloc_size = sizeof(struct mvebu_video_priv),
  524. };