mb862xx.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007
  4. * DENX Software Engineering, Anatolij Gustschin, agust@denx.de
  5. */
  6. /*
  7. * mb862xx.c - Graphic interface for Fujitsu CoralP/Lime
  8. * PCI and video mode code was derived from smiLynxEM driver.
  9. */
  10. #include <common.h>
  11. #include <asm/io.h>
  12. #include <env.h>
  13. #include <pci.h>
  14. #include <video_fb.h>
  15. #include "videomodes.h"
  16. #include <mb862xx.h>
  17. #if defined(CONFIG_POST)
  18. #include <post.h>
  19. #endif
  20. /*
  21. * Graphic Device
  22. */
  23. GraphicDevice mb862xx;
  24. /*
  25. * 32MB external RAM - 256K Chip MMIO = 0x1FC0000 ;
  26. */
  27. #define VIDEO_MEM_SIZE 0x01FC0000
  28. #if defined(CONFIG_PCI)
  29. #if defined(CONFIG_VIDEO_CORALP)
  30. static struct pci_device_id supported[] = {
  31. { PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_P },
  32. { PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_PA },
  33. { }
  34. };
  35. /* Internal clock frequency divider table, index is mode number */
  36. unsigned int fr_div[] = { 0x00000f00, 0x00000900, 0x00000500 };
  37. #endif
  38. #endif
  39. #if defined(CONFIG_VIDEO_CORALP)
  40. #define rd_io in32r
  41. #define wr_io out32r
  42. #else
  43. #define rd_io(addr) in_be32((volatile unsigned *)(addr))
  44. #define wr_io(addr, val) out_be32((volatile unsigned *)(addr), (val))
  45. #endif
  46. #define HOST_RD_REG(off) rd_io((dev->frameAdrs + GC_HOST_BASE + (off)))
  47. #define HOST_WR_REG(off, val) wr_io((dev->frameAdrs + GC_HOST_BASE + (off)), \
  48. (val))
  49. #define DISP_RD_REG(off) rd_io((dev->frameAdrs + GC_DISP_BASE + (off)))
  50. #define DISP_WR_REG(off, val) wr_io((dev->frameAdrs + GC_DISP_BASE + (off)), \
  51. (val))
  52. #define DE_RD_REG(off) rd_io((dev->dprBase + (off)))
  53. #define DE_WR_REG(off, val) wr_io((dev->dprBase + (off)), (val))
  54. #if defined(CONFIG_VIDEO_CORALP)
  55. #define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_GEO_FIFO)), (val))
  56. #else
  57. #define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_FIFO)), (val))
  58. #endif
  59. #define L0PAL_WR_REG(idx, val) wr_io((dev->frameAdrs + \
  60. (GC_DISP_BASE | GC_L0PAL0) + \
  61. ((idx) << 2)), (val))
  62. #if defined(CONFIG_VIDEO_MB862xx_ACCEL)
  63. static void gdc_sw_reset (void)
  64. {
  65. GraphicDevice *dev = &mb862xx;
  66. HOST_WR_REG (GC_SRST, 0x1);
  67. udelay (500);
  68. video_hw_init ();
  69. }
  70. static void de_wait (void)
  71. {
  72. GraphicDevice *dev = &mb862xx;
  73. int lc = 0x10000;
  74. /*
  75. * Sync with software writes to framebuffer,
  76. * try to reset if engine locked
  77. */
  78. while (DE_RD_REG (GC_CTR) & 0x00000131)
  79. if (lc-- < 0) {
  80. gdc_sw_reset ();
  81. puts ("gdc reset done after drawing engine lock.\n");
  82. break;
  83. }
  84. }
  85. static void de_wait_slots (int slots)
  86. {
  87. GraphicDevice *dev = &mb862xx;
  88. int lc = 0x10000;
  89. /* Wait for free fifo slots */
  90. while (DE_RD_REG (GC_IFCNT) < slots)
  91. if (lc-- < 0) {
  92. gdc_sw_reset ();
  93. puts ("gdc reset done after drawing engine lock.\n");
  94. break;
  95. }
  96. }
  97. #endif
  98. #if !defined(CONFIG_VIDEO_CORALP)
  99. static void board_disp_init (void)
  100. {
  101. GraphicDevice *dev = &mb862xx;
  102. const gdc_regs *regs = board_get_regs ();
  103. while (regs->index) {
  104. DISP_WR_REG (regs->index, regs->value);
  105. regs++;
  106. }
  107. }
  108. #endif
  109. /*
  110. * Init drawing engine if accel enabled.
  111. * Also clears visible framebuffer.
  112. */
  113. static void de_init (void)
  114. {
  115. GraphicDevice *dev = &mb862xx;
  116. #if defined(CONFIG_VIDEO_MB862xx_ACCEL)
  117. int cf = (dev->gdfBytesPP == 1) ? 0x0000 : 0x8000;
  118. dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
  119. /* Setup mode and fbbase, xres, fg, bg */
  120. de_wait_slots (2);
  121. DE_WR_FIFO (0xf1010108);
  122. DE_WR_FIFO (cf | 0x0300);
  123. DE_WR_REG (GC_FBR, 0x0);
  124. DE_WR_REG (GC_XRES, dev->winSizeX);
  125. DE_WR_REG (GC_FC, 0x0);
  126. DE_WR_REG (GC_BC, 0x0);
  127. /* Reset clipping */
  128. DE_WR_REG (GC_CXMIN, 0x0);
  129. DE_WR_REG (GC_CXMAX, dev->winSizeX);
  130. DE_WR_REG (GC_CYMIN, 0x0);
  131. DE_WR_REG (GC_CYMAX, dev->winSizeY);
  132. /* Clear framebuffer using drawing engine */
  133. de_wait_slots (3);
  134. DE_WR_FIFO (0x09410000);
  135. DE_WR_FIFO (0x00000000);
  136. DE_WR_FIFO (dev->winSizeY << 16 | dev->winSizeX);
  137. /* sync with SW access to framebuffer */
  138. de_wait ();
  139. #else
  140. unsigned int i, *p;
  141. i = dev->winSizeX * dev->winSizeY;
  142. p = (unsigned int *)dev->frameAdrs;
  143. while (i--)
  144. *p++ = 0;
  145. #endif
  146. }
  147. #if defined(CONFIG_VIDEO_CORALP)
  148. /* use CCF and MMR parameters for Coral-P Eval. Board as default */
  149. #ifndef CONFIG_SYS_MB862xx_CCF
  150. #define CONFIG_SYS_MB862xx_CCF 0x00090000
  151. #endif
  152. #ifndef CONFIG_SYS_MB862xx_MMR
  153. #define CONFIG_SYS_MB862xx_MMR 0x11d7fa13
  154. #endif
  155. unsigned int pci_video_init (void)
  156. {
  157. GraphicDevice *dev = &mb862xx;
  158. pci_dev_t devbusfn;
  159. u16 device;
  160. if ((devbusfn = pci_find_devices (supported, 0)) < 0) {
  161. puts("controller not present\n");
  162. return 0;
  163. }
  164. /* PCI setup */
  165. pci_write_config_dword (devbusfn, PCI_COMMAND,
  166. (PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
  167. pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &dev->frameAdrs);
  168. dev->frameAdrs = pci_mem_to_phys (devbusfn, dev->frameAdrs);
  169. if (dev->frameAdrs == 0) {
  170. puts ("PCI config: failed to get base address\n");
  171. return 0;
  172. }
  173. dev->pciBase = dev->frameAdrs;
  174. puts("Coral-");
  175. pci_read_config_word(devbusfn, PCI_DEVICE_ID, &device);
  176. switch (device) {
  177. case PCI_DEVICE_ID_CORAL_P:
  178. puts("P\n");
  179. break;
  180. case PCI_DEVICE_ID_CORAL_PA:
  181. puts("PA\n");
  182. break;
  183. default:
  184. puts("Unknown\n");
  185. return 0;
  186. }
  187. /* Setup clocks and memory mode for Coral-P(A) */
  188. HOST_WR_REG(GC_CCF, CONFIG_SYS_MB862xx_CCF);
  189. udelay (200);
  190. HOST_WR_REG(GC_MMR, CONFIG_SYS_MB862xx_MMR);
  191. udelay (100);
  192. return dev->frameAdrs;
  193. }
  194. unsigned int card_init (void)
  195. {
  196. GraphicDevice *dev = &mb862xx;
  197. unsigned int cf, videomode, div = 0;
  198. unsigned long t1, hsync, vsync;
  199. char *penv;
  200. int tmp, i, bpp;
  201. struct ctfb_res_modes *res_mode;
  202. struct ctfb_res_modes var_mode;
  203. memset (dev, 0, sizeof (GraphicDevice));
  204. if (!pci_video_init ())
  205. return 0;
  206. tmp = 0;
  207. videomode = 0x310;
  208. /* get video mode via environment */
  209. penv = env_get("videomode");
  210. if (penv) {
  211. /* decide if it is a string */
  212. if (penv[0] <= '9') {
  213. videomode = (int) simple_strtoul (penv, NULL, 16);
  214. tmp = 1;
  215. }
  216. } else {
  217. tmp = 1;
  218. }
  219. if (tmp) {
  220. /* parameter are vesa modes, search params */
  221. for (i = 0; i < VESA_MODES_COUNT; i++) {
  222. if (vesa_modes[i].vesanr == videomode)
  223. break;
  224. }
  225. if (i == VESA_MODES_COUNT) {
  226. printf ("\tno VESA Mode found, fallback to mode 0x%x\n",
  227. videomode);
  228. i = 0;
  229. }
  230. res_mode = (struct ctfb_res_modes *)
  231. &res_mode_init[vesa_modes[i].resindex];
  232. if (vesa_modes[i].resindex > 2) {
  233. puts ("\tUnsupported resolution, using default\n");
  234. bpp = vesa_modes[1].bits_per_pixel;
  235. div = fr_div[1];
  236. }
  237. bpp = vesa_modes[i].bits_per_pixel;
  238. div = fr_div[vesa_modes[i].resindex];
  239. } else {
  240. res_mode = (struct ctfb_res_modes *) &var_mode;
  241. bpp = video_get_params (res_mode, penv);
  242. }
  243. /* calculate hsync and vsync freq (info only) */
  244. t1 = (res_mode->left_margin + res_mode->xres +
  245. res_mode->right_margin + res_mode->hsync_len) / 8;
  246. t1 *= 8;
  247. t1 *= res_mode->pixclock;
  248. t1 /= 1000;
  249. hsync = 1000000000L / t1;
  250. t1 *= (res_mode->upper_margin + res_mode->yres +
  251. res_mode->lower_margin + res_mode->vsync_len);
  252. t1 /= 1000;
  253. vsync = 1000000000L / t1;
  254. /* fill in Graphic device struct */
  255. sprintf (dev->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres,
  256. res_mode->yres, bpp, (hsync / 1000), (vsync / 1000));
  257. printf ("\t%s\n", dev->modeIdent);
  258. dev->winSizeX = res_mode->xres;
  259. dev->winSizeY = res_mode->yres;
  260. dev->memSize = VIDEO_MEM_SIZE;
  261. switch (bpp) {
  262. case 8:
  263. dev->gdfIndex = GDF__8BIT_INDEX;
  264. dev->gdfBytesPP = 1;
  265. break;
  266. case 15:
  267. case 16:
  268. dev->gdfIndex = GDF_15BIT_555RGB;
  269. dev->gdfBytesPP = 2;
  270. break;
  271. default:
  272. printf ("\t%d bpp configured, but only 8,15 and 16 supported\n",
  273. bpp);
  274. puts ("\tfallback to 15bpp\n");
  275. dev->gdfIndex = GDF_15BIT_555RGB;
  276. dev->gdfBytesPP = 2;
  277. }
  278. /* Setup dot clock (internal pll, division rate) */
  279. DISP_WR_REG (GC_DCM1, div);
  280. /* L0 init */
  281. cf = (dev->gdfBytesPP == 1) ? 0x00000000 : 0x80000000;
  282. DISP_WR_REG (GC_L0M, ((dev->winSizeX * dev->gdfBytesPP) / 64) << 16 |
  283. (dev->winSizeY - 1) | cf);
  284. DISP_WR_REG (GC_L0OA0, 0x0);
  285. DISP_WR_REG (GC_L0DA0, 0x0);
  286. DISP_WR_REG (GC_L0DY_L0DX, 0x0);
  287. DISP_WR_REG (GC_L0EM, 0x0);
  288. DISP_WR_REG (GC_L0WY_L0WX, 0x0);
  289. DISP_WR_REG (GC_L0WH_L0WW, (dev->winSizeY - 1) << 16 | dev->winSizeX);
  290. /* Display timing init */
  291. DISP_WR_REG (GC_HTP_A, (dev->winSizeX +
  292. res_mode->left_margin +
  293. res_mode->right_margin +
  294. res_mode->hsync_len - 1) << 16);
  295. DISP_WR_REG (GC_HDB_HDP_A, (dev->winSizeX - 1) << 16 |
  296. (dev->winSizeX - 1));
  297. DISP_WR_REG (GC_VSW_HSW_HSP_A, (res_mode->vsync_len - 1) << 24 |
  298. (res_mode->hsync_len - 1) << 16 |
  299. (dev->winSizeX +
  300. res_mode->right_margin - 1));
  301. DISP_WR_REG (GC_VTR_A, (dev->winSizeY + res_mode->lower_margin +
  302. res_mode->upper_margin +
  303. res_mode->vsync_len - 1) << 16);
  304. DISP_WR_REG (GC_VDP_VSP_A, (dev->winSizeY-1) << 16 |
  305. (dev->winSizeY +
  306. res_mode->lower_margin - 1));
  307. DISP_WR_REG (GC_WY_WX, 0x0);
  308. DISP_WR_REG (GC_WH_WW, dev->winSizeY << 16 | dev->winSizeX);
  309. /* Display enable, L0 layer */
  310. DISP_WR_REG (GC_DCM1, 0x80010000 | div);
  311. return dev->frameAdrs;
  312. }
  313. #endif
  314. #if !defined(CONFIG_VIDEO_CORALP)
  315. int mb862xx_probe(unsigned int addr)
  316. {
  317. GraphicDevice *dev = &mb862xx;
  318. unsigned int reg;
  319. dev->frameAdrs = addr;
  320. dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
  321. /* Try to access GDC ID/Revision registers */
  322. reg = HOST_RD_REG (GC_CID);
  323. reg = HOST_RD_REG (GC_CID);
  324. if (reg == 0x303) {
  325. reg = DE_RD_REG(GC_REV);
  326. reg = DE_RD_REG(GC_REV);
  327. if ((reg & ~0xff) == 0x20050100)
  328. return MB862XX_TYPE_LIME;
  329. }
  330. return 0;
  331. }
  332. #endif
  333. void *video_hw_init (void)
  334. {
  335. GraphicDevice *dev = &mb862xx;
  336. puts ("Video: Fujitsu ");
  337. memset (dev, 0, sizeof (GraphicDevice));
  338. #if defined(CONFIG_VIDEO_CORALP)
  339. if (card_init () == 0)
  340. return NULL;
  341. #else
  342. /*
  343. * Preliminary init of the onboard graphic controller,
  344. * retrieve base address
  345. */
  346. if ((dev->frameAdrs = board_video_init ()) == 0) {
  347. puts ("Controller not found!\n");
  348. return NULL;
  349. } else {
  350. puts ("Lime\n");
  351. /* Set Change of Clock Frequency Register */
  352. HOST_WR_REG (GC_CCF, CONFIG_SYS_MB862xx_CCF);
  353. /* Delay required */
  354. udelay(300);
  355. /* Set Memory I/F Mode Register) */
  356. HOST_WR_REG (GC_MMR, CONFIG_SYS_MB862xx_MMR);
  357. }
  358. #endif
  359. de_init ();
  360. #if !defined(CONFIG_VIDEO_CORALP)
  361. board_disp_init ();
  362. #endif
  363. #if (defined(CONFIG_LWMON5) || \
  364. defined(CONFIG_SOCRATES)) && !(CONFIG_POST & CONFIG_SYS_POST_SYSMON)
  365. /* Lamp on */
  366. board_backlight_switch (1);
  367. #endif
  368. return dev;
  369. }
  370. /*
  371. * Set a RGB color in the LUT
  372. */
  373. void video_set_lut (unsigned int index, unsigned char r,
  374. unsigned char g, unsigned char b)
  375. {
  376. GraphicDevice *dev = &mb862xx;
  377. L0PAL_WR_REG (index, (r << 16) | (g << 8) | (b));
  378. }
  379. #if defined(CONFIG_VIDEO_MB862xx_ACCEL)
  380. /*
  381. * Drawing engine Fill and BitBlt screen region
  382. */
  383. void video_hw_rectfill (unsigned int bpp, unsigned int dst_x,
  384. unsigned int dst_y, unsigned int dim_x,
  385. unsigned int dim_y, unsigned int color)
  386. {
  387. GraphicDevice *dev = &mb862xx;
  388. de_wait_slots (3);
  389. DE_WR_REG (GC_FC, color);
  390. DE_WR_FIFO (0x09410000);
  391. DE_WR_FIFO ((dst_y << 16) | dst_x);
  392. DE_WR_FIFO ((dim_y << 16) | dim_x);
  393. de_wait ();
  394. }
  395. void video_hw_bitblt (unsigned int bpp, unsigned int src_x,
  396. unsigned int src_y, unsigned int dst_x,
  397. unsigned int dst_y, unsigned int width,
  398. unsigned int height)
  399. {
  400. GraphicDevice *dev = &mb862xx;
  401. unsigned int ctrl = 0x0d000000L;
  402. if (src_x >= dst_x && src_y >= dst_y)
  403. ctrl |= 0x00440000L;
  404. else if (src_x >= dst_x && src_y <= dst_y)
  405. ctrl |= 0x00460000L;
  406. else if (src_x <= dst_x && src_y >= dst_y)
  407. ctrl |= 0x00450000L;
  408. else
  409. ctrl |= 0x00470000L;
  410. de_wait_slots (4);
  411. DE_WR_FIFO (ctrl);
  412. DE_WR_FIFO ((src_y << 16) | src_x);
  413. DE_WR_FIFO ((dst_y << 16) | dst_x);
  414. DE_WR_FIFO ((height << 16) | width);
  415. de_wait (); /* sync */
  416. }
  417. #endif