logicore_dp_tx.c 65 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * logicore_dp_tx.c
  4. *
  5. * Driver for XILINX LogiCore DisplayPort v6.1 TX (Source)
  6. * based on Xilinx dp_v3_1 driver sources, updated to dp_v4_0
  7. *
  8. * (C) Copyright 2016
  9. * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
  10. */
  11. #include <common.h>
  12. #include <clk.h>
  13. #include <display.h>
  14. #include <dm.h>
  15. #include <errno.h>
  16. #include "axi.h"
  17. #include "logicore_dp_dpcd.h"
  18. #include "logicore_dp_tx.h"
  19. #include "logicore_dp_tx_regif.h"
  20. /* Default AXI clock frequency value */
  21. #define S_AXI_CLK_DEFAULT 100000000
  22. /* Default DP phy clock value */
  23. #define PHY_CLOCK_SELECT_DEFAULT PHY_CLOCK_SELECT_540GBPS
  24. /* The maximum voltage swing level is 3 */
  25. #define MAXIMUM_VS_LEVEL 3
  26. /* The maximum pre-emphasis level is 3 */
  27. #define MAXIMUM_PE_LEVEL 3
  28. /* Error out if an AUX request yields a defer reply more than 50 times */
  29. #define AUX_MAX_DEFER_COUNT 50
  30. /* Error out if an AUX request times out more than 50 times awaiting a reply */
  31. #define AUX_MAX_TIMEOUT_COUNT 50
  32. /* Error out if checking for a connected device times out more than 50 times */
  33. #define IS_CONNECTED_MAX_TIMEOUT_COUNT 50
  34. /**
  35. * enum link_training_states - States for link training state machine
  36. * @TS_CLOCK_RECOVERY: State for clock recovery
  37. * @TS_CHANNEL_EQUALIZATION: State for channel equalization
  38. * @TS_ADJUST_LINK_RATE: State where link rate is reduced in reaction to
  39. * failed link training
  40. * @TS_ADJUST_LANE_COUNT: State where lane count is reduced in reaction to
  41. * failed link training
  42. * @TS_FAILURE: State of link training failure
  43. * @TS_SUCCESS:: State for successfully completed link training
  44. */
  45. enum link_training_states {
  46. TS_CLOCK_RECOVERY,
  47. TS_CHANNEL_EQUALIZATION,
  48. TS_ADJUST_LINK_RATE,
  49. TS_ADJUST_LANE_COUNT,
  50. TS_FAILURE,
  51. TS_SUCCESS
  52. };
  53. /**
  54. * struct aux_transaction - Description of an AUX channel transaction
  55. * @cmd_code: Command code of the transaction
  56. * @num_bytes: The number of bytes in the transaction's payload data
  57. * @address: The DPCD address of the transaction
  58. * @data: Payload data of the AUX channel transaction
  59. */
  60. struct aux_transaction {
  61. u16 cmd_code;
  62. u8 num_bytes;
  63. u32 address;
  64. u8 *data;
  65. };
  66. /**
  67. * struct main_stream_attributes - Main stream attributes
  68. * @pixel_clock_hz: Pixel clock of the stream (in Hz)
  69. * @misc_0: Miscellaneous stream attributes 0 as specified
  70. * by the DisplayPort 1.2 specification
  71. * @misc_1: Miscellaneous stream attributes 1 as specified
  72. * by the DisplayPort 1.2 specification
  73. * @n_vid: N value for the video stream
  74. * @m_vid: M value used to recover the video clock from the
  75. * link clock
  76. * @user_pixel_width: Width of the user data input port
  77. * @data_per_lane: Used to translate the number of pixels per line
  78. * to the native internal 16-bit datapath
  79. * @avg_bytes_per_tu: Average number of bytes per transfer unit,
  80. * scaled up by a factor of 1000
  81. * @transfer_unit_size: Size of the transfer unit in the framing logic
  82. * In MST mode, this is also the number of time
  83. * slots that are alloted in the payload ID table
  84. * @init_wait: Number of initial wait cycles at the start of a
  85. * new line by the framing logic
  86. * @bits_per_color: Bits per color component
  87. * @component_format: The component format currently in use by the
  88. * video stream
  89. * @dynamic_range: The dynamic range currently in use by the video
  90. * stream
  91. * @y_cb_cr_colorimetry: The YCbCr colorimetry currently in use by the
  92. * video stream
  93. * @synchronous_clock_mode: Synchronous clock mode is currently in use by
  94. * the video stream
  95. * @override_user_pixel_width: If set to 1, the value stored for
  96. * user_pixel_width will be used as the pixel width
  97. * @h_start: Horizontal blank start (pixels)
  98. * @h_active: Horizontal active resolution (pixels)
  99. * @h_sync_width: Horizontal sync width (pixels)
  100. * @h_total: Horizontal total (pixels)
  101. * @h_sync_polarity: Horizontal sync polarity (0=neg|1=pos)
  102. * @v_start: Vertical blank start (in lines)
  103. * @v_active: Vertical active resolution (lines)
  104. * @v_sync_width: Vertical sync width (lines)
  105. * @v_total: Vertical total (lines)
  106. * @v_sync_polarity: Vertical sync polarity (0=neg|1=pos)
  107. *
  108. * All porch parameters have been removed, because our videodata is
  109. * hstart/vstart based, and there is no benefit in keeping the porches
  110. */
  111. struct main_stream_attributes {
  112. u32 pixel_clock_hz;
  113. u32 misc_0;
  114. u32 misc_1;
  115. u32 n_vid;
  116. //u32 m_vid;
  117. u32 user_pixel_width;
  118. u32 data_per_lane;
  119. u32 avg_bytes_per_tu;
  120. u32 transfer_unit_size;
  121. u32 init_wait;
  122. u32 bits_per_color;
  123. u8 component_format;
  124. u8 dynamic_range;
  125. u8 y_cb_cr_colorimetry;
  126. u8 synchronous_clock_mode;
  127. u8 override_user_pixel_width;
  128. u32 h_start;
  129. u16 h_active;
  130. u16 h_sync_width;
  131. u16 h_total;
  132. bool h_sync_polarity;
  133. u32 v_start;
  134. u16 v_active;
  135. u16 v_sync_width;
  136. u16 v_total;
  137. bool v_sync_polarity;
  138. };
  139. /**
  140. * struct link_config - Description of link configuration
  141. * @lane_count: Currently selected lane count for this link
  142. * @link_rate: Currently selected link rate for this link
  143. * @scrambler_en: Flag to determine whether the scrambler is
  144. * enabled for this link
  145. * @enhanced_framing_mode: Flag to determine whether enhanced framing
  146. * mode is active for this link
  147. * @max_lane_count: Maximum lane count for this link
  148. * @max_link_rate: Maximum link rate for this link
  149. * @support_enhanced_framing_mode: Flag to indicate whether the link supports
  150. * enhanced framing mode
  151. * @vs_level: Voltage swing for each lane
  152. * @pe_level: Pre-emphasis/cursor level for each lane
  153. */
  154. struct link_config {
  155. u8 lane_count;
  156. u8 link_rate;
  157. bool scrambler_en;
  158. bool enhanced_framing_mode;
  159. u8 max_lane_count;
  160. u8 max_link_rate;
  161. bool support_enhanced_framing_mode;
  162. u8 vs_level;
  163. u8 pe_level;
  164. };
  165. /**
  166. * struct dp_tx - Private data structure of LogiCore DP TX devices
  167. *
  168. * @base: Address of register base of device
  169. * @s_axi_clk: The AXI clock frequency in Hz
  170. * @train_adaptive: Use adaptive link trainig (i.e. successively reduce
  171. * link rate and/or lane count) for this device
  172. * @max_link_rate: Maximum link rate for this device
  173. * @max_lane_count: Maximum lane count for this device
  174. * @dpcd_rx_caps: RX device's status registers, see below
  175. * @lane_status_ajd_reqs: Lane status and adjustment requests information for
  176. * this device
  177. * @link_config: The link configuration for this device
  178. * @main_stream_attributes: MSA set for this device
  179. *
  180. * dpcd_rx_caps is a raw read of the RX device's status registers. The first 4
  181. * bytes correspond to the lane status associated with clock recovery, channel
  182. * equalization, symbol lock, and interlane alignment. The remaining 2 bytes
  183. * represent the pre-emphasis and voltage swing level adjustments requested by
  184. * the RX device.
  185. */
  186. struct dp_tx {
  187. u32 base;
  188. u32 s_axi_clk;
  189. bool train_adaptive;
  190. u8 max_link_rate;
  191. u8 max_lane_count;
  192. u8 dpcd_rx_caps[16];
  193. u8 lane_status_ajd_reqs[6];
  194. struct link_config link_config;
  195. struct main_stream_attributes main_stream_attributes;
  196. };
  197. /*
  198. * Internal API
  199. */
  200. /**
  201. * get_reg() - Read a register of a LogiCore DP TX device
  202. * @dev: The LogiCore DP TX device in question
  203. * @reg: The offset of the register to read
  204. *
  205. * Return: The read register value
  206. */
  207. static u32 get_reg(struct udevice *dev, u32 reg)
  208. {
  209. struct dp_tx *dp_tx = dev_get_priv(dev);
  210. u32 value = 0;
  211. int res;
  212. /* TODO(mario.six@gdsys.cc): error handling */
  213. res = axi_read(dev->parent, dp_tx->base + reg, &value, AXI_SIZE_32);
  214. if (res < 0)
  215. printf("%s() failed; res = %d\n", __func__, res);
  216. return value;
  217. }
  218. /**
  219. * set_reg() - Write a register of a LogiCore DP TX device
  220. * @dev: The LogiCore DP TX device in question
  221. * @reg: The offset of the register to write
  222. * @value: The value to write to the register
  223. */
  224. static void set_reg(struct udevice *dev, u32 reg, u32 value)
  225. {
  226. struct dp_tx *dp_tx = dev_get_priv(dev);
  227. axi_write(dev->parent, dp_tx->base + reg, &value, AXI_SIZE_32);
  228. }
  229. /**
  230. * is_connected() - Check if there is a connected RX device
  231. * @dev: The LogiCore DP TX device in question
  232. *
  233. * The Xilinx original calls msleep_interruptible at least once, ignoring
  234. * status.
  235. *
  236. * Return: true if a connected RX device was detected, false otherwise
  237. */
  238. static bool is_connected(struct udevice *dev)
  239. {
  240. u8 retries = 0;
  241. do {
  242. int status = get_reg(dev, REG_INTERRUPT_SIG_STATE) &
  243. INTERRUPT_SIG_STATE_HPD_STATE_MASK;
  244. if (status)
  245. return true;
  246. udelay(1000);
  247. } while (retries++ < IS_CONNECTED_MAX_TIMEOUT_COUNT);
  248. return false;
  249. }
  250. /**
  251. * wait_phy_ready() - Wait for the DisplayPort PHY to come out of reset
  252. * @dev: The LogiCore DP TX device in question
  253. * @mask: Bit mask specifying which bit in the status register should be waited
  254. * for
  255. *
  256. * Return: 0 if wait succeeded, -ve if error occurred
  257. */
  258. static int wait_phy_ready(struct udevice *dev, u32 mask)
  259. {
  260. u16 timeout = 20000;
  261. u32 phy_status;
  262. /* Wait until the PHY is ready. */
  263. do {
  264. phy_status = get_reg(dev, REG_PHY_STATUS) & mask;
  265. /* Protect against an infinite loop. */
  266. if (!timeout--)
  267. return -ETIMEDOUT;
  268. udelay(20);
  269. } while (phy_status != mask);
  270. return 0;
  271. }
  272. /* AUX channel access */
  273. /**
  274. * aux_wait_ready() - Wait until another request is no longer in progress
  275. * @dev: The LogiCore DP TX device in question
  276. *
  277. * Return: 0 if wait succeeded, -ve if error occurred
  278. */
  279. static int aux_wait_ready(struct udevice *dev)
  280. {
  281. int status;
  282. u32 timeout = 100;
  283. /* Wait until the DisplayPort TX core is ready. */
  284. do {
  285. status = get_reg(dev, REG_INTERRUPT_SIG_STATE);
  286. /* Protect against an infinite loop. */
  287. if (!timeout--)
  288. return -ETIMEDOUT;
  289. udelay(20);
  290. } while (status & REPLY_STATUS_REPLY_IN_PROGRESS_MASK);
  291. return 0;
  292. }
  293. /**
  294. * aux_wait_reply() - Wait for reply on AUX channel
  295. * @dev: The LogiCore DP TX device in question
  296. *
  297. * Wait for a reply indicating that the most recent AUX request
  298. * has been received by the RX device.
  299. *
  300. * Return: 0 if wait succeeded, -ve if error occurred
  301. */
  302. static int aux_wait_reply(struct udevice *dev)
  303. {
  304. u32 timeout = 100;
  305. while (timeout > 0) {
  306. int status = get_reg(dev, REG_REPLY_STATUS);
  307. /* Check for error. */
  308. if (status & REPLY_STATUS_REPLY_ERROR_MASK)
  309. return -ETIMEDOUT;
  310. /* Check for a reply. */
  311. if ((status & REPLY_STATUS_REPLY_RECEIVED_MASK) &&
  312. !(status &
  313. REPLY_STATUS_REQUEST_IN_PROGRESS_MASK) &&
  314. !(status &
  315. REPLY_STATUS_REPLY_IN_PROGRESS_MASK)) {
  316. return 0;
  317. }
  318. timeout--;
  319. udelay(20);
  320. }
  321. return -ETIMEDOUT;
  322. }
  323. /**
  324. * aux_request_send() - Send request on the AUX channel
  325. * @dev: The LogiCore DP TX device in question
  326. * @request: The request to send
  327. *
  328. * Submit the supplied AUX request to the RX device over the AUX
  329. * channel by writing the command, the destination address, (the write buffer
  330. * for write commands), and the data size to the DisplayPort TX core.
  331. *
  332. * This is the lower-level sending routine, which is called by aux_request().
  333. *
  334. * Return: 0 if request was sent successfully, -ve on error
  335. */
  336. static int aux_request_send(struct udevice *dev,
  337. struct aux_transaction *request)
  338. {
  339. u32 timeout_count;
  340. int status;
  341. u8 index;
  342. /* Ensure that any pending AUX transactions have completed. */
  343. timeout_count = 0;
  344. do {
  345. status = get_reg(dev, REG_REPLY_STATUS);
  346. udelay(20);
  347. timeout_count++;
  348. if (timeout_count >= AUX_MAX_TIMEOUT_COUNT)
  349. return -ETIMEDOUT;
  350. } while ((status & REPLY_STATUS_REQUEST_IN_PROGRESS_MASK) ||
  351. (status & REPLY_STATUS_REPLY_IN_PROGRESS_MASK));
  352. set_reg(dev, REG_AUX_ADDRESS, request->address);
  353. if (request->cmd_code == AUX_CMD_WRITE ||
  354. request->cmd_code == AUX_CMD_I2C_WRITE ||
  355. request->cmd_code == AUX_CMD_I2C_WRITE_MOT) {
  356. /* Feed write data into the DisplayPort TX core's write FIFO. */
  357. for (index = 0; index < request->num_bytes; index++) {
  358. set_reg(dev,
  359. REG_AUX_WRITE_FIFO, request->data[index]);
  360. }
  361. }
  362. /* Submit the command and the data size. */
  363. set_reg(dev, REG_AUX_CMD,
  364. ((request->cmd_code << AUX_CMD_SHIFT) |
  365. ((request->num_bytes - 1) &
  366. AUX_CMD_NBYTES_TRANSFER_MASK)));
  367. /* Check for a reply from the RX device to the submitted request. */
  368. status = aux_wait_reply(dev);
  369. if (status)
  370. /* Waiting for a reply timed out. */
  371. return -ETIMEDOUT;
  372. /* Analyze the reply. */
  373. status = get_reg(dev, REG_AUX_REPLY_CODE);
  374. if (status == AUX_REPLY_CODE_DEFER ||
  375. status == AUX_REPLY_CODE_I2C_DEFER) {
  376. /* The request was deferred. */
  377. return -EAGAIN;
  378. } else if ((status == AUX_REPLY_CODE_NACK) ||
  379. (status == AUX_REPLY_CODE_I2C_NACK)) {
  380. /* The request was not acknowledged. */
  381. return -EIO;
  382. }
  383. /* The request was acknowledged. */
  384. if (request->cmd_code == AUX_CMD_READ ||
  385. request->cmd_code == AUX_CMD_I2C_READ ||
  386. request->cmd_code == AUX_CMD_I2C_READ_MOT) {
  387. /* Wait until all data has been received. */
  388. timeout_count = 0;
  389. do {
  390. status = get_reg(dev, REG_REPLY_DATA_COUNT);
  391. udelay(100);
  392. timeout_count++;
  393. if (timeout_count >= AUX_MAX_TIMEOUT_COUNT)
  394. return -ETIMEDOUT;
  395. } while (status != request->num_bytes);
  396. /* Obtain the read data from the reply FIFO. */
  397. for (index = 0; index < request->num_bytes; index++)
  398. request->data[index] = get_reg(dev, REG_AUX_REPLY_DATA);
  399. }
  400. return 0;
  401. }
  402. /**
  403. * aux_request() - Submit request on the AUX channel
  404. * @dev: The LogiCore DP TX device in question
  405. * @request: The request to submit
  406. *
  407. * Submit the supplied AUX request to the RX device over the AUX
  408. * channel. If waiting for a reply times out, or if the DisplayPort TX core
  409. * indicates that the request was deferred, the request is sent again (up to a
  410. * maximum specified by AUX_MAX_DEFER_COUNT|AUX_MAX_TIMEOUT_COUNT).
  411. *
  412. * Return: 0 if request was submitted successfully, -ve on error
  413. */
  414. static int aux_request(struct udevice *dev, struct aux_transaction *request)
  415. {
  416. u32 defer_count = 0;
  417. u32 timeout_count = 0;
  418. while ((defer_count < AUX_MAX_DEFER_COUNT) &&
  419. (timeout_count < AUX_MAX_TIMEOUT_COUNT)) {
  420. int status = aux_wait_ready(dev);
  421. if (status) {
  422. /* The RX device isn't ready yet. */
  423. timeout_count++;
  424. continue;
  425. }
  426. status = aux_request_send(dev, request);
  427. if (status == -EAGAIN) {
  428. /* The request was deferred. */
  429. defer_count++;
  430. } else if (status == -ETIMEDOUT) {
  431. /* Waiting for a reply timed out. */
  432. timeout_count++;
  433. } else {
  434. /*
  435. * -EIO indicates that the request was NACK'ed,
  436. * 0 indicates that the request was ACK'ed.
  437. */
  438. return status;
  439. }
  440. udelay(100);
  441. }
  442. /* The request was not successfully received by the RX device. */
  443. return -ETIMEDOUT;
  444. }
  445. /**
  446. * aux_common() - Common (read/write) AUX communication transmission
  447. * @dev: The LogiCore DP TX device in question
  448. * @cmd_type: Command code of the transaction
  449. * @address: The DPCD address of the transaction
  450. * @num_bytes: Number of bytes in the payload data
  451. * @data: The payload data of the AUX command
  452. *
  453. * Common sequence of submitting an AUX command for AUX read, AUX write,
  454. * I2C-over-AUX read, and I2C-over-AUX write transactions. If required, the
  455. * reads and writes are split into multiple requests, each acting on a maximum
  456. * of 16 bytes.
  457. *
  458. * Return: 0 if OK, -ve on error
  459. */
  460. static int aux_common(struct udevice *dev, u32 cmd_type, u32 address,
  461. u32 num_bytes, u8 *data)
  462. {
  463. struct aux_transaction request;
  464. u32 bytes_left;
  465. /*
  466. * Set the start address for AUX transactions. For I2C transactions,
  467. * this is the address of the I2C bus.
  468. */
  469. request.address = address;
  470. bytes_left = num_bytes;
  471. while (bytes_left) {
  472. int status;
  473. request.cmd_code = cmd_type;
  474. if (cmd_type == AUX_CMD_READ ||
  475. cmd_type == AUX_CMD_WRITE) {
  476. /* Increment address for normal AUX transactions. */
  477. request.address = address + (num_bytes - bytes_left);
  478. }
  479. /* Increment the pointer to the supplied data buffer. */
  480. request.data = &data[num_bytes - bytes_left];
  481. request.num_bytes = (bytes_left > 16) ? 16 : bytes_left;
  482. bytes_left -= request.num_bytes;
  483. if (cmd_type == AUX_CMD_I2C_READ && bytes_left) {
  484. /*
  485. * Middle of a transaction I2C read request. Override
  486. * the command code that was set to cmd_type.
  487. */
  488. request.cmd_code = AUX_CMD_I2C_READ_MOT;
  489. } else if ((cmd_type == AUX_CMD_I2C_WRITE) && bytes_left) {
  490. /*
  491. * Middle of a transaction I2C write request. Override
  492. * the command code that was set to cmd_type.
  493. */
  494. request.cmd_code = AUX_CMD_I2C_WRITE_MOT;
  495. }
  496. status = aux_request(dev, &request);
  497. if (status)
  498. return status;
  499. }
  500. return 0;
  501. }
  502. /**
  503. * aux_read() - Issue AUX read request
  504. * @dev: The LogiCore DP TX device in question
  505. * @dpcd_address: The DPCD address to read from
  506. * @bytes_to_read: Number of bytes to read
  507. * @read_data: Buffer to receive the read data
  508. *
  509. * Issue a read request over the AUX channel that will read from the RX
  510. * device's DisplayPort Configuration data (DPCD) address space. The read
  511. * message will be divided into multiple transactions which read a maximum of
  512. * 16 bytes each.
  513. *
  514. * Return: 0 if read operation was successful, -ve on error
  515. */
  516. static int aux_read(struct udevice *dev, u32 dpcd_address, u32 bytes_to_read,
  517. void *read_data)
  518. {
  519. int status;
  520. if (!is_connected(dev))
  521. return -ENODEV;
  522. /* Send AUX read transaction. */
  523. status = aux_common(dev, AUX_CMD_READ, dpcd_address,
  524. bytes_to_read, (u8 *)read_data);
  525. return status;
  526. }
  527. /**
  528. * aux_write() - Issue AUX write request
  529. * @dev: The LogiCore DP TX device in question
  530. * @dpcd_address: The DPCD address to write to
  531. * @bytes_to_write: Number of bytes to write
  532. * @write_data: Buffer containig data to be written
  533. *
  534. * Issue a write request over the AUX channel that will write to
  535. * the RX device's DisplayPort Configuration data (DPCD) address space. The
  536. * write message will be divided into multiple transactions which write a
  537. * maximum of 16 bytes each.
  538. *
  539. * Return: 0 if write operation was successful, -ve on error
  540. */
  541. static int aux_write(struct udevice *dev, u32 dpcd_address, u32 bytes_to_write,
  542. void *write_data)
  543. {
  544. int status;
  545. if (!is_connected(dev))
  546. return -ENODEV;
  547. /* Send AUX write transaction. */
  548. status = aux_common(dev, AUX_CMD_WRITE, dpcd_address,
  549. bytes_to_write, (u8 *)write_data);
  550. return status;
  551. }
  552. /* Core initialization */
  553. /**
  554. * initialize() - Initialize a LogiCore DP TX device
  555. * @dev: The LogiCore DP TX device in question
  556. *
  557. * Return: Always 0
  558. */
  559. static int initialize(struct udevice *dev)
  560. {
  561. struct dp_tx *dp_tx = dev_get_priv(dev);
  562. u32 val;
  563. u32 phy_config;
  564. unsigned int k;
  565. /* place the PHY (and GTTXRESET) into reset. */
  566. phy_config = get_reg(dev, REG_PHY_CONFIG);
  567. set_reg(dev, REG_PHY_CONFIG, phy_config | PHY_CONFIG_GT_ALL_RESET_MASK);
  568. /* reset the video streams and AUX logic. */
  569. set_reg(dev, REG_SOFT_RESET,
  570. SOFT_RESET_VIDEO_STREAM_ALL_MASK |
  571. SOFT_RESET_AUX_MASK);
  572. /* disable the DisplayPort TX core. */
  573. set_reg(dev, REG_ENABLE, 0);
  574. /* set the clock divider. */
  575. val = get_reg(dev, REG_AUX_CLK_DIVIDER);
  576. val &= ~AUX_CLK_DIVIDER_VAL_MASK;
  577. val |= dp_tx->s_axi_clk / 1000000;
  578. set_reg(dev, REG_AUX_CLK_DIVIDER, val);
  579. /* set the DisplayPort TX core's clock speed. */
  580. set_reg(dev, REG_PHY_CLOCK_SELECT, PHY_CLOCK_SELECT_DEFAULT);
  581. /* bring the PHY (and GTTXRESET) out of reset. */
  582. set_reg(dev, REG_PHY_CONFIG,
  583. phy_config & ~PHY_CONFIG_GT_ALL_RESET_MASK);
  584. /* enable the DisplayPort TX core. */
  585. set_reg(dev, REG_ENABLE, 1);
  586. /* Unmask Hot-Plug-Detect (HPD) interrupts. */
  587. set_reg(dev, REG_INTERRUPT_MASK,
  588. ~INTERRUPT_MASK_HPD_PULSE_DETECTED_MASK &
  589. ~INTERRUPT_MASK_HPD_EVENT_MASK &
  590. ~INTERRUPT_MASK_HPD_IRQ_MASK);
  591. for (k = 0; k < 4; k++) {
  592. /* Disable pre-cursor levels. */
  593. set_reg(dev, REG_PHY_PRECURSOR_LANE_0 + 4 * k, 0);
  594. /* Write default voltage swing levels to the TX registers. */
  595. set_reg(dev, REG_PHY_VOLTAGE_DIFF_LANE_0 + 4 * k, 0);
  596. /* Write default pre-emphasis levels to the TX registers. */
  597. set_reg(dev, REG_PHY_POSTCURSOR_LANE_0 + 4 * k, 0);
  598. }
  599. return 0;
  600. }
  601. /**
  602. * is_link_rate_valid() - Check if given link rate is valif for device
  603. * @dev: The LogiCore DP TX device in question
  604. * @link_rate: The link rate to be checked for validity
  605. *
  606. * Return: true if he supplied link rate is valid, false otherwise
  607. */
  608. static bool is_link_rate_valid(struct udevice *dev, u8 link_rate)
  609. {
  610. struct dp_tx *dp_tx = dev_get_priv(dev);
  611. bool valid = true;
  612. if (link_rate != LINK_BW_SET_162GBPS &&
  613. link_rate != LINK_BW_SET_270GBPS &&
  614. link_rate != LINK_BW_SET_540GBPS)
  615. valid = false;
  616. else if (link_rate > dp_tx->link_config.max_link_rate)
  617. valid = false;
  618. return valid;
  619. }
  620. /**
  621. * is_lane_count_valid() - Check if given lane count is valif for device
  622. * @dev: The LogiCore DP TX device in question
  623. * @lane_count: The lane count to be checked for validity
  624. *
  625. * Return: true if he supplied lane count is valid, false otherwise
  626. */
  627. static bool is_lane_count_valid(struct udevice *dev, u8 lane_count)
  628. {
  629. struct dp_tx *dp_tx = dev_get_priv(dev);
  630. bool valid = true;
  631. if (lane_count != LANE_COUNT_SET_1 &&
  632. lane_count != LANE_COUNT_SET_2 &&
  633. lane_count != LANE_COUNT_SET_4)
  634. valid = false;
  635. else if (lane_count > dp_tx->link_config.max_lane_count)
  636. valid = false;
  637. return valid;
  638. }
  639. /**
  640. * get_rx_capabilities() - Check if capabilities of RX device are valid for TX
  641. * device
  642. * @dev: The LogiCore DP TX device in question
  643. *
  644. * Return: 0 if the capabilities of the RX device are valid for the TX device,
  645. * -ve if not, of an error occurred during capability determination
  646. */
  647. static int get_rx_capabilities(struct udevice *dev)
  648. {
  649. struct dp_tx *dp_tx = dev_get_priv(dev);
  650. int status;
  651. u8 rx_max_link_rate;
  652. u8 rx_max_lane_count;
  653. if (!is_connected(dev))
  654. return -ENODEV;
  655. status = aux_read(dev, DPCD_RECEIVER_CAP_FIELD_START, 16,
  656. dp_tx->dpcd_rx_caps);
  657. if (status)
  658. return -EIO;
  659. rx_max_link_rate = dp_tx->dpcd_rx_caps[DPCD_MAX_LINK_RATE];
  660. rx_max_lane_count = dp_tx->dpcd_rx_caps[DPCD_MAX_LANE_COUNT] &
  661. DPCD_MAX_LANE_COUNT_MASK;
  662. dp_tx->link_config.max_link_rate =
  663. (rx_max_link_rate > dp_tx->max_link_rate) ?
  664. dp_tx->max_link_rate : rx_max_link_rate;
  665. if (!is_link_rate_valid(dev, rx_max_link_rate))
  666. return -EINVAL;
  667. dp_tx->link_config.max_lane_count =
  668. (rx_max_lane_count > dp_tx->max_lane_count) ?
  669. dp_tx->max_lane_count : rx_max_lane_count;
  670. if (!is_lane_count_valid(dev, rx_max_lane_count))
  671. return -EINVAL;
  672. dp_tx->link_config.support_enhanced_framing_mode =
  673. dp_tx->dpcd_rx_caps[DPCD_MAX_LANE_COUNT] &
  674. DPCD_ENHANCED_FRAME_SUPPORT_MASK;
  675. return 0;
  676. }
  677. /**
  678. * enable_main_link() - Switch on main link for a device
  679. * @dev: The LogiCore DP TX device in question
  680. */
  681. static void enable_main_link(struct udevice *dev)
  682. {
  683. /* reset the scrambler. */
  684. set_reg(dev, REG_FORCE_SCRAMBLER_RESET, 0x1);
  685. /* enable the main stream. */
  686. set_reg(dev, REG_ENABLE_MAIN_STREAM, 0x1);
  687. }
  688. /**
  689. * disable_main_link() - Switch off main link for a device
  690. * @dev: The LogiCore DP TX device in question
  691. */
  692. static void disable_main_link(struct udevice *dev)
  693. {
  694. /* reset the scrambler. */
  695. set_reg(dev, REG_FORCE_SCRAMBLER_RESET, 0x1);
  696. /* Disable the main stream. */
  697. set_reg(dev, REG_ENABLE_MAIN_STREAM, 0x0);
  698. }
  699. /**
  700. * reset_dp_phy() - Reset a device
  701. * @dev: The LogiCore DP TX device in question
  702. * @reset: Bit mask determining which bits in the device's config register
  703. * should be set for the reset
  704. */
  705. static void reset_dp_phy(struct udevice *dev, u32 reset)
  706. {
  707. struct dp_tx *dp_tx = dev_get_priv(dev);
  708. u32 val;
  709. set_reg(dev, REG_ENABLE, 0x0);
  710. val = get_reg(dev, REG_PHY_CONFIG);
  711. /* Apply reset. */
  712. set_reg(dev, REG_PHY_CONFIG, val | reset);
  713. /* Remove reset. */
  714. set_reg(dev, REG_PHY_CONFIG, val);
  715. /* Wait for the PHY to be ready. */
  716. wait_phy_ready(dev, phy_status_lanes_ready_mask(dp_tx->max_lane_count));
  717. set_reg(dev, REG_ENABLE, 0x1);
  718. }
  719. /**
  720. * set_enhanced_frame_mode() - Enable/Disable enhanced frame mode
  721. * @dev: The LogiCore DP TX device in question
  722. * @enable: Flag to determine whether to enable (1) or disable (0) the enhanced
  723. * frame mode
  724. *
  725. * Enable or disable the enhanced framing symbol sequence for
  726. * both the DisplayPort TX core and the RX device.
  727. *
  728. * Return: 0 if enabling/disabling the enhanced frame mode was successful, -ve
  729. * on error
  730. */
  731. static int set_enhanced_frame_mode(struct udevice *dev, u8 enable)
  732. {
  733. struct dp_tx *dp_tx = dev_get_priv(dev);
  734. int status;
  735. u8 val;
  736. if (!is_connected(dev))
  737. return -ENODEV;
  738. if (dp_tx->link_config.support_enhanced_framing_mode)
  739. dp_tx->link_config.enhanced_framing_mode = enable;
  740. else
  741. dp_tx->link_config.enhanced_framing_mode = false;
  742. /* Write enhanced frame mode enable to the DisplayPort TX core. */
  743. set_reg(dev, REG_ENHANCED_FRAME_EN,
  744. dp_tx->link_config.enhanced_framing_mode);
  745. /* Write enhanced frame mode enable to the RX device. */
  746. status = aux_read(dev, DPCD_LANE_COUNT_SET, 0x1, &val);
  747. if (status)
  748. return -EIO;
  749. if (dp_tx->link_config.enhanced_framing_mode)
  750. val |= DPCD_ENHANCED_FRAME_EN_MASK;
  751. else
  752. val &= ~DPCD_ENHANCED_FRAME_EN_MASK;
  753. status = aux_write(dev, DPCD_LANE_COUNT_SET, 0x1, &val);
  754. if (status)
  755. return -EIO;
  756. return 0;
  757. }
  758. /**
  759. * set_lane_count() - Set the lane count
  760. * @dev: The LogiCore DP TX device in question
  761. * @lane_count: Lane count to set
  762. *
  763. * Set the number of lanes to be used by the main link for both
  764. * the DisplayPort TX core and the RX device.
  765. *
  766. * Return: 0 if setting the lane count was successful, -ve on error
  767. */
  768. static int set_lane_count(struct udevice *dev, u8 lane_count)
  769. {
  770. struct dp_tx *dp_tx = dev_get_priv(dev);
  771. int status;
  772. u8 val;
  773. if (!is_connected(dev))
  774. return -ENODEV;
  775. printf(" set lane count to %u\n", lane_count);
  776. dp_tx->link_config.lane_count = lane_count;
  777. /* Write the new lane count to the DisplayPort TX core. */
  778. set_reg(dev, REG_LANE_COUNT_SET, dp_tx->link_config.lane_count);
  779. /* Write the new lane count to the RX device. */
  780. status = aux_read(dev, DPCD_LANE_COUNT_SET, 0x1, &val);
  781. if (status)
  782. return -EIO;
  783. val &= ~DPCD_LANE_COUNT_SET_MASK;
  784. val |= dp_tx->link_config.lane_count;
  785. status = aux_write(dev, DPCD_LANE_COUNT_SET, 0x1, &val);
  786. if (status)
  787. return -EIO;
  788. return 0;
  789. }
  790. /**
  791. * set_clk_speed() - Set DP phy clock speed
  792. * @dev: The LogiCore DP TX device in question
  793. * @speed: The clock frquency to set (one of PHY_CLOCK_SELECT_*)
  794. *
  795. * Set the clock frequency for the DisplayPort PHY corresponding to a desired
  796. * data rate.
  797. *
  798. * Return: 0 if setting the DP phy clock speed was successful, -ve on error
  799. */
  800. static int set_clk_speed(struct udevice *dev, u32 speed)
  801. {
  802. struct dp_tx *dp_tx = dev_get_priv(dev);
  803. int status;
  804. u32 val;
  805. u32 mask;
  806. /* Disable the DisplayPort TX core first. */
  807. val = get_reg(dev, REG_ENABLE);
  808. set_reg(dev, REG_ENABLE, 0x0);
  809. /* Change speed of the feedback clock. */
  810. set_reg(dev, REG_PHY_CLOCK_SELECT, speed);
  811. /* Re-enable the DisplayPort TX core if it was previously enabled. */
  812. if (val)
  813. set_reg(dev, REG_ENABLE, 0x1);
  814. /* Wait until the PHY is ready. */
  815. mask = phy_status_lanes_ready_mask(dp_tx->max_lane_count);
  816. status = wait_phy_ready(dev, mask);
  817. if (status)
  818. return -EIO;
  819. return 0;
  820. }
  821. /**
  822. * set_link_rate() - Set the link rate
  823. * @dev: The LogiCore DP TX device in question
  824. * @link_rate: The link rate to set (one of LINK_BW_SET_*)
  825. *
  826. * Set the data rate to be used by the main link for both the DisplayPort TX
  827. * core and the RX device.
  828. *
  829. * Return: 0 if setting the link rate was successful, -ve on error
  830. */
  831. static int set_link_rate(struct udevice *dev, u8 link_rate)
  832. {
  833. struct dp_tx *dp_tx = dev_get_priv(dev);
  834. int status;
  835. /* Write a corresponding clock frequency to the DisplayPort TX core. */
  836. switch (link_rate) {
  837. case LINK_BW_SET_162GBPS:
  838. printf(" set link rate to 1.62 Gb/s\n");
  839. status = set_clk_speed(dev, PHY_CLOCK_SELECT_162GBPS);
  840. break;
  841. case LINK_BW_SET_270GBPS:
  842. printf(" set link rate to 2.70 Gb/s\n");
  843. status = set_clk_speed(dev, PHY_CLOCK_SELECT_270GBPS);
  844. break;
  845. case LINK_BW_SET_540GBPS:
  846. printf(" set link rate to 5.40 Gb/s\n");
  847. status = set_clk_speed(dev, PHY_CLOCK_SELECT_540GBPS);
  848. break;
  849. default:
  850. return -EINVAL;
  851. }
  852. if (status)
  853. return -EIO;
  854. dp_tx->link_config.link_rate = link_rate;
  855. /* Write new link rate to the DisplayPort TX core. */
  856. set_reg(dev, REG_LINK_BW_SET, dp_tx->link_config.link_rate);
  857. /* Write new link rate to the RX device. */
  858. status = aux_write(dev, DPCD_LINK_BW_SET, 1,
  859. &dp_tx->link_config.link_rate);
  860. if (status)
  861. return -EIO;
  862. return 0;
  863. }
  864. /* Link training */
  865. /**
  866. * get_training_delay() - Get training delay
  867. * @dev: The LogiCore DP TX device in question
  868. * @training_state: The training state for which the required training delay
  869. * should be queried
  870. *
  871. * Determine what the RX device's required training delay is for
  872. * link training.
  873. *
  874. * Return: The training delay in us
  875. */
  876. static int get_training_delay(struct udevice *dev, int training_state)
  877. {
  878. struct dp_tx *dp_tx = dev_get_priv(dev);
  879. u16 delay;
  880. switch (dp_tx->dpcd_rx_caps[DPCD_TRAIN_AUX_RD_INTERVAL]) {
  881. case DPCD_TRAIN_AUX_RD_INT_100_400US:
  882. if (training_state == TS_CLOCK_RECOVERY)
  883. /* delay for the clock recovery phase. */
  884. delay = 100;
  885. else
  886. /* delay for the channel equalization phase. */
  887. delay = 400;
  888. break;
  889. case DPCD_TRAIN_AUX_RD_INT_4MS:
  890. delay = 4000;
  891. break;
  892. case DPCD_TRAIN_AUX_RD_INT_8MS:
  893. delay = 8000;
  894. break;
  895. case DPCD_TRAIN_AUX_RD_INT_12MS:
  896. delay = 12000;
  897. break;
  898. case DPCD_TRAIN_AUX_RD_INT_16MS:
  899. delay = 16000;
  900. break;
  901. default:
  902. /* Default to 20 ms. */
  903. delay = 20000;
  904. break;
  905. }
  906. return delay;
  907. }
  908. /**
  909. * set_vswing_preemp() - Build AUX data to set voltage swing and pre-emphasis
  910. * @dev: The LogiCore DP TX device in question
  911. * @aux_data: Buffer to receive the built AUX data
  912. *
  913. * Build AUX data to set current voltage swing and pre-emphasis level settings;
  914. * the necessary data is taken from the link_config structure.
  915. */
  916. static void set_vswing_preemp(struct udevice *dev, u8 *aux_data)
  917. {
  918. struct dp_tx *dp_tx = dev_get_priv(dev);
  919. u8 data;
  920. u8 vs_level_rx = dp_tx->link_config.vs_level;
  921. u8 pe_level_rx = dp_tx->link_config.pe_level;
  922. /* Set up the data buffer for writing to the RX device. */
  923. data = (pe_level_rx << DPCD_TRAINING_LANEX_SET_PE_SHIFT) | vs_level_rx;
  924. /* The maximum voltage swing has been reached. */
  925. if (vs_level_rx == MAXIMUM_VS_LEVEL)
  926. data |= DPCD_TRAINING_LANEX_SET_MAX_VS_MASK;
  927. /* The maximum pre-emphasis level has been reached. */
  928. if (pe_level_rx == MAXIMUM_PE_LEVEL)
  929. data |= DPCD_TRAINING_LANEX_SET_MAX_PE_MASK;
  930. memset(aux_data, data, 4);
  931. }
  932. /**
  933. * adj_vswing_preemp() - Adjust voltage swing and pre-emphasis
  934. * @dev: The LogiCore DP TX device in question
  935. *
  936. * Set new voltage swing and pre-emphasis levels using the
  937. * adjustment requests obtained from the RX device.
  938. *
  939. * Return: 0 if voltage swing and pre-emphasis could be adjusted successfully,
  940. * -ve on error
  941. */
  942. static int adj_vswing_preemp(struct udevice *dev)
  943. {
  944. struct dp_tx *dp_tx = dev_get_priv(dev);
  945. int status;
  946. u8 index;
  947. u8 vs_level_adj_req[4];
  948. u8 pe_level_adj_req[4];
  949. u8 aux_data[4];
  950. u8 *ajd_reqs = &dp_tx->lane_status_ajd_reqs[4];
  951. /*
  952. * Analyze the adjustment requests for changes in voltage swing and
  953. * pre-emphasis levels.
  954. */
  955. vs_level_adj_req[0] = ajd_reqs[0] & DPCD_ADJ_REQ_LANE_0_2_VS_MASK;
  956. vs_level_adj_req[1] = (ajd_reqs[0] & DPCD_ADJ_REQ_LANE_1_3_VS_MASK) >>
  957. DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT;
  958. vs_level_adj_req[2] = ajd_reqs[1] & DPCD_ADJ_REQ_LANE_0_2_VS_MASK;
  959. vs_level_adj_req[3] = (ajd_reqs[1] & DPCD_ADJ_REQ_LANE_1_3_VS_MASK) >>
  960. DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT;
  961. pe_level_adj_req[0] = (ajd_reqs[0] & DPCD_ADJ_REQ_LANE_0_2_PE_MASK) >>
  962. DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT;
  963. pe_level_adj_req[1] = (ajd_reqs[0] & DPCD_ADJ_REQ_LANE_1_3_PE_MASK) >>
  964. DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT;
  965. pe_level_adj_req[2] = (ajd_reqs[1] & DPCD_ADJ_REQ_LANE_0_2_PE_MASK) >>
  966. DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT;
  967. pe_level_adj_req[3] = (ajd_reqs[1] & DPCD_ADJ_REQ_LANE_1_3_PE_MASK) >>
  968. DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT;
  969. /*
  970. * Change the drive settings to match the adjustment requests. Use the
  971. * greatest level requested.
  972. */
  973. dp_tx->link_config.vs_level = 0;
  974. dp_tx->link_config.pe_level = 0;
  975. for (index = 0; index < dp_tx->link_config.lane_count; index++) {
  976. if (vs_level_adj_req[index] > dp_tx->link_config.vs_level)
  977. dp_tx->link_config.vs_level = vs_level_adj_req[index];
  978. if (pe_level_adj_req[index] > dp_tx->link_config.pe_level)
  979. dp_tx->link_config.pe_level = pe_level_adj_req[index];
  980. }
  981. /*
  982. * Verify that the voltage swing and pre-emphasis combination is
  983. * allowed. Some combinations will result in a differential peak-to-peak
  984. * voltage that is outside the permissible range. See the VESA
  985. * DisplayPort v1.2 Specification, section 3.1.5.2.
  986. * The valid combinations are:
  987. * PE=0 PE=1 PE=2 PE=3
  988. * VS=0 valid valid valid valid
  989. * VS=1 valid valid valid
  990. * VS=2 valid valid
  991. * VS=3 valid
  992. *
  993. * NOTE:
  994. * Xilinix dp_v3_1 driver seems to have an off by one error when
  995. * limiting pe_level which is fixed here.
  996. */
  997. if (dp_tx->link_config.pe_level > (3 - dp_tx->link_config.vs_level))
  998. dp_tx->link_config.pe_level = 3 - dp_tx->link_config.vs_level;
  999. /*
  1000. * Make the adjustments to both the DisplayPort TX core and the RX
  1001. * device.
  1002. */
  1003. set_vswing_preemp(dev, aux_data);
  1004. /*
  1005. * Write the voltage swing and pre-emphasis levels for each lane to the
  1006. * RX device.
  1007. */
  1008. status = aux_write(dev, DPCD_TRAINING_LANE0_SET, 4, aux_data);
  1009. if (status)
  1010. return -EIO;
  1011. return 0;
  1012. }
  1013. /**
  1014. * get_lane_status_adj_reqs() - Read lane status and adjustment requests
  1015. * information from the device
  1016. * @dev: The LogiCore DP TX device in question
  1017. *
  1018. * Do a burst AUX read from the RX device over the AUX channel. The contents of
  1019. * the status registers will be stored for later use by check_clock_recovery,
  1020. * check_channel_equalization, and adj_vswing_preemp.
  1021. *
  1022. * Return: 0 if the status information were read successfully, -ve on error
  1023. */
  1024. static int get_lane_status_adj_reqs(struct udevice *dev)
  1025. {
  1026. struct dp_tx *dp_tx = dev_get_priv(dev);
  1027. int status;
  1028. /*
  1029. * Read and store 4 bytes of lane status and 2 bytes of adjustment
  1030. * requests.
  1031. */
  1032. status = aux_read(dev, DPCD_STATUS_LANE_0_1, 6,
  1033. dp_tx->lane_status_ajd_reqs);
  1034. if (status)
  1035. return -EIO;
  1036. return 0;
  1037. }
  1038. /**
  1039. * check_clock_recovery() - Check clock recovery success
  1040. * @dev: The LogiCore DP TX device in question
  1041. * @lane_count: The number of lanes for which to check clock recovery success
  1042. *
  1043. * Check if the RX device's DisplayPort Configuration data (DPCD) indicates
  1044. * that the clock recovery sequence during link training was successful - the
  1045. * RX device's link clock and data recovery unit has realized and maintained
  1046. * the frequency lock for all lanes currently in use.
  1047. *
  1048. * Return: 0 if clock recovery was successful on all lanes in question, -ve if
  1049. * not
  1050. */
  1051. static int check_clock_recovery(struct udevice *dev, u8 lane_count)
  1052. {
  1053. struct dp_tx *dp_tx = dev_get_priv(dev);
  1054. u8 *lane_status = dp_tx->lane_status_ajd_reqs;
  1055. /* Check that all LANEx_CR_DONE bits are set. */
  1056. switch (lane_count) {
  1057. case LANE_COUNT_SET_4:
  1058. if (!(lane_status[1] & DPCD_STATUS_LANE_3_CR_DONE_MASK))
  1059. goto out_fail;
  1060. if (!(lane_status[1] & DPCD_STATUS_LANE_2_CR_DONE_MASK))
  1061. goto out_fail;
  1062. /* Drop through and check lane 1. */
  1063. case LANE_COUNT_SET_2:
  1064. if (!(lane_status[0] & DPCD_STATUS_LANE_1_CR_DONE_MASK))
  1065. goto out_fail;
  1066. /* Drop through and check lane 0. */
  1067. case LANE_COUNT_SET_1:
  1068. if (!(lane_status[0] & DPCD_STATUS_LANE_0_CR_DONE_MASK))
  1069. goto out_fail;
  1070. default:
  1071. /* All (lane_count) lanes have achieved clock recovery. */
  1072. break;
  1073. }
  1074. return 0;
  1075. out_fail:
  1076. return -EIO;
  1077. }
  1078. /**
  1079. * check_channel_equalization() - Check channel equalization success
  1080. * @dev: The LogiCore DP TX device in question
  1081. * @lane_count: The number of lanes for which to check channel equalization
  1082. * success
  1083. *
  1084. * Check if the RX device's DisplayPort Configuration data (DPCD) indicates
  1085. * that the channel equalization sequence during link training was successful -
  1086. * the RX device has achieved channel equalization, symbol lock, and interlane
  1087. * alignment for all lanes currently in use.
  1088. *
  1089. * Return: 0 if channel equalization was successful on all lanes in question,
  1090. * -ve if not
  1091. */
  1092. static int check_channel_equalization(struct udevice *dev, u8 lane_count)
  1093. {
  1094. struct dp_tx *dp_tx = dev_get_priv(dev);
  1095. u8 *lane_status = dp_tx->lane_status_ajd_reqs;
  1096. /* Check that all LANEx_CHANNEL_EQ_DONE bits are set. */
  1097. switch (lane_count) {
  1098. case LANE_COUNT_SET_4:
  1099. if (!(lane_status[1] & DPCD_STATUS_LANE_3_CE_DONE_MASK))
  1100. goto out_fail;
  1101. if (!(lane_status[1] & DPCD_STATUS_LANE_2_CE_DONE_MASK))
  1102. goto out_fail;
  1103. /* Drop through and check lane 1. */
  1104. case LANE_COUNT_SET_2:
  1105. if (!(lane_status[0] & DPCD_STATUS_LANE_1_CE_DONE_MASK))
  1106. goto out_fail;
  1107. /* Drop through and check lane 0. */
  1108. case LANE_COUNT_SET_1:
  1109. if (!(lane_status[0] & DPCD_STATUS_LANE_0_CE_DONE_MASK))
  1110. goto out_fail;
  1111. default:
  1112. /* All (lane_count) lanes have achieved channel equalization. */
  1113. break;
  1114. }
  1115. /* Check that all LANEx_SYMBOL_LOCKED bits are set. */
  1116. switch (lane_count) {
  1117. case LANE_COUNT_SET_4:
  1118. if (!(lane_status[1] & DPCD_STATUS_LANE_3_SL_DONE_MASK))
  1119. goto out_fail;
  1120. if (!(lane_status[1] & DPCD_STATUS_LANE_2_SL_DONE_MASK))
  1121. goto out_fail;
  1122. /* Drop through and check lane 1. */
  1123. case LANE_COUNT_SET_2:
  1124. if (!(lane_status[0] & DPCD_STATUS_LANE_1_SL_DONE_MASK))
  1125. goto out_fail;
  1126. /* Drop through and check lane 0. */
  1127. case LANE_COUNT_SET_1:
  1128. if (!(lane_status[0] & DPCD_STATUS_LANE_0_SL_DONE_MASK))
  1129. goto out_fail;
  1130. default:
  1131. /* All (lane_count) lanes have achieved symbol lock. */
  1132. break;
  1133. }
  1134. /* Check that interlane alignment is done. */
  1135. if (!(lane_status[2] & DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK))
  1136. goto out_fail;
  1137. return 0;
  1138. out_fail:
  1139. return -EIO;
  1140. }
  1141. /**
  1142. * set_training_pattern() - Set training pattern for link training
  1143. * @dev: The LogiCore DP TX device in question
  1144. * @pattern: The training pattern to set
  1145. *
  1146. * Set the training pattern to be used during link training for both the
  1147. * DisplayPort TX core and the RX device.
  1148. *
  1149. * Return: 0 if the training pattern could be set successfully, -ve if not
  1150. */
  1151. static int set_training_pattern(struct udevice *dev, u32 pattern)
  1152. {
  1153. struct dp_tx *dp_tx = dev_get_priv(dev);
  1154. int status;
  1155. u8 aux_data[5];
  1156. /* Write to the DisplayPort TX core. */
  1157. set_reg(dev, REG_TRAINING_PATTERN_SET, pattern);
  1158. aux_data[0] = pattern;
  1159. /* Write scrambler disable to the DisplayPort TX core. */
  1160. switch (pattern) {
  1161. case TRAINING_PATTERN_SET_OFF:
  1162. set_reg(dev, REG_SCRAMBLING_DISABLE, 0);
  1163. dp_tx->link_config.scrambler_en = 1;
  1164. break;
  1165. case TRAINING_PATTERN_SET_TP1:
  1166. case TRAINING_PATTERN_SET_TP2:
  1167. case TRAINING_PATTERN_SET_TP3:
  1168. aux_data[0] |= DPCD_TP_SET_SCRAMB_DIS_MASK;
  1169. set_reg(dev, REG_SCRAMBLING_DISABLE, 1);
  1170. dp_tx->link_config.scrambler_en = 0;
  1171. break;
  1172. default:
  1173. break;
  1174. }
  1175. /*
  1176. * Make the adjustments to both the DisplayPort TX core and the RX
  1177. * device.
  1178. */
  1179. set_vswing_preemp(dev, &aux_data[1]);
  1180. /*
  1181. * Write the voltage swing and pre-emphasis levels for each lane to the
  1182. * RX device.
  1183. */
  1184. if (pattern == TRAINING_PATTERN_SET_OFF)
  1185. status = aux_write(dev, DPCD_TP_SET, 1, aux_data);
  1186. else
  1187. status = aux_write(dev, DPCD_TP_SET, 5, aux_data);
  1188. if (status)
  1189. return -EIO;
  1190. return 0;
  1191. }
  1192. /**
  1193. * training_state_clock_recovery() - Run clock recovery part of link training
  1194. * @dev: The LogiCore DP TX device in question
  1195. *
  1196. * Run the clock recovery sequence as part of link training. The
  1197. * sequence is as follows:
  1198. *
  1199. * 0) Start signaling at the minimum voltage swing, pre-emphasis, and
  1200. * post- cursor levels.
  1201. * 1) Transmit training pattern 1 over the main link with symbol
  1202. * scrambling disabled.
  1203. * 2) The clock recovery loop. If clock recovery is unsuccessful after
  1204. * MaxIterations loop iterations, return.
  1205. * 2a) Wait for at least the period of time specified in the RX device's
  1206. * DisplayPort Configuration data (DPCD) register,
  1207. * TRAINING_AUX_RD_INTERVAL.
  1208. * 2b) Check if all lanes have achieved clock recovery lock. If so,
  1209. * return.
  1210. * 2c) Check if the same voltage swing level has been used 5 consecutive
  1211. * times or if the maximum level has been reached. If so, return.
  1212. * 2d) Adjust the voltage swing, pre-emphasis, and post-cursor levels as
  1213. * requested by the RX device.
  1214. * 2e) Loop back to 2a.
  1215. *
  1216. * For a more detailed description of the clock recovery sequence, see section
  1217. * 3.5.1.2.1 of the DisplayPort 1.2a specification document.
  1218. *
  1219. * Return: The next state machine state to advance to
  1220. */
  1221. static unsigned int training_state_clock_recovery(struct udevice *dev)
  1222. {
  1223. struct dp_tx *dp_tx = dev_get_priv(dev);
  1224. int status;
  1225. u32 delay_us;
  1226. u8 prev_vs_level = 0;
  1227. u8 same_vs_level_count = 0;
  1228. /*
  1229. * Obtain the required delay for clock recovery as specified by the
  1230. * RX device.
  1231. */
  1232. delay_us = get_training_delay(dev, TS_CLOCK_RECOVERY);
  1233. /* Start CRLock. */
  1234. /* Transmit training pattern 1. */
  1235. /* Disable the scrambler. */
  1236. /* Start from minimal voltage swing and pre-emphasis levels. */
  1237. dp_tx->link_config.vs_level = 0;
  1238. dp_tx->link_config.pe_level = 0;
  1239. status = set_training_pattern(dev, TRAINING_PATTERN_SET_TP1);
  1240. if (status)
  1241. return TS_FAILURE;
  1242. while (1) {
  1243. /* Wait delay specified in TRAINING_AUX_RD_INTERVAL. */
  1244. udelay(delay_us);
  1245. /* Get lane and adjustment requests. */
  1246. status = get_lane_status_adj_reqs(dev);
  1247. if (status)
  1248. return TS_FAILURE;
  1249. /*
  1250. * Check if all lanes have realized and maintained the frequency
  1251. * lock and get adjustment requests.
  1252. */
  1253. status = check_clock_recovery(dev,
  1254. dp_tx->link_config.lane_count);
  1255. if (!status)
  1256. return TS_CHANNEL_EQUALIZATION;
  1257. /*
  1258. * Check if the same voltage swing for each lane has been used 5
  1259. * consecutive times.
  1260. */
  1261. if (prev_vs_level == dp_tx->link_config.vs_level) {
  1262. same_vs_level_count++;
  1263. } else {
  1264. same_vs_level_count = 0;
  1265. prev_vs_level = dp_tx->link_config.vs_level;
  1266. }
  1267. if (same_vs_level_count >= 5)
  1268. break;
  1269. /* Only try maximum voltage swing once. */
  1270. if (dp_tx->link_config.vs_level == MAXIMUM_VS_LEVEL)
  1271. break;
  1272. /* Adjust the drive settings as requested by the RX device. */
  1273. status = adj_vswing_preemp(dev);
  1274. if (status)
  1275. /* The AUX write failed. */
  1276. return TS_FAILURE;
  1277. }
  1278. return TS_ADJUST_LINK_RATE;
  1279. }
  1280. /**
  1281. * training_state_channel_equalization() - Run channel equalization part of
  1282. * link training
  1283. * @dev: The LogiCore DP TX device in question
  1284. *
  1285. * Run the channel equalization sequence as part of link
  1286. * training. The sequence is as follows:
  1287. *
  1288. * 0) Start signaling with the same drive settings used at the end of the
  1289. * clock recovery sequence.
  1290. * 1) Transmit training pattern 2 (or 3) over the main link with symbol
  1291. * scrambling disabled.
  1292. * 2) The channel equalization loop. If channel equalization is
  1293. * unsuccessful after 5 loop iterations, return.
  1294. * 2a) Wait for at least the period of time specified in the RX device's
  1295. * DisplayPort Configuration data (DPCD) register,
  1296. * TRAINING_AUX_RD_INTERVAL.
  1297. * 2b) Check if all lanes have achieved channel equalization, symbol lock,
  1298. * and interlane alignment. If so, return.
  1299. * 2c) Check if the same voltage swing level has been used 5 consecutive
  1300. * times or if the maximum level has been reached. If so, return.
  1301. * 2d) Adjust the voltage swing, pre-emphasis, and post-cursor levels as
  1302. * requested by the RX device.
  1303. * 2e) Loop back to 2a.
  1304. *
  1305. * For a more detailed description of the channel equalization sequence, see
  1306. * section 3.5.1.2.2 of the DisplayPort 1.2a specification document.
  1307. *
  1308. * Return: The next state machine state to advance to
  1309. */
  1310. static int training_state_channel_equalization(struct udevice *dev)
  1311. {
  1312. struct dp_tx *dp_tx = dev_get_priv(dev);
  1313. int status;
  1314. u32 delay_us;
  1315. u32 iteration_count = 0;
  1316. /*
  1317. * Obtain the required delay for channel equalization as specified by
  1318. * the RX device.
  1319. */
  1320. delay_us = get_training_delay(dev, TS_CHANNEL_EQUALIZATION);
  1321. /* Start channel equalization. */
  1322. /* Write the current drive settings. */
  1323. /* Transmit training pattern 2/3. */
  1324. if (dp_tx->dpcd_rx_caps[DPCD_MAX_LANE_COUNT] & DPCD_TPS3_SUPPORT_MASK)
  1325. status = set_training_pattern(dev, TRAINING_PATTERN_SET_TP3);
  1326. else
  1327. status = set_training_pattern(dev, TRAINING_PATTERN_SET_TP2);
  1328. if (status)
  1329. return TS_FAILURE;
  1330. while (iteration_count < 5) {
  1331. /* Wait delay specified in TRAINING_AUX_RD_INTERVAL. */
  1332. udelay(delay_us);
  1333. /* Get lane and adjustment requests. */
  1334. status = get_lane_status_adj_reqs(dev);
  1335. if (status)
  1336. /* The AUX read failed. */
  1337. return TS_FAILURE;
  1338. /* Check that all lanes still have their clocks locked. */
  1339. status = check_clock_recovery(dev,
  1340. dp_tx->link_config.lane_count);
  1341. if (status)
  1342. break;
  1343. /*
  1344. * Check if all lanes have accomplished channel equalization,
  1345. * symbol lock, and interlane alignment.
  1346. */
  1347. status =
  1348. check_channel_equalization(dev,
  1349. dp_tx->link_config.lane_count);
  1350. if (!status)
  1351. return TS_SUCCESS;
  1352. /* Adjust the drive settings as requested by the RX device. */
  1353. status = adj_vswing_preemp(dev);
  1354. if (status)
  1355. /* The AUX write failed. */
  1356. return TS_FAILURE;
  1357. iteration_count++;
  1358. }
  1359. /*
  1360. * Tried 5 times with no success. Try a reduced bitrate first, then
  1361. * reduce the number of lanes.
  1362. */
  1363. return TS_ADJUST_LINK_RATE;
  1364. }
  1365. /**
  1366. * training_state_adjust_link_rate() - Downshift data rate and/or lane count
  1367. * @dev: The LogiCore DP TX device in question
  1368. *
  1369. * This function is reached if either the clock recovery or the channel
  1370. * equalization process failed during training. As a result, the data rate will
  1371. * be downshifted, and training will be re-attempted (starting with clock
  1372. * recovery) at the reduced data rate. If the data rate is already at 1.62
  1373. * Gbps, a downshift in lane count will be attempted.
  1374. *
  1375. * Return: The next state machine state to advance to
  1376. */
  1377. static int training_state_adjust_link_rate(struct udevice *dev)
  1378. {
  1379. struct dp_tx *dp_tx = dev_get_priv(dev);
  1380. int status;
  1381. switch (dp_tx->link_config.link_rate) {
  1382. case LINK_BW_SET_540GBPS:
  1383. status = set_link_rate(dev, LINK_BW_SET_270GBPS);
  1384. if (status) {
  1385. status = TS_FAILURE;
  1386. break;
  1387. }
  1388. status = TS_CLOCK_RECOVERY;
  1389. break;
  1390. case LINK_BW_SET_270GBPS:
  1391. status = set_link_rate(dev, LINK_BW_SET_162GBPS);
  1392. if (status) {
  1393. status = TS_FAILURE;
  1394. break;
  1395. }
  1396. status = TS_CLOCK_RECOVERY;
  1397. break;
  1398. default:
  1399. /*
  1400. * Already at the lowest link rate. Try reducing the lane
  1401. * count next.
  1402. */
  1403. status = TS_ADJUST_LANE_COUNT;
  1404. break;
  1405. }
  1406. return status;
  1407. }
  1408. /**
  1409. * trainig_state_adjust_lane_count - Downshift lane count
  1410. * @dev: The LogiCore DP TX device in question
  1411. *
  1412. * This function is reached if either the clock recovery or the channel
  1413. * equalization process failed during training, and a minimal data rate of 1.62
  1414. * Gbps was being used. As a result, the number of lanes in use will be
  1415. * reduced, and training will be re-attempted (starting with clock recovery) at
  1416. * this lower lane count.
  1417. *
  1418. * Return: The next state machine state to advance to
  1419. */
  1420. static int trainig_state_adjust_lane_count(struct udevice *dev)
  1421. {
  1422. struct dp_tx *dp_tx = dev_get_priv(dev);
  1423. int status;
  1424. switch (dp_tx->link_config.lane_count) {
  1425. case LANE_COUNT_SET_4:
  1426. status = set_lane_count(dev, LANE_COUNT_SET_2);
  1427. if (status) {
  1428. status = TS_FAILURE;
  1429. break;
  1430. }
  1431. status = set_link_rate(dev, dp_tx->link_config.max_link_rate);
  1432. if (status) {
  1433. status = TS_FAILURE;
  1434. break;
  1435. }
  1436. status = TS_CLOCK_RECOVERY;
  1437. break;
  1438. case LANE_COUNT_SET_2:
  1439. status = set_lane_count(dev, LANE_COUNT_SET_1);
  1440. if (status) {
  1441. status = TS_FAILURE;
  1442. break;
  1443. }
  1444. status = set_link_rate(dev, dp_tx->link_config.max_link_rate);
  1445. if (status) {
  1446. status = TS_FAILURE;
  1447. break;
  1448. }
  1449. status = TS_CLOCK_RECOVERY;
  1450. break;
  1451. default:
  1452. /*
  1453. * Already at the lowest lane count. Training has failed at the
  1454. * lowest lane count and link rate.
  1455. */
  1456. status = TS_FAILURE;
  1457. break;
  1458. }
  1459. return status;
  1460. }
  1461. /**
  1462. * check_link_status() - Check status of link
  1463. * @dev: The LogiCore DP TX device in question
  1464. * @lane_count: The lane count to use for the check
  1465. *
  1466. * Check if the receiver's DisplayPort Configuration data (DPCD) indicates the
  1467. * receiver has achieved and maintained clock recovery, channel equalization,
  1468. * symbol lock, and interlane alignment for all lanes currently in use.
  1469. *
  1470. * Return: 0 if the link status is OK, -ve if a error occurred during checking
  1471. */
  1472. static int check_link_status(struct udevice *dev, u8 lane_count)
  1473. {
  1474. u8 retry_count = 0;
  1475. if (!is_connected(dev))
  1476. return -ENODEV;
  1477. /* Retrieve AUX info. */
  1478. do {
  1479. int status;
  1480. /* Get lane and adjustment requests. */
  1481. status = get_lane_status_adj_reqs(dev);
  1482. if (status)
  1483. return -EIO;
  1484. /* Check if the link needs training. */
  1485. if ((check_clock_recovery(dev, lane_count) == 0) &&
  1486. (check_channel_equalization(dev, lane_count) == 0))
  1487. return 0;
  1488. retry_count++;
  1489. } while (retry_count < 5); /* Retry up to 5 times. */
  1490. return -EIO;
  1491. }
  1492. /**
  1493. * run_training() - Run link training
  1494. * @dev: The LogiCore DP TX device in question
  1495. *
  1496. * Run the link training process. It is implemented as a state machine, with
  1497. * each state returning the next state. First, the clock recovery sequence will
  1498. * be run; if successful, the channel equalization sequence will run. If either
  1499. * the clock recovery or channel equalization sequence failed, the link rate or
  1500. * the number of lanes used will be reduced and training will be re-attempted.
  1501. * If training fails at the minimal data rate, 1.62 Gbps with a single lane,
  1502. * training will no longer re-attempt and fail.
  1503. *
  1504. * ### Here be dragons ###
  1505. * There are undocumented timeout constraints in the link training process. In
  1506. * DP v1.2a spec, Chapter 3.5.1.2.2 a 10ms limit for the complete training
  1507. * process is mentioned. Which individual timeouts are derived and implemented
  1508. * by sink manufacturers is unknown. So each step should be as short as
  1509. * possible and link training should start as soon as possible after HPD.
  1510. *
  1511. * Return: 0 if the training sequence ran successfully, -ve if a error occurred
  1512. * or the training failed
  1513. */
  1514. static int run_training(struct udevice *dev)
  1515. {
  1516. struct dp_tx *dp_tx = dev_get_priv(dev);
  1517. int status;
  1518. int training_state = TS_CLOCK_RECOVERY;
  1519. while (1) {
  1520. switch (training_state) {
  1521. case TS_CLOCK_RECOVERY:
  1522. training_state =
  1523. training_state_clock_recovery(dev);
  1524. break;
  1525. case TS_CHANNEL_EQUALIZATION:
  1526. training_state =
  1527. training_state_channel_equalization(dev);
  1528. break;
  1529. case TS_ADJUST_LINK_RATE:
  1530. training_state =
  1531. training_state_adjust_link_rate(dev);
  1532. break;
  1533. case TS_ADJUST_LANE_COUNT:
  1534. training_state =
  1535. trainig_state_adjust_lane_count(dev);
  1536. break;
  1537. default:
  1538. break;
  1539. }
  1540. if (training_state == TS_SUCCESS)
  1541. break;
  1542. else if (training_state == TS_FAILURE)
  1543. return -EIO;
  1544. if (training_state == TS_ADJUST_LINK_RATE ||
  1545. training_state == TS_ADJUST_LANE_COUNT) {
  1546. if (!dp_tx->train_adaptive)
  1547. return -EIO;
  1548. status = set_training_pattern(dev,
  1549. TRAINING_PATTERN_SET_OFF);
  1550. if (status)
  1551. return -EIO;
  1552. }
  1553. }
  1554. /* Final status check. */
  1555. status = check_link_status(dev, dp_tx->link_config.lane_count);
  1556. if (status)
  1557. return -EIO;
  1558. return 0;
  1559. }
  1560. /* Link policy maker */
  1561. /**
  1562. * cfg_main_link_max() - Determine best common capabilities
  1563. * @dev: The LogiCore DP TX device in question
  1564. *
  1565. * Determine the common capabilities between the DisplayPort TX core and the RX
  1566. * device.
  1567. *
  1568. * Return: 0 if the determination succeeded, -ve on error
  1569. */
  1570. static int cfg_main_link_max(struct udevice *dev)
  1571. {
  1572. struct dp_tx *dp_tx = dev_get_priv(dev);
  1573. int status;
  1574. if (!is_connected(dev))
  1575. return -ENODEV;
  1576. /*
  1577. * Configure the main link to the maximum common link rate between the
  1578. * DisplayPort TX core and the RX device.
  1579. */
  1580. status = set_link_rate(dev, dp_tx->link_config.max_link_rate);
  1581. if (status)
  1582. return status;
  1583. /*
  1584. * Configure the main link to the maximum common lane count between the
  1585. * DisplayPort TX core and the RX device.
  1586. */
  1587. status = set_lane_count(dev, dp_tx->link_config.max_lane_count);
  1588. if (status)
  1589. return status;
  1590. return 0;
  1591. }
  1592. /**
  1593. * establish_link() - Establish a link
  1594. * @dev: The LogiCore DP TX device in question
  1595. *
  1596. * Check if the link needs training and run the training sequence if training
  1597. * is required.
  1598. *
  1599. * Return: 0 if the link was established successfully, -ve on error
  1600. */
  1601. static int establish_link(struct udevice *dev)
  1602. {
  1603. struct dp_tx *dp_tx = dev_get_priv(dev);
  1604. int status;
  1605. int status2;
  1606. u32 mask;
  1607. reset_dp_phy(dev, PHY_CONFIG_PHY_RESET_MASK);
  1608. /* Disable main link during training. */
  1609. disable_main_link(dev);
  1610. /* Wait for the PHY to be ready. */
  1611. mask = phy_status_lanes_ready_mask(dp_tx->max_lane_count);
  1612. status = wait_phy_ready(dev, mask);
  1613. if (status)
  1614. return -EIO;
  1615. /* Train main link. */
  1616. status = run_training(dev);
  1617. /* Turn off the training pattern and enable scrambler. */
  1618. status2 = set_training_pattern(dev, TRAINING_PATTERN_SET_OFF);
  1619. if (status || status2)
  1620. return -EIO;
  1621. return 0;
  1622. }
  1623. /*
  1624. * Stream policy maker
  1625. */
  1626. /**
  1627. * cfg_msa_recalculate() - Calculate MSA parameters
  1628. * @dev: The LogiCore DP TX device in question
  1629. *
  1630. * Calculate the following Main Stream Attributes (MSA):
  1631. * - Transfer unit size
  1632. * - User pixel width
  1633. * - Horizontal total clock
  1634. * - Vertical total clock
  1635. * - misc_0
  1636. * - misc_1
  1637. * - Data per lane
  1638. * - Average number of bytes per transfer unit
  1639. * - Number of initial wait cycles
  1640. *
  1641. * These values are derived from:
  1642. * - Bits per color
  1643. * - Horizontal resolution
  1644. * - Vertical resolution
  1645. * - Horizontal blank start
  1646. * - Vertical blank start
  1647. * - Pixel clock (in KHz)
  1648. * - Horizontal sync polarity
  1649. * - Vertical sync polarity
  1650. * - Horizontal sync pulse width
  1651. * - Vertical sync pulse width
  1652. */
  1653. static void cfg_msa_recalculate(struct udevice *dev)
  1654. {
  1655. struct dp_tx *dp_tx = dev_get_priv(dev);
  1656. u32 video_bw;
  1657. u32 link_bw;
  1658. u32 words_per_line;
  1659. u8 bits_per_pixel;
  1660. struct main_stream_attributes *msa_config;
  1661. struct link_config *link_config;
  1662. msa_config = &dp_tx->main_stream_attributes;
  1663. link_config = &dp_tx->link_config;
  1664. /*
  1665. * Set the user pixel width to handle clocks that exceed the
  1666. * capabilities of the DisplayPort TX core.
  1667. */
  1668. if (msa_config->override_user_pixel_width == 0) {
  1669. if (msa_config->pixel_clock_hz > 300000000 &&
  1670. link_config->lane_count == LANE_COUNT_SET_4) {
  1671. msa_config->user_pixel_width = 4;
  1672. } /*
  1673. * Xilinx driver used 75 MHz as a limit here, 150 MHZ should
  1674. * be more sane
  1675. */
  1676. else if ((msa_config->pixel_clock_hz > 150000000) &&
  1677. (link_config->lane_count != LANE_COUNT_SET_1)) {
  1678. msa_config->user_pixel_width = 2;
  1679. } else {
  1680. msa_config->user_pixel_width = 1;
  1681. }
  1682. }
  1683. /* Compute the rest of the MSA values. */
  1684. msa_config->n_vid = 27 * 1000 * link_config->link_rate;
  1685. /* Miscellaneous attributes. */
  1686. if (msa_config->bits_per_color == 6)
  1687. msa_config->misc_0 = MAIN_STREAMX_MISC0_BDC_6BPC;
  1688. else if (msa_config->bits_per_color == 8)
  1689. msa_config->misc_0 = MAIN_STREAMX_MISC0_BDC_8BPC;
  1690. else if (msa_config->bits_per_color == 10)
  1691. msa_config->misc_0 = MAIN_STREAMX_MISC0_BDC_10BPC;
  1692. else if (msa_config->bits_per_color == 12)
  1693. msa_config->misc_0 = MAIN_STREAMX_MISC0_BDC_12BPC;
  1694. else if (msa_config->bits_per_color == 16)
  1695. msa_config->misc_0 = MAIN_STREAMX_MISC0_BDC_16BPC;
  1696. msa_config->misc_0 = (msa_config->misc_0 <<
  1697. MAIN_STREAMX_MISC0_BDC_SHIFT) |
  1698. (msa_config->y_cb_cr_colorimetry <<
  1699. MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT) |
  1700. (msa_config->dynamic_range <<
  1701. MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT) |
  1702. (msa_config->component_format <<
  1703. MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT) |
  1704. (msa_config->synchronous_clock_mode);
  1705. msa_config->misc_1 = 0;
  1706. /*
  1707. * Determine the number of bits per pixel for the specified color
  1708. * component format.
  1709. */
  1710. if (msa_config->component_format ==
  1711. MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422)
  1712. /* YCbCr422 color component format. */
  1713. bits_per_pixel = msa_config->bits_per_color * 2;
  1714. else
  1715. /* RGB or YCbCr 4:4:4 color component format. */
  1716. bits_per_pixel = msa_config->bits_per_color * 3;
  1717. /* Calculate the data per lane. */
  1718. words_per_line = (msa_config->h_active * bits_per_pixel);
  1719. if (words_per_line % 16)
  1720. words_per_line += 16;
  1721. words_per_line /= 16;
  1722. msa_config->data_per_lane = words_per_line - link_config->lane_count;
  1723. if (words_per_line % link_config->lane_count)
  1724. msa_config->data_per_lane += (words_per_line %
  1725. link_config->lane_count);
  1726. /*
  1727. * Allocate a fixed size for single-stream transport (SST)
  1728. * operation.
  1729. */
  1730. msa_config->transfer_unit_size = 64;
  1731. /*
  1732. * Calculate the average number of bytes per transfer unit.
  1733. * Note: Both the integer and the fractional part is stored in
  1734. * avg_bytes_per_tu.
  1735. */
  1736. video_bw = ((msa_config->pixel_clock_hz / 1000) * bits_per_pixel) / 8;
  1737. link_bw = (link_config->lane_count * link_config->link_rate * 27);
  1738. msa_config->avg_bytes_per_tu = (video_bw *
  1739. msa_config->transfer_unit_size) /
  1740. link_bw;
  1741. /*
  1742. * The number of initial wait cycles at the start of a new line
  1743. * by the framing logic. This allows enough data to be buffered
  1744. * in the input FIFO before video is sent.
  1745. */
  1746. if ((msa_config->avg_bytes_per_tu / 1000) <= 4)
  1747. msa_config->init_wait = 64;
  1748. else
  1749. msa_config->init_wait = msa_config->transfer_unit_size -
  1750. (msa_config->avg_bytes_per_tu / 1000);
  1751. }
  1752. /**
  1753. * set_line_reset() - Enable/Disable end-of-line-reset
  1754. * @dev: The LogiCore DP TX device in question
  1755. *
  1756. * Disable/enable the end-of-line-reset to the internal video pipe in case of
  1757. * reduced blanking as required.
  1758. */
  1759. static void set_line_reset(struct udevice *dev)
  1760. {
  1761. struct dp_tx *dp_tx = dev_get_priv(dev);
  1762. u32 reg_val;
  1763. u16 h_blank;
  1764. u16 h_reduced_blank;
  1765. struct main_stream_attributes *msa_config =
  1766. &dp_tx->main_stream_attributes;
  1767. h_blank = msa_config->h_total - msa_config->h_active;
  1768. /* Reduced blanking starts at ceil(0.2 * HTotal). */
  1769. h_reduced_blank = 2 * msa_config->h_total;
  1770. if (h_reduced_blank % 10)
  1771. h_reduced_blank += 10;
  1772. h_reduced_blank /= 10;
  1773. /* CVT spec. states h_blank is either 80 or 160 for reduced blanking. */
  1774. reg_val = get_reg(dev, REG_LINE_RESET_DISABLE);
  1775. if (h_blank < h_reduced_blank &&
  1776. (h_blank == 80 || h_blank == 160)) {
  1777. reg_val |= LINE_RESET_DISABLE_MASK;
  1778. } else {
  1779. reg_val &= ~LINE_RESET_DISABLE_MASK;
  1780. }
  1781. set_reg(dev, REG_LINE_RESET_DISABLE, reg_val);
  1782. }
  1783. /**
  1784. * clear_msa_values() - Clear MSA values
  1785. * @dev: The LogiCore DP TX device in question
  1786. *
  1787. * Clear the main stream attributes registers of the DisplayPort TX core.
  1788. */
  1789. static void clear_msa_values(struct udevice *dev)
  1790. {
  1791. set_reg(dev, REG_MAIN_STREAM_HTOTAL, 0);
  1792. set_reg(dev, REG_MAIN_STREAM_VTOTAL, 0);
  1793. set_reg(dev, REG_MAIN_STREAM_POLARITY, 0);
  1794. set_reg(dev, REG_MAIN_STREAM_HSWIDTH, 0);
  1795. set_reg(dev, REG_MAIN_STREAM_VSWIDTH, 0);
  1796. set_reg(dev, REG_MAIN_STREAM_HRES, 0);
  1797. set_reg(dev, REG_MAIN_STREAM_VRES, 0);
  1798. set_reg(dev, REG_MAIN_STREAM_HSTART, 0);
  1799. set_reg(dev, REG_MAIN_STREAM_VSTART, 0);
  1800. set_reg(dev, REG_MAIN_STREAM_MISC0, 0);
  1801. set_reg(dev, REG_MAIN_STREAM_MISC1, 0);
  1802. set_reg(dev, REG_USER_PIXEL_WIDTH, 0);
  1803. set_reg(dev, REG_USER_DATA_COUNT_PER_LANE, 0);
  1804. set_reg(dev, REG_M_VID, 0);
  1805. set_reg(dev, REG_N_VID, 0);
  1806. set_reg(dev, REG_STREAM1, 0);
  1807. set_reg(dev, REG_TU_SIZE, 0);
  1808. set_reg(dev, REG_MIN_BYTES_PER_TU, 0);
  1809. set_reg(dev, REG_FRAC_BYTES_PER_TU, 0);
  1810. set_reg(dev, REG_INIT_WAIT, 0);
  1811. }
  1812. /**
  1813. * set_msa_values() - Set MSA values
  1814. * @dev: The LogiCore DP TX device in question
  1815. *
  1816. * Set the main stream attributes registers of the DisplayPort TX
  1817. * core with the values specified in the main stream attributes configuration
  1818. * structure.
  1819. */
  1820. static void set_msa_values(struct udevice *dev)
  1821. {
  1822. struct dp_tx *dp_tx = dev_get_priv(dev);
  1823. struct main_stream_attributes *msa_config =
  1824. &dp_tx->main_stream_attributes;
  1825. printf(" set MSA %u x %u\n", msa_config->h_active,
  1826. msa_config->v_active);
  1827. set_reg(dev, REG_MAIN_STREAM_HTOTAL, msa_config->h_total);
  1828. set_reg(dev, REG_MAIN_STREAM_VTOTAL, msa_config->v_total);
  1829. set_reg(dev, REG_MAIN_STREAM_POLARITY,
  1830. msa_config->h_sync_polarity |
  1831. (msa_config->v_sync_polarity <<
  1832. MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT));
  1833. set_reg(dev, REG_MAIN_STREAM_HSWIDTH, msa_config->h_sync_width);
  1834. set_reg(dev, REG_MAIN_STREAM_VSWIDTH, msa_config->v_sync_width);
  1835. set_reg(dev, REG_MAIN_STREAM_HRES, msa_config->h_active);
  1836. set_reg(dev, REG_MAIN_STREAM_VRES, msa_config->v_active);
  1837. set_reg(dev, REG_MAIN_STREAM_HSTART, msa_config->h_start);
  1838. set_reg(dev, REG_MAIN_STREAM_VSTART, msa_config->v_start);
  1839. set_reg(dev, REG_MAIN_STREAM_MISC0, msa_config->misc_0);
  1840. set_reg(dev, REG_MAIN_STREAM_MISC1, msa_config->misc_1);
  1841. set_reg(dev, REG_USER_PIXEL_WIDTH, msa_config->user_pixel_width);
  1842. set_reg(dev, REG_M_VID, msa_config->pixel_clock_hz / 1000);
  1843. set_reg(dev, REG_N_VID, msa_config->n_vid);
  1844. set_reg(dev, REG_USER_DATA_COUNT_PER_LANE, msa_config->data_per_lane);
  1845. set_line_reset(dev);
  1846. set_reg(dev, REG_TU_SIZE, msa_config->transfer_unit_size);
  1847. set_reg(dev, REG_MIN_BYTES_PER_TU, msa_config->avg_bytes_per_tu / 1000);
  1848. set_reg(dev, REG_FRAC_BYTES_PER_TU,
  1849. (msa_config->avg_bytes_per_tu % 1000) * 1024 / 1000);
  1850. set_reg(dev, REG_INIT_WAIT, msa_config->init_wait);
  1851. }
  1852. /*
  1853. * external API
  1854. */
  1855. /**
  1856. * logicore_dp_tx_set_msa() - Set given MSA values on device
  1857. * @dev: The LogiCore DP TX device in question
  1858. * @msa: The MSA values to set for the device
  1859. */
  1860. static void logicore_dp_tx_set_msa(struct udevice *dev,
  1861. struct logicore_dp_tx_msa *msa)
  1862. {
  1863. struct dp_tx *dp_tx = dev_get_priv(dev);
  1864. memset(&dp_tx->main_stream_attributes, 0,
  1865. sizeof(struct main_stream_attributes));
  1866. dp_tx->main_stream_attributes.pixel_clock_hz = msa->pixel_clock_hz;
  1867. dp_tx->main_stream_attributes.bits_per_color = msa->bits_per_color;
  1868. dp_tx->main_stream_attributes.h_active = msa->h_active;
  1869. dp_tx->main_stream_attributes.h_start = msa->h_start;
  1870. dp_tx->main_stream_attributes.h_sync_polarity = msa->h_sync_polarity;
  1871. dp_tx->main_stream_attributes.h_sync_width = msa->h_sync_width;
  1872. dp_tx->main_stream_attributes.h_total = msa->h_total;
  1873. dp_tx->main_stream_attributes.v_active = msa->v_active;
  1874. dp_tx->main_stream_attributes.v_start = msa->v_start;
  1875. dp_tx->main_stream_attributes.v_sync_polarity = msa->v_sync_polarity;
  1876. dp_tx->main_stream_attributes.v_sync_width = msa->v_sync_width;
  1877. dp_tx->main_stream_attributes.v_total = msa->v_total;
  1878. dp_tx->main_stream_attributes.override_user_pixel_width =
  1879. msa->override_user_pixel_width;
  1880. dp_tx->main_stream_attributes.user_pixel_width = msa->user_pixel_width;
  1881. dp_tx->main_stream_attributes.synchronous_clock_mode = 0;
  1882. }
  1883. /**
  1884. * logicore_dp_tx_video_enable() - Enable video output
  1885. * @dev: The LogiCore DP TX device in question
  1886. * @msa: The MSA values to set for the device
  1887. *
  1888. * Return: 0 if the video was enabled successfully, -ve on error
  1889. */
  1890. static int logicore_dp_tx_video_enable(struct udevice *dev,
  1891. struct logicore_dp_tx_msa *msa)
  1892. {
  1893. struct dp_tx *dp_tx = dev_get_priv(dev);
  1894. int res;
  1895. u8 power = 0x01;
  1896. if (!is_connected(dev)) {
  1897. printf(" no DP sink connected\n");
  1898. return -EIO;
  1899. }
  1900. initialize(dev);
  1901. disable_main_link(dev);
  1902. logicore_dp_tx_set_msa(dev, msa);
  1903. get_rx_capabilities(dev);
  1904. printf(" DP sink connected\n");
  1905. aux_write(dev, DPCD_SET_POWER_DP_PWR_VOLTAGE, 1, &power);
  1906. set_enhanced_frame_mode(dev, true);
  1907. cfg_main_link_max(dev);
  1908. res = establish_link(dev);
  1909. printf(" establish_link: %s, vs: %d, pe: %d\n",
  1910. res ? "failed" : "ok", dp_tx->link_config.vs_level,
  1911. dp_tx->link_config.pe_level);
  1912. cfg_msa_recalculate(dev);
  1913. clear_msa_values(dev);
  1914. set_msa_values(dev);
  1915. enable_main_link(dev);
  1916. return 0;
  1917. }
  1918. /*
  1919. * Driver functions
  1920. */
  1921. static int logicore_dp_tx_enable(struct udevice *dev, int panel_bpp,
  1922. const struct display_timing *timing)
  1923. {
  1924. struct clk pixclock;
  1925. struct logicore_dp_tx_msa *msa;
  1926. struct logicore_dp_tx_msa mode_640_480_60 = {
  1927. .pixel_clock_hz = 25175000,
  1928. .bits_per_color = 8,
  1929. .h_active = 640,
  1930. .h_start = 144,
  1931. .h_sync_polarity = false,
  1932. .h_sync_width = 96,
  1933. .h_total = 800,
  1934. .v_active = 480,
  1935. .v_start = 35,
  1936. .v_sync_polarity = false,
  1937. .v_sync_width = 2,
  1938. .v_total = 525,
  1939. .override_user_pixel_width = false,
  1940. .user_pixel_width = 0,
  1941. };
  1942. struct logicore_dp_tx_msa mode_720_400_70 = {
  1943. .pixel_clock_hz = 28300000,
  1944. .bits_per_color = 8,
  1945. .h_active = 720,
  1946. .h_start = 162,
  1947. .h_sync_polarity = false,
  1948. .h_sync_width = 108,
  1949. .h_total = 900,
  1950. .v_active = 400,
  1951. .v_start = 37,
  1952. .v_sync_polarity = true,
  1953. .v_sync_width = 2,
  1954. .v_total = 449,
  1955. .override_user_pixel_width = false,
  1956. .user_pixel_width = 0,
  1957. };
  1958. struct logicore_dp_tx_msa mode_1024_768_60 = {
  1959. .pixel_clock_hz = 65000000,
  1960. .bits_per_color = 8,
  1961. .h_active = 1024,
  1962. .h_start = 296,
  1963. .h_sync_polarity = false,
  1964. .h_sync_width = 136,
  1965. .h_total = 1344,
  1966. .v_active = 768,
  1967. .v_start = 35,
  1968. .v_sync_polarity = false,
  1969. .v_sync_width = 2,
  1970. .v_total = 806,
  1971. .override_user_pixel_width = false,
  1972. .user_pixel_width = 0,
  1973. };
  1974. if (timing->hactive.typ == 1024 && timing->vactive.typ == 768)
  1975. msa = &mode_1024_768_60;
  1976. else if (timing->hactive.typ == 720 && timing->vactive.typ == 400)
  1977. msa = &mode_720_400_70;
  1978. else
  1979. msa = &mode_640_480_60;
  1980. if (clk_get_by_index(dev, 0, &pixclock)) {
  1981. printf("%s: Could not get pixelclock\n", dev->name);
  1982. return -1;
  1983. }
  1984. clk_set_rate(&pixclock, msa->pixel_clock_hz);
  1985. return logicore_dp_tx_video_enable(dev, msa);
  1986. }
  1987. static int logicore_dp_tx_probe(struct udevice *dev)
  1988. {
  1989. struct dp_tx *dp_tx = dev_get_priv(dev);
  1990. dp_tx->s_axi_clk = S_AXI_CLK_DEFAULT;
  1991. dp_tx->train_adaptive = false;
  1992. dp_tx->max_link_rate = DPCD_MAX_LINK_RATE_540GBPS;
  1993. dp_tx->max_lane_count = DPCD_MAX_LANE_COUNT_4;
  1994. dp_tx->base = dev_read_u32_default(dev, "reg", -1);
  1995. return 0;
  1996. }
  1997. static const struct dm_display_ops logicore_dp_tx_ops = {
  1998. .enable = logicore_dp_tx_enable,
  1999. };
  2000. static const struct udevice_id logicore_dp_tx_ids[] = {
  2001. { .compatible = "gdsys,logicore_dp_tx" },
  2002. { /* sentinel */ }
  2003. };
  2004. U_BOOT_DRIVER(logicore_dp_tx) = {
  2005. .name = "logicore_dp_tx",
  2006. .id = UCLASS_DISPLAY,
  2007. .of_match = logicore_dp_tx_ids,
  2008. .probe = logicore_dp_tx_probe,
  2009. .priv_auto_alloc_size = sizeof(struct dp_tx),
  2010. .ops = &logicore_dp_tx_ops,
  2011. };