ihs_video_out.c 8.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2017
  4. * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
  5. *
  6. * based on the gdsys osd driver, which is
  7. *
  8. * (C) Copyright 2010
  9. * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.de
  10. */
  11. #include <common.h>
  12. #include <display.h>
  13. #include <dm.h>
  14. #include <regmap.h>
  15. #include <video_osd.h>
  16. #include <asm/gpio.h>
  17. static const uint MAX_X_CHARS = 53;
  18. static const uint MAX_Y_CHARS = 26;
  19. static const uint MAX_VIDEOMEM_WIDTH = 64;
  20. static const uint MAX_VIDEOMEM_HEIGHT = 32;
  21. static const uint CHAR_WIDTH = 12;
  22. static const uint CHAR_HEIGHT = 18;
  23. static const u16 BASE_WIDTH_MASK = 0x3f00;
  24. static const uint BASE_WIDTH_SHIFT = 8;
  25. static const u16 BASE_HEIGTH_MASK = 0x001f;
  26. static const uint BASE_HEIGTH_SHIFT;
  27. struct ihs_video_out_regs {
  28. /* Device version register */
  29. u16 versions;
  30. /* Device feature register */
  31. u16 features;
  32. /* Device control register */
  33. u16 control;
  34. /* Register controlling screen size */
  35. u16 xy_size;
  36. /* Register controlling screen scaling */
  37. u16 xy_scale;
  38. /* Register controlling screen x position */
  39. u16 x_pos;
  40. /* Register controlling screen y position */
  41. u16 y_pos;
  42. };
  43. #define ihs_video_out_set(map, member, val) \
  44. regmap_range_set(map, 1, struct ihs_video_out_regs, member, val)
  45. #define ihs_video_out_get(map, member, valp) \
  46. regmap_range_get(map, 1, struct ihs_video_out_regs, member, valp)
  47. enum {
  48. CONTROL_FILTER_BLACK = (0 << 0),
  49. CONTROL_FILTER_ORIGINAL = (1 << 0),
  50. CONTROL_FILTER_DARKER = (2 << 0),
  51. CONTROL_FILTER_GRAY = (3 << 0),
  52. CONTROL_MODE_PASSTHROUGH = (0 << 3),
  53. CONTROL_MODE_OSD = (1 << 3),
  54. CONTROL_MODE_AUTO = (2 << 3),
  55. CONTROL_MODE_OFF = (3 << 3),
  56. CONTROL_ENABLE_OFF = (0 << 6),
  57. CONTROL_ENABLE_ON = (1 << 6),
  58. };
  59. struct ihs_video_out_priv {
  60. /* Register map for OSD device */
  61. struct regmap *map;
  62. /* Pointer to video memory */
  63. u16 *vidmem;
  64. /* Display width in text columns */
  65. uint base_width;
  66. /* Display height in text rows */
  67. uint base_height;
  68. /* x-resolution of the display in pixels */
  69. uint res_x;
  70. /* y-resolution of the display in pixels */
  71. uint res_y;
  72. /* OSD's sync mode (resolution + frequency) */
  73. int sync_src;
  74. /* The display port output for this OSD */
  75. struct udevice *video_tx;
  76. /* The pixel clock generator for the display */
  77. struct udevice *clk_gen;
  78. };
  79. static const struct udevice_id ihs_video_out_ids[] = {
  80. { .compatible = "gdsys,ihs_video_out" },
  81. { }
  82. };
  83. /**
  84. * set_control() - Set the control register to a given value
  85. *
  86. * The current value of sync_src is preserved by the function automatically.
  87. *
  88. * @dev: the OSD device whose control register to set
  89. * @value: the 16-bit value to write to the control register
  90. * Return: 0
  91. */
  92. static int set_control(struct udevice *dev, u16 value)
  93. {
  94. struct ihs_video_out_priv *priv = dev_get_priv(dev);
  95. if (priv->sync_src)
  96. value |= ((priv->sync_src & 0x7) << 8);
  97. ihs_video_out_set(priv->map, control, value);
  98. return 0;
  99. }
  100. int ihs_video_out_get_info(struct udevice *dev, struct video_osd_info *info)
  101. {
  102. struct ihs_video_out_priv *priv = dev_get_priv(dev);
  103. u16 versions;
  104. ihs_video_out_get(priv->map, versions, &versions);
  105. info->width = priv->base_width;
  106. info->height = priv->base_height;
  107. info->major_version = versions / 100;
  108. info->minor_version = versions % 100;
  109. return 0;
  110. }
  111. int ihs_video_out_set_mem(struct udevice *dev, uint col, uint row, u8 *buf,
  112. size_t buflen, uint count)
  113. {
  114. struct ihs_video_out_priv *priv = dev_get_priv(dev);
  115. int res;
  116. uint offset;
  117. uint k, rep;
  118. u16 data;
  119. /* Repetitions (controlled via count parmeter) */
  120. for (rep = 0; rep < count; ++rep) {
  121. offset = row * priv->base_width + col + rep * (buflen / 2);
  122. /* Write a single buffer copy */
  123. for (k = 0; k < buflen / 2; ++k) {
  124. uint max_size = priv->base_width * priv->base_height;
  125. if (offset + k >= max_size) {
  126. debug("%s: Write would be out of OSD bounds\n",
  127. dev->name);
  128. return -E2BIG;
  129. }
  130. data = buf[2 * k + 1] + 256 * buf[2 * k];
  131. out_le16(priv->vidmem + offset + k, data);
  132. }
  133. }
  134. res = set_control(dev, CONTROL_FILTER_ORIGINAL |
  135. CONTROL_MODE_OSD |
  136. CONTROL_ENABLE_ON);
  137. if (res) {
  138. debug("%s: Could not set control register\n", dev->name);
  139. return res;
  140. }
  141. return 0;
  142. }
  143. /**
  144. * div2_u16() - Approximately divide a 16-bit number by 2
  145. *
  146. * @val: The 16-bit value to divide by two
  147. * Return: The approximate division of val by two
  148. */
  149. static inline u16 div2_u16(u16 val)
  150. {
  151. return (32767 * val) / 65535;
  152. }
  153. int ihs_video_out_set_size(struct udevice *dev, uint col, uint row)
  154. {
  155. struct ihs_video_out_priv *priv = dev_get_priv(dev);
  156. if (!col || col > MAX_VIDEOMEM_WIDTH || col > MAX_X_CHARS ||
  157. !row || row > MAX_VIDEOMEM_HEIGHT || row > MAX_Y_CHARS) {
  158. debug("%s: Desired OSD size invalid\n", dev->name);
  159. return -EINVAL;
  160. }
  161. ihs_video_out_set(priv->map, xy_size, ((col - 1) << 8) | (row - 1));
  162. /* Center OSD on screen */
  163. ihs_video_out_set(priv->map, x_pos,
  164. div2_u16(priv->res_x - CHAR_WIDTH * col));
  165. ihs_video_out_set(priv->map, y_pos,
  166. div2_u16(priv->res_y - CHAR_HEIGHT * row));
  167. return 0;
  168. }
  169. int ihs_video_out_print(struct udevice *dev, uint col, uint row, ulong color,
  170. char *text)
  171. {
  172. int res;
  173. u8 buffer[2 * MAX_VIDEOMEM_WIDTH];
  174. uint k;
  175. uint charcount = strlen(text);
  176. uint len = min(charcount, 2 * MAX_VIDEOMEM_WIDTH);
  177. for (k = 0; k < len; ++k) {
  178. buffer[2 * k] = text[k];
  179. buffer[2 * k + 1] = color;
  180. }
  181. res = ihs_video_out_set_mem(dev, col, row, buffer, 2 * len, 1);
  182. if (res < 0) {
  183. debug("%s: Could not write to video memory\n", dev->name);
  184. return res;
  185. }
  186. return 0;
  187. }
  188. static const struct video_osd_ops ihs_video_out_ops = {
  189. .get_info = ihs_video_out_get_info,
  190. .set_mem = ihs_video_out_set_mem,
  191. .set_size = ihs_video_out_set_size,
  192. .print = ihs_video_out_print,
  193. };
  194. int ihs_video_out_probe(struct udevice *dev)
  195. {
  196. struct ihs_video_out_priv *priv = dev_get_priv(dev);
  197. struct ofnode_phandle_args phandle_args;
  198. const char *mode;
  199. u16 features;
  200. struct display_timing timing;
  201. int res;
  202. res = regmap_init_mem(dev_ofnode(dev), &priv->map);
  203. if (res) {
  204. debug("%s: Could not initialize regmap (err = %d)\n", dev->name,
  205. res);
  206. return res;
  207. }
  208. /* Range with index 2 is video memory */
  209. priv->vidmem = regmap_get_range(priv->map, 2);
  210. mode = dev_read_string(dev, "mode");
  211. if (!mode) {
  212. debug("%s: Could not read mode property\n", dev->name);
  213. return -EINVAL;
  214. }
  215. if (!strcmp(mode, "1024_768_60")) {
  216. priv->sync_src = 2;
  217. priv->res_x = 1024;
  218. priv->res_y = 768;
  219. timing.hactive.typ = 1024;
  220. timing.vactive.typ = 768;
  221. } else if (!strcmp(mode, "720_400_70")) {
  222. priv->sync_src = 1;
  223. priv->res_x = 720;
  224. priv->res_y = 400;
  225. timing.hactive.typ = 720;
  226. timing.vactive.typ = 400;
  227. } else {
  228. priv->sync_src = 0;
  229. priv->res_x = 640;
  230. priv->res_y = 480;
  231. timing.hactive.typ = 640;
  232. timing.vactive.typ = 480;
  233. }
  234. ihs_video_out_get(priv->map, features, &features);
  235. res = set_control(dev, CONTROL_FILTER_ORIGINAL |
  236. CONTROL_MODE_OSD |
  237. CONTROL_ENABLE_OFF);
  238. if (res) {
  239. debug("%s: Could not set control register (err = %d)\n",
  240. dev->name, res);
  241. return res;
  242. }
  243. priv->base_width = ((features & BASE_WIDTH_MASK)
  244. >> BASE_WIDTH_SHIFT) + 1;
  245. priv->base_height = ((features & BASE_HEIGTH_MASK)
  246. >> BASE_HEIGTH_SHIFT) + 1;
  247. res = dev_read_phandle_with_args(dev, "clk_gen", NULL, 0, 0,
  248. &phandle_args);
  249. if (res) {
  250. debug("%s: Could not get clk_gen node (err = %d)\n",
  251. dev->name, res);
  252. return -EINVAL;
  253. }
  254. res = uclass_get_device_by_ofnode(UCLASS_CLK, phandle_args.node,
  255. &priv->clk_gen);
  256. if (res) {
  257. debug("%s: Could not get clk_gen dev (err = %d)\n",
  258. dev->name, res);
  259. return -EINVAL;
  260. }
  261. res = dev_read_phandle_with_args(dev, "video_tx", NULL, 0, 0,
  262. &phandle_args);
  263. if (res) {
  264. debug("%s: Could not get video_tx (err = %d)\n",
  265. dev->name, res);
  266. return -EINVAL;
  267. }
  268. res = uclass_get_device_by_ofnode(UCLASS_DISPLAY, phandle_args.node,
  269. &priv->video_tx);
  270. if (res) {
  271. debug("%s: Could not get video_tx dev (err = %d)\n",
  272. dev->name, res);
  273. return -EINVAL;
  274. }
  275. res = display_enable(priv->video_tx, 8, &timing);
  276. if (res && res != -EIO) { /* Ignore missing DP sink error */
  277. debug("%s: Could not enable the display (err = %d)\n",
  278. dev->name, res);
  279. return res;
  280. }
  281. return 0;
  282. }
  283. U_BOOT_DRIVER(ihs_video_out_drv) = {
  284. .name = "ihs_video_out_drv",
  285. .id = UCLASS_VIDEO_OSD,
  286. .ops = &ihs_video_out_ops,
  287. .of_match = ihs_video_out_ids,
  288. .probe = ihs_video_out_probe,
  289. .priv_auto_alloc_size = sizeof(struct ihs_video_out_priv),
  290. };