fsl_dcu_fb.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. * Copyright 2019 Toradex AG
  5. *
  6. * FSL DCU Framebuffer driver
  7. */
  8. #include <init.h>
  9. #include <asm/io.h>
  10. #include <common.h>
  11. #include <dm.h>
  12. #include <fdt_support.h>
  13. #include <fsl_dcu_fb.h>
  14. #include <linux/fb.h>
  15. #include <malloc.h>
  16. #include <video.h>
  17. #include <video_fb.h>
  18. #include "videomodes.h"
  19. /* Convert the X,Y resolution pair into a single number */
  20. #define RESOLUTION(x, y) (((u32)(x) << 16) | (y))
  21. #ifdef CONFIG_SYS_FSL_DCU_LE
  22. #define dcu_read32 in_le32
  23. #define dcu_write32 out_le32
  24. #elif defined(CONFIG_SYS_FSL_DCU_BE)
  25. #define dcu_read32 in_be32
  26. #define dcu_write32 out_be32
  27. #endif
  28. #define DCU_MODE_BLEND_ITER(x) ((x) << 20)
  29. #define DCU_MODE_RASTER_EN (1 << 14)
  30. #define DCU_MODE_NORMAL 1
  31. #define DCU_MODE_COLORBAR 3
  32. #define DCU_BGND_R(x) ((x) << 16)
  33. #define DCU_BGND_G(x) ((x) << 8)
  34. #define DCU_BGND_B(x) (x)
  35. #define DCU_DISP_SIZE_DELTA_Y(x) ((x) << 16)
  36. #define DCU_DISP_SIZE_DELTA_X(x) (x)
  37. #define DCU_HSYN_PARA_BP(x) ((x) << 22)
  38. #define DCU_HSYN_PARA_PW(x) ((x) << 11)
  39. #define DCU_HSYN_PARA_FP(x) (x)
  40. #define DCU_VSYN_PARA_BP(x) ((x) << 22)
  41. #define DCU_VSYN_PARA_PW(x) ((x) << 11)
  42. #define DCU_VSYN_PARA_FP(x) (x)
  43. #define DCU_SYN_POL_INV_PXCK_FALL (1 << 6)
  44. #define DCU_SYN_POL_NEG_REMAIN (0 << 5)
  45. #define DCU_SYN_POL_INV_VS_LOW (1 << 1)
  46. #define DCU_SYN_POL_INV_HS_LOW (1)
  47. #define DCU_THRESHOLD_LS_BF_VS(x) ((x) << 16)
  48. #define DCU_THRESHOLD_OUT_BUF_HIGH(x) ((x) << 8)
  49. #define DCU_THRESHOLD_OUT_BUF_LOW(x) (x)
  50. #define DCU_UPDATE_MODE_MODE (1 << 31)
  51. #define DCU_UPDATE_MODE_READREG (1 << 30)
  52. #define DCU_CTRLDESCLN_1_HEIGHT(x) ((x) << 16)
  53. #define DCU_CTRLDESCLN_1_WIDTH(x) (x)
  54. #define DCU_CTRLDESCLN_2_POSY(x) ((x) << 16)
  55. #define DCU_CTRLDESCLN_2_POSX(x) (x)
  56. #define DCU_CTRLDESCLN_4_EN (1 << 31)
  57. #define DCU_CTRLDESCLN_4_TILE_EN (1 << 30)
  58. #define DCU_CTRLDESCLN_4_DATA_SEL_CLUT (1 << 29)
  59. #define DCU_CTRLDESCLN_4_SAFETY_EN (1 << 28)
  60. #define DCU_CTRLDESCLN_4_TRANS(x) ((x) << 20)
  61. #define DCU_CTRLDESCLN_4_BPP(x) ((x) << 16)
  62. #define DCU_CTRLDESCLN_4_RLE_EN (1 << 15)
  63. #define DCU_CTRLDESCLN_4_LUOFFS(x) ((x) << 4)
  64. #define DCU_CTRLDESCLN_4_BB_ON (1 << 2)
  65. #define DCU_CTRLDESCLN_4_AB(x) (x)
  66. #define DCU_CTRLDESCLN_5_CKMAX_R(x) ((x) << 16)
  67. #define DCU_CTRLDESCLN_5_CKMAX_G(x) ((x) << 8)
  68. #define DCU_CTRLDESCLN_5_CKMAX_B(x) (x)
  69. #define DCU_CTRLDESCLN_6_CKMIN_R(x) ((x) << 16)
  70. #define DCU_CTRLDESCLN_6_CKMIN_G(x) ((x) << 8)
  71. #define DCU_CTRLDESCLN_6_CKMIN_B(x) (x)
  72. #define DCU_CTRLDESCLN_7_TILE_VER(x) ((x) << 16)
  73. #define DCU_CTRLDESCLN_7_TILE_HOR(x) (x)
  74. #define DCU_CTRLDESCLN_8_FG_FCOLOR(x) (x)
  75. #define DCU_CTRLDESCLN_9_BG_BCOLOR(x) (x)
  76. #define BPP_16_RGB565 4
  77. #define BPP_24_RGB888 5
  78. #define BPP_32_ARGB8888 6
  79. DECLARE_GLOBAL_DATA_PTR;
  80. /*
  81. * This setting is used for the TWR_LCD_RGB card
  82. */
  83. static struct fb_videomode fsl_dcu_mode_480_272 = {
  84. .name = "480x272-60",
  85. .refresh = 60,
  86. .xres = 480,
  87. .yres = 272,
  88. .pixclock = 91996,
  89. .left_margin = 2,
  90. .right_margin = 2,
  91. .upper_margin = 1,
  92. .lower_margin = 1,
  93. .hsync_len = 41,
  94. .vsync_len = 2,
  95. .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  96. .vmode = FB_VMODE_NONINTERLACED
  97. };
  98. /*
  99. * This setting is used for Siliconimage SiI9022A HDMI
  100. */
  101. static struct fb_videomode fsl_dcu_cea_mode_640_480 = {
  102. .name = "640x480-60",
  103. .refresh = 60,
  104. .xres = 640,
  105. .yres = 480,
  106. .pixclock = 39722,
  107. .left_margin = 48,
  108. .right_margin = 16,
  109. .upper_margin = 33,
  110. .lower_margin = 10,
  111. .hsync_len = 96,
  112. .vsync_len = 2,
  113. .sync = 0,
  114. .vmode = FB_VMODE_NONINTERLACED,
  115. };
  116. static struct fb_videomode fsl_dcu_mode_640_480 = {
  117. .name = "640x480-60",
  118. .refresh = 60,
  119. .xres = 640,
  120. .yres = 480,
  121. .pixclock = 25175,
  122. .left_margin = 40,
  123. .right_margin = 24,
  124. .upper_margin = 32,
  125. .lower_margin = 11,
  126. .hsync_len = 96,
  127. .vsync_len = 2,
  128. .sync = 0,
  129. .vmode = FB_VMODE_NONINTERLACED,
  130. };
  131. static struct fb_videomode fsl_dcu_mode_800_480 = {
  132. .name = "800x480-60",
  133. .refresh = 60,
  134. .xres = 800,
  135. .yres = 480,
  136. .pixclock = 33260,
  137. .left_margin = 216,
  138. .right_margin = 40,
  139. .upper_margin = 35,
  140. .lower_margin = 10,
  141. .hsync_len = 128,
  142. .vsync_len = 2,
  143. .sync = 0,
  144. .vmode = FB_VMODE_NONINTERLACED,
  145. };
  146. static struct fb_videomode fsl_dcu_mode_1024_600 = {
  147. .name = "1024x600-60",
  148. .refresh = 60,
  149. .xres = 1024,
  150. .yres = 600,
  151. .pixclock = 48000,
  152. .left_margin = 104,
  153. .right_margin = 43,
  154. .upper_margin = 24,
  155. .lower_margin = 20,
  156. .hsync_len = 5,
  157. .vsync_len = 5,
  158. .sync = 0,
  159. .vmode = FB_VMODE_NONINTERLACED,
  160. };
  161. /*
  162. * DCU register map
  163. */
  164. struct dcu_reg {
  165. u32 desc_cursor[4];
  166. u32 mode;
  167. u32 bgnd;
  168. u32 disp_size;
  169. u32 hsyn_para;
  170. u32 vsyn_para;
  171. u32 synpol;
  172. u32 threshold;
  173. u32 int_status;
  174. u32 int_mask;
  175. u32 colbar[8];
  176. u32 div_ratio;
  177. u32 sign_calc[2];
  178. u32 crc_val;
  179. u8 res_064[0x6c-0x64];
  180. u32 parr_err_status1;
  181. u8 res_070[0x7c-0x70];
  182. u32 parr_err_status3;
  183. u32 mparr_err_status1;
  184. u8 res_084[0x90-0x84];
  185. u32 mparr_err_status3;
  186. u32 threshold_inp_buf[2];
  187. u8 res_09c[0xa0-0x9c];
  188. u32 luma_comp;
  189. u32 chroma_red;
  190. u32 chroma_green;
  191. u32 chroma_blue;
  192. u32 crc_pos;
  193. u32 lyr_intpol_en;
  194. u32 lyr_luma_comp;
  195. u32 lyr_chrm_red;
  196. u32 lyr_chrm_grn;
  197. u32 lyr_chrm_blue;
  198. u8 res_0c4[0xcc-0xc8];
  199. u32 update_mode;
  200. u32 underrun;
  201. u8 res_0d4[0x100-0xd4];
  202. u32 gpr;
  203. u32 slr_l[2];
  204. u32 slr_disp_size;
  205. u32 slr_hvsync_para;
  206. u32 slr_pol;
  207. u32 slr_l_transp[2];
  208. u8 res_120[0x200-0x120];
  209. u32 ctrldescl[DCU_LAYER_MAX_NUM][16];
  210. };
  211. static void reset_total_layers(void)
  212. {
  213. struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
  214. int i;
  215. for (i = 0; i < DCU_LAYER_MAX_NUM; i++) {
  216. dcu_write32(&regs->ctrldescl[i][0], 0);
  217. dcu_write32(&regs->ctrldescl[i][1], 0);
  218. dcu_write32(&regs->ctrldescl[i][2], 0);
  219. dcu_write32(&regs->ctrldescl[i][3], 0);
  220. dcu_write32(&regs->ctrldescl[i][4], 0);
  221. dcu_write32(&regs->ctrldescl[i][5], 0);
  222. dcu_write32(&regs->ctrldescl[i][6], 0);
  223. dcu_write32(&regs->ctrldescl[i][7], 0);
  224. dcu_write32(&regs->ctrldescl[i][8], 0);
  225. dcu_write32(&regs->ctrldescl[i][9], 0);
  226. dcu_write32(&regs->ctrldescl[i][10], 0);
  227. }
  228. }
  229. static int layer_ctrldesc_init(struct fb_info fbinfo,
  230. int index, u32 pixel_format)
  231. {
  232. struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
  233. unsigned int bpp = BPP_24_RGB888;
  234. dcu_write32(&regs->ctrldescl[index][0],
  235. DCU_CTRLDESCLN_1_HEIGHT(fbinfo.var.yres) |
  236. DCU_CTRLDESCLN_1_WIDTH(fbinfo.var.xres));
  237. dcu_write32(&regs->ctrldescl[index][1],
  238. DCU_CTRLDESCLN_2_POSY(0) |
  239. DCU_CTRLDESCLN_2_POSX(0));
  240. dcu_write32(&regs->ctrldescl[index][2],
  241. (unsigned int)fbinfo.screen_base);
  242. switch (pixel_format) {
  243. case 16:
  244. bpp = BPP_16_RGB565;
  245. break;
  246. case 24:
  247. bpp = BPP_24_RGB888;
  248. break;
  249. case 32:
  250. bpp = BPP_32_ARGB8888;
  251. break;
  252. default:
  253. printf("unsupported color depth: %u\n", pixel_format);
  254. }
  255. dcu_write32(&regs->ctrldescl[index][3],
  256. DCU_CTRLDESCLN_4_EN |
  257. DCU_CTRLDESCLN_4_TRANS(0xff) |
  258. DCU_CTRLDESCLN_4_BPP(bpp) |
  259. DCU_CTRLDESCLN_4_AB(0));
  260. dcu_write32(&regs->ctrldescl[index][4],
  261. DCU_CTRLDESCLN_5_CKMAX_R(0xff) |
  262. DCU_CTRLDESCLN_5_CKMAX_G(0xff) |
  263. DCU_CTRLDESCLN_5_CKMAX_B(0xff));
  264. dcu_write32(&regs->ctrldescl[index][5],
  265. DCU_CTRLDESCLN_6_CKMIN_R(0) |
  266. DCU_CTRLDESCLN_6_CKMIN_G(0) |
  267. DCU_CTRLDESCLN_6_CKMIN_B(0));
  268. dcu_write32(&regs->ctrldescl[index][6],
  269. DCU_CTRLDESCLN_7_TILE_VER(0) |
  270. DCU_CTRLDESCLN_7_TILE_HOR(0));
  271. dcu_write32(&regs->ctrldescl[index][7], DCU_CTRLDESCLN_8_FG_FCOLOR(0));
  272. dcu_write32(&regs->ctrldescl[index][8], DCU_CTRLDESCLN_9_BG_BCOLOR(0));
  273. return 0;
  274. }
  275. int fsl_dcu_init(struct fb_info *fbinfo, unsigned int xres,
  276. unsigned int yres, unsigned int pixel_format)
  277. {
  278. struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
  279. unsigned int div, mode;
  280. /*
  281. * When DM_VIDEO is enabled reservation of framebuffer is done
  282. * in advance during bind() call.
  283. */
  284. #if !CONFIG_IS_ENABLED(DM_VIDEO)
  285. fbinfo->screen_size = fbinfo->var.xres * fbinfo->var.yres *
  286. (fbinfo->var.bits_per_pixel / 8);
  287. if (fbinfo->screen_size > CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB) {
  288. fbinfo->screen_size = 0;
  289. return -ENOMEM;
  290. }
  291. /* Reserve framebuffer at the end of memory */
  292. gd->fb_base = gd->bd->bi_dram[0].start +
  293. gd->bd->bi_dram[0].size - fbinfo->screen_size;
  294. fbinfo->screen_base = (char *)gd->fb_base;
  295. memset(fbinfo->screen_base, 0, fbinfo->screen_size);
  296. #endif
  297. reset_total_layers();
  298. dcu_write32(&regs->disp_size,
  299. DCU_DISP_SIZE_DELTA_Y(fbinfo->var.yres) |
  300. DCU_DISP_SIZE_DELTA_X(fbinfo->var.xres / 16));
  301. dcu_write32(&regs->hsyn_para,
  302. DCU_HSYN_PARA_BP(fbinfo->var.left_margin) |
  303. DCU_HSYN_PARA_PW(fbinfo->var.hsync_len) |
  304. DCU_HSYN_PARA_FP(fbinfo->var.right_margin));
  305. dcu_write32(&regs->vsyn_para,
  306. DCU_VSYN_PARA_BP(fbinfo->var.upper_margin) |
  307. DCU_VSYN_PARA_PW(fbinfo->var.vsync_len) |
  308. DCU_VSYN_PARA_FP(fbinfo->var.lower_margin));
  309. dcu_write32(&regs->synpol,
  310. DCU_SYN_POL_INV_PXCK_FALL |
  311. DCU_SYN_POL_NEG_REMAIN |
  312. DCU_SYN_POL_INV_VS_LOW |
  313. DCU_SYN_POL_INV_HS_LOW);
  314. dcu_write32(&regs->bgnd,
  315. DCU_BGND_R(0) | DCU_BGND_G(0) | DCU_BGND_B(0));
  316. dcu_write32(&regs->mode,
  317. DCU_MODE_BLEND_ITER(2) |
  318. DCU_MODE_RASTER_EN);
  319. dcu_write32(&regs->threshold,
  320. DCU_THRESHOLD_LS_BF_VS(0x3) |
  321. DCU_THRESHOLD_OUT_BUF_HIGH(0x78) |
  322. DCU_THRESHOLD_OUT_BUF_LOW(0));
  323. mode = dcu_read32(&regs->mode);
  324. dcu_write32(&regs->mode, mode | DCU_MODE_NORMAL);
  325. layer_ctrldesc_init(*fbinfo, 0, pixel_format);
  326. div = dcu_set_pixel_clock(fbinfo->var.pixclock);
  327. dcu_write32(&regs->div_ratio, (div - 1));
  328. dcu_write32(&regs->update_mode, DCU_UPDATE_MODE_READREG);
  329. return 0;
  330. }
  331. ulong board_get_usable_ram_top(ulong total_size)
  332. {
  333. return gd->ram_top - CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB;
  334. }
  335. int fsl_probe_common(struct fb_info *fbinfo, unsigned int *win_x,
  336. unsigned int *win_y)
  337. {
  338. const char *options;
  339. unsigned int depth = 0, freq = 0;
  340. struct fb_videomode *fsl_dcu_mode_db = &fsl_dcu_mode_480_272;
  341. if (!video_get_video_mode(win_x, win_y, &depth, &freq,
  342. &options))
  343. return -EINVAL;
  344. /* Find the monitor port, which is a required option */
  345. if (!options)
  346. return -EINVAL;
  347. if (strncmp(options, "monitor=", 8) != 0)
  348. return -EINVAL;
  349. switch (RESOLUTION(*win_x, *win_y)) {
  350. case RESOLUTION(480, 272):
  351. fsl_dcu_mode_db = &fsl_dcu_mode_480_272;
  352. break;
  353. case RESOLUTION(640, 480):
  354. if (!strncmp(options, "monitor=hdmi", 12))
  355. fsl_dcu_mode_db = &fsl_dcu_cea_mode_640_480;
  356. else
  357. fsl_dcu_mode_db = &fsl_dcu_mode_640_480;
  358. break;
  359. case RESOLUTION(800, 480):
  360. fsl_dcu_mode_db = &fsl_dcu_mode_800_480;
  361. break;
  362. case RESOLUTION(1024, 600):
  363. fsl_dcu_mode_db = &fsl_dcu_mode_1024_600;
  364. break;
  365. default:
  366. printf("unsupported resolution %ux%u\n",
  367. *win_x, *win_y);
  368. }
  369. fbinfo->var.xres = fsl_dcu_mode_db->xres;
  370. fbinfo->var.yres = fsl_dcu_mode_db->yres;
  371. fbinfo->var.bits_per_pixel = 32;
  372. fbinfo->var.pixclock = fsl_dcu_mode_db->pixclock;
  373. fbinfo->var.left_margin = fsl_dcu_mode_db->left_margin;
  374. fbinfo->var.right_margin = fsl_dcu_mode_db->right_margin;
  375. fbinfo->var.upper_margin = fsl_dcu_mode_db->upper_margin;
  376. fbinfo->var.lower_margin = fsl_dcu_mode_db->lower_margin;
  377. fbinfo->var.hsync_len = fsl_dcu_mode_db->hsync_len;
  378. fbinfo->var.vsync_len = fsl_dcu_mode_db->vsync_len;
  379. fbinfo->var.sync = fsl_dcu_mode_db->sync;
  380. fbinfo->var.vmode = fsl_dcu_mode_db->vmode;
  381. fbinfo->fix.line_length = fbinfo->var.xres *
  382. fbinfo->var.bits_per_pixel / 8;
  383. return platform_dcu_init(fbinfo, *win_x, *win_y,
  384. options + 8, fsl_dcu_mode_db);
  385. }
  386. #ifndef CONFIG_DM_VIDEO
  387. static struct fb_info info;
  388. #if defined(CONFIG_OF_BOARD_SETUP)
  389. int fsl_dcu_fixedfb_setup(void *blob)
  390. {
  391. u64 start, size;
  392. int ret;
  393. start = gd->bd->bi_dram[0].start;
  394. size = gd->bd->bi_dram[0].size - info.screen_size;
  395. /*
  396. * Align size on section size (1 MiB).
  397. */
  398. size &= 0xfff00000;
  399. ret = fdt_fixup_memory_banks(blob, &start, &size, 1);
  400. if (ret) {
  401. eprintf("Cannot setup fb: Error reserving memory\n");
  402. return ret;
  403. }
  404. return 0;
  405. }
  406. #endif
  407. void *video_hw_init(void)
  408. {
  409. static GraphicDevice ctfb;
  410. if (fsl_probe_common(&info, &ctfb.winSizeX, &ctfb.winSizeY) < 0)
  411. return NULL;
  412. ctfb.frameAdrs = (unsigned int)info.screen_base;
  413. ctfb.plnSizeX = ctfb.winSizeX;
  414. ctfb.plnSizeY = ctfb.winSizeY;
  415. ctfb.gdfBytesPP = 4;
  416. ctfb.gdfIndex = GDF_32BIT_X888RGB;
  417. ctfb.memSize = info.screen_size;
  418. return &ctfb;
  419. }
  420. #else /* ifndef CONFIG_DM_VIDEO */
  421. static int fsl_dcu_video_probe(struct udevice *dev)
  422. {
  423. struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
  424. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  425. struct fb_info fbinfo = { 0 };
  426. unsigned int win_x;
  427. unsigned int win_y;
  428. u32 fb_start, fb_end;
  429. int ret = 0;
  430. fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
  431. fb_end = plat->base + plat->size;
  432. fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
  433. fbinfo.screen_base = (char *)fb_start;
  434. fbinfo.screen_size = plat->size;
  435. ret = fsl_probe_common(&fbinfo, &win_x, &win_y);
  436. if (ret < 0)
  437. return ret;
  438. uc_priv->bpix = VIDEO_BPP32;
  439. uc_priv->xsize = win_x;
  440. uc_priv->ysize = win_y;
  441. /* Enable dcache for the frame buffer */
  442. mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
  443. DCACHE_WRITEBACK);
  444. video_set_flush_dcache(dev, true);
  445. return ret;
  446. }
  447. static int fsl_dcu_video_bind(struct udevice *dev)
  448. {
  449. struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
  450. unsigned int win_x;
  451. unsigned int win_y;
  452. unsigned int depth = 0, freq = 0;
  453. const char *options;
  454. int ret = 0;
  455. ret = video_get_video_mode(&win_x, &win_y, &depth, &freq, &options);
  456. if (ret < 0)
  457. return ret;
  458. plat->size = win_x * win_y * 32;
  459. return 0;
  460. }
  461. static const struct udevice_id fsl_dcu_video_ids[] = {
  462. { .compatible = "fsl,vf610-dcu" },
  463. { /* sentinel */ }
  464. };
  465. U_BOOT_DRIVER(fsl_dcu_video) = {
  466. .name = "fsl_dcu_video",
  467. .id = UCLASS_VIDEO,
  468. .of_match = fsl_dcu_video_ids,
  469. .bind = fsl_dcu_video_bind,
  470. .probe = fsl_dcu_video_probe,
  471. .flags = DM_FLAG_PRE_RELOC,
  472. };
  473. #endif /* ifndef CONFIG_DM_VIDEO */