dw_mipi_dsi.c 22 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016, Fuzhou Rockchip Electronics Co., Ltd
  4. * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
  5. * Author(s): Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
  6. * Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
  7. *
  8. * This generic Synopsys DesignWare MIPI DSI host driver is inspired from
  9. * the Linux Kernel driver drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c.
  10. */
  11. #include <common.h>
  12. #include <clk.h>
  13. #include <dsi_host.h>
  14. #include <dm.h>
  15. #include <errno.h>
  16. #include <panel.h>
  17. #include <video.h>
  18. #include <asm/io.h>
  19. #include <asm/arch/gpio.h>
  20. #include <dm/device-internal.h>
  21. #include <dm/device_compat.h>
  22. #include <linux/iopoll.h>
  23. #include <video_bridge.h>
  24. #define HWVER_131 0x31333100 /* IP version 1.31 */
  25. #define DSI_VERSION 0x00
  26. #define VERSION GENMASK(31, 8)
  27. #define DSI_PWR_UP 0x04
  28. #define RESET 0
  29. #define POWERUP BIT(0)
  30. #define DSI_CLKMGR_CFG 0x08
  31. #define TO_CLK_DIVISION(div) (((div) & 0xff) << 8)
  32. #define TX_ESC_CLK_DIVISION(div) ((div) & 0xff)
  33. #define DSI_DPI_VCID 0x0c
  34. #define DPI_VCID(vcid) ((vcid) & 0x3)
  35. #define DSI_DPI_COLOR_CODING 0x10
  36. #define LOOSELY18_EN BIT(8)
  37. #define DPI_COLOR_CODING_16BIT_1 0x0
  38. #define DPI_COLOR_CODING_16BIT_2 0x1
  39. #define DPI_COLOR_CODING_16BIT_3 0x2
  40. #define DPI_COLOR_CODING_18BIT_1 0x3
  41. #define DPI_COLOR_CODING_18BIT_2 0x4
  42. #define DPI_COLOR_CODING_24BIT 0x5
  43. #define DSI_DPI_CFG_POL 0x14
  44. #define COLORM_ACTIVE_LOW BIT(4)
  45. #define SHUTD_ACTIVE_LOW BIT(3)
  46. #define HSYNC_ACTIVE_LOW BIT(2)
  47. #define VSYNC_ACTIVE_LOW BIT(1)
  48. #define DATAEN_ACTIVE_LOW BIT(0)
  49. #define DSI_DPI_LP_CMD_TIM 0x18
  50. #define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16)
  51. #define INVACT_LPCMD_TIME(p) ((p) & 0xff)
  52. #define DSI_DBI_VCID 0x1c
  53. #define DSI_DBI_CFG 0x20
  54. #define DSI_DBI_PARTITIONING_EN 0x24
  55. #define DSI_DBI_CMDSIZE 0x28
  56. #define DSI_PCKHDL_CFG 0x2c
  57. #define CRC_RX_EN BIT(4)
  58. #define ECC_RX_EN BIT(3)
  59. #define BTA_EN BIT(2)
  60. #define EOTP_RX_EN BIT(1)
  61. #define EOTP_TX_EN BIT(0)
  62. #define DSI_GEN_VCID 0x30
  63. #define DSI_MODE_CFG 0x34
  64. #define ENABLE_VIDEO_MODE 0
  65. #define ENABLE_CMD_MODE BIT(0)
  66. #define DSI_VID_MODE_CFG 0x38
  67. #define ENABLE_LOW_POWER (0x3f << 8)
  68. #define ENABLE_LOW_POWER_MASK (0x3f << 8)
  69. #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES 0x0
  70. #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS 0x1
  71. #define VID_MODE_TYPE_BURST 0x2
  72. #define VID_MODE_TYPE_MASK 0x3
  73. #define DSI_VID_PKT_SIZE 0x3c
  74. #define VID_PKT_SIZE(p) ((p) & 0x3fff)
  75. #define DSI_VID_NUM_CHUNKS 0x40
  76. #define VID_NUM_CHUNKS(c) ((c) & 0x1fff)
  77. #define DSI_VID_NULL_SIZE 0x44
  78. #define VID_NULL_SIZE(b) ((b) & 0x1fff)
  79. #define DSI_VID_HSA_TIME 0x48
  80. #define DSI_VID_HBP_TIME 0x4c
  81. #define DSI_VID_HLINE_TIME 0x50
  82. #define DSI_VID_VSA_LINES 0x54
  83. #define DSI_VID_VBP_LINES 0x58
  84. #define DSI_VID_VFP_LINES 0x5c
  85. #define DSI_VID_VACTIVE_LINES 0x60
  86. #define DSI_EDPI_CMD_SIZE 0x64
  87. #define DSI_CMD_MODE_CFG 0x68
  88. #define MAX_RD_PKT_SIZE_LP BIT(24)
  89. #define DCS_LW_TX_LP BIT(19)
  90. #define DCS_SR_0P_TX_LP BIT(18)
  91. #define DCS_SW_1P_TX_LP BIT(17)
  92. #define DCS_SW_0P_TX_LP BIT(16)
  93. #define GEN_LW_TX_LP BIT(14)
  94. #define GEN_SR_2P_TX_LP BIT(13)
  95. #define GEN_SR_1P_TX_LP BIT(12)
  96. #define GEN_SR_0P_TX_LP BIT(11)
  97. #define GEN_SW_2P_TX_LP BIT(10)
  98. #define GEN_SW_1P_TX_LP BIT(9)
  99. #define GEN_SW_0P_TX_LP BIT(8)
  100. #define ACK_RQST_EN BIT(1)
  101. #define TEAR_FX_EN BIT(0)
  102. #define CMD_MODE_ALL_LP (MAX_RD_PKT_SIZE_LP | \
  103. DCS_LW_TX_LP | \
  104. DCS_SR_0P_TX_LP | \
  105. DCS_SW_1P_TX_LP | \
  106. DCS_SW_0P_TX_LP | \
  107. GEN_LW_TX_LP | \
  108. GEN_SR_2P_TX_LP | \
  109. GEN_SR_1P_TX_LP | \
  110. GEN_SR_0P_TX_LP | \
  111. GEN_SW_2P_TX_LP | \
  112. GEN_SW_1P_TX_LP | \
  113. GEN_SW_0P_TX_LP)
  114. #define DSI_GEN_HDR 0x6c
  115. #define DSI_GEN_PLD_DATA 0x70
  116. #define DSI_CMD_PKT_STATUS 0x74
  117. #define GEN_RD_CMD_BUSY BIT(6)
  118. #define GEN_PLD_R_FULL BIT(5)
  119. #define GEN_PLD_R_EMPTY BIT(4)
  120. #define GEN_PLD_W_FULL BIT(3)
  121. #define GEN_PLD_W_EMPTY BIT(2)
  122. #define GEN_CMD_FULL BIT(1)
  123. #define GEN_CMD_EMPTY BIT(0)
  124. #define DSI_TO_CNT_CFG 0x78
  125. #define HSTX_TO_CNT(p) (((p) & 0xffff) << 16)
  126. #define LPRX_TO_CNT(p) ((p) & 0xffff)
  127. #define DSI_HS_RD_TO_CNT 0x7c
  128. #define DSI_LP_RD_TO_CNT 0x80
  129. #define DSI_HS_WR_TO_CNT 0x84
  130. #define DSI_LP_WR_TO_CNT 0x88
  131. #define DSI_BTA_TO_CNT 0x8c
  132. #define DSI_LPCLK_CTRL 0x94
  133. #define AUTO_CLKLANE_CTRL BIT(1)
  134. #define PHY_TXREQUESTCLKHS BIT(0)
  135. #define DSI_PHY_TMR_LPCLK_CFG 0x98
  136. #define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16)
  137. #define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff)
  138. #define DSI_PHY_TMR_CFG 0x9c
  139. #define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24)
  140. #define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16)
  141. #define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff)
  142. #define PHY_HS2LP_TIME_V131(lbcc) (((lbcc) & 0x3ff) << 16)
  143. #define PHY_LP2HS_TIME_V131(lbcc) ((lbcc) & 0x3ff)
  144. #define DSI_PHY_RSTZ 0xa0
  145. #define PHY_DISFORCEPLL 0
  146. #define PHY_ENFORCEPLL BIT(3)
  147. #define PHY_DISABLECLK 0
  148. #define PHY_ENABLECLK BIT(2)
  149. #define PHY_RSTZ 0
  150. #define PHY_UNRSTZ BIT(1)
  151. #define PHY_SHUTDOWNZ 0
  152. #define PHY_UNSHUTDOWNZ BIT(0)
  153. #define DSI_PHY_IF_CFG 0xa4
  154. #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8)
  155. #define N_LANES(n) (((n) - 1) & 0x3)
  156. #define DSI_PHY_ULPS_CTRL 0xa8
  157. #define DSI_PHY_TX_TRIGGERS 0xac
  158. #define DSI_PHY_STATUS 0xb0
  159. #define PHY_STOP_STATE_CLK_LANE BIT(2)
  160. #define PHY_LOCK BIT(0)
  161. #define DSI_PHY_TST_CTRL0 0xb4
  162. #define PHY_TESTCLK BIT(1)
  163. #define PHY_UNTESTCLK 0
  164. #define PHY_TESTCLR BIT(0)
  165. #define PHY_UNTESTCLR 0
  166. #define DSI_PHY_TST_CTRL1 0xb8
  167. #define PHY_TESTEN BIT(16)
  168. #define PHY_UNTESTEN 0
  169. #define PHY_TESTDOUT(n) (((n) & 0xff) << 8)
  170. #define PHY_TESTDIN(n) ((n) & 0xff)
  171. #define DSI_INT_ST0 0xbc
  172. #define DSI_INT_ST1 0xc0
  173. #define DSI_INT_MSK0 0xc4
  174. #define DSI_INT_MSK1 0xc8
  175. #define DSI_PHY_TMR_RD_CFG 0xf4
  176. #define MAX_RD_TIME_V131(lbcc) ((lbcc) & 0x7fff)
  177. #define PHY_STATUS_TIMEOUT_US 10000
  178. #define CMD_PKT_STATUS_TIMEOUT_US 20000
  179. #define MSEC_PER_SEC 1000
  180. struct dw_mipi_dsi {
  181. struct mipi_dsi_host dsi_host;
  182. struct mipi_dsi_device *device;
  183. void __iomem *base;
  184. unsigned int lane_mbps; /* per lane */
  185. u32 channel;
  186. unsigned int max_data_lanes;
  187. const struct mipi_dsi_phy_ops *phy_ops;
  188. };
  189. static int dsi_mode_vrefresh(struct display_timing *timings)
  190. {
  191. int refresh = 0;
  192. unsigned int calc_val;
  193. u32 htotal = timings->hactive.typ + timings->hfront_porch.typ +
  194. timings->hback_porch.typ + timings->hsync_len.typ;
  195. u32 vtotal = timings->vactive.typ + timings->vfront_porch.typ +
  196. timings->vback_porch.typ + timings->vsync_len.typ;
  197. if (htotal > 0 && vtotal > 0) {
  198. calc_val = timings->pixelclock.typ;
  199. calc_val /= htotal;
  200. refresh = (calc_val + vtotal / 2) / vtotal;
  201. }
  202. return refresh;
  203. }
  204. /*
  205. * The controller should generate 2 frames before
  206. * preparing the peripheral.
  207. */
  208. static void dw_mipi_dsi_wait_for_two_frames(struct display_timing *timings)
  209. {
  210. int refresh, two_frames;
  211. refresh = dsi_mode_vrefresh(timings);
  212. two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
  213. mdelay(two_frames);
  214. }
  215. static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
  216. {
  217. return container_of(host, struct dw_mipi_dsi, dsi_host);
  218. }
  219. static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
  220. {
  221. writel(val, dsi->base + reg);
  222. }
  223. static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
  224. {
  225. return readl(dsi->base + reg);
  226. }
  227. static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
  228. struct mipi_dsi_device *device)
  229. {
  230. struct dw_mipi_dsi *dsi = host_to_dsi(host);
  231. if (device->lanes > dsi->max_data_lanes) {
  232. dev_err(device->dev,
  233. "the number of data lanes(%u) is too many\n",
  234. device->lanes);
  235. return -EINVAL;
  236. }
  237. dsi->channel = device->channel;
  238. return 0;
  239. }
  240. static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
  241. const struct mipi_dsi_msg *msg)
  242. {
  243. bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM;
  244. u32 val = 0;
  245. if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
  246. val |= ACK_RQST_EN;
  247. if (lpm)
  248. val |= CMD_MODE_ALL_LP;
  249. dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
  250. dsi_write(dsi, DSI_CMD_MODE_CFG, val);
  251. }
  252. static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
  253. {
  254. int ret;
  255. u32 val, mask;
  256. ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
  257. val, !(val & GEN_CMD_FULL),
  258. CMD_PKT_STATUS_TIMEOUT_US);
  259. if (ret) {
  260. dev_err(dsi->dev, "failed to get available command FIFO\n");
  261. return ret;
  262. }
  263. dsi_write(dsi, DSI_GEN_HDR, hdr_val);
  264. mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
  265. ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
  266. val, (val & mask) == mask,
  267. CMD_PKT_STATUS_TIMEOUT_US);
  268. if (ret) {
  269. dev_err(dsi->dev, "failed to write command FIFO\n");
  270. return ret;
  271. }
  272. return 0;
  273. }
  274. static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi,
  275. const struct mipi_dsi_packet *packet)
  276. {
  277. const u8 *tx_buf = packet->payload;
  278. int len = packet->payload_length, pld_data_bytes = sizeof(u32), ret;
  279. __le32 word;
  280. u32 val;
  281. while (len) {
  282. if (len < pld_data_bytes) {
  283. word = 0;
  284. memcpy(&word, tx_buf, len);
  285. dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
  286. len = 0;
  287. } else {
  288. memcpy(&word, tx_buf, pld_data_bytes);
  289. dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
  290. tx_buf += pld_data_bytes;
  291. len -= pld_data_bytes;
  292. }
  293. ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
  294. val, !(val & GEN_PLD_W_FULL),
  295. CMD_PKT_STATUS_TIMEOUT_US);
  296. if (ret) {
  297. dev_err(dsi->dev,
  298. "failed to get available write payload FIFO\n");
  299. return ret;
  300. }
  301. }
  302. word = 0;
  303. memcpy(&word, packet->header, sizeof(packet->header));
  304. return dw_mipi_dsi_gen_pkt_hdr_write(dsi, le32_to_cpu(word));
  305. }
  306. static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi,
  307. const struct mipi_dsi_msg *msg)
  308. {
  309. int i, j, ret, len = msg->rx_len;
  310. u8 *buf = msg->rx_buf;
  311. u32 val;
  312. /* Wait end of the read operation */
  313. ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
  314. val, !(val & GEN_RD_CMD_BUSY),
  315. CMD_PKT_STATUS_TIMEOUT_US);
  316. if (ret) {
  317. dev_err(dsi->dev, "Timeout during read operation\n");
  318. return ret;
  319. }
  320. for (i = 0; i < len; i += 4) {
  321. /* Read fifo must not be empty before all bytes are read */
  322. ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
  323. val, !(val & GEN_PLD_R_EMPTY),
  324. CMD_PKT_STATUS_TIMEOUT_US);
  325. if (ret) {
  326. dev_err(dsi->dev, "Read payload FIFO is empty\n");
  327. return ret;
  328. }
  329. val = dsi_read(dsi, DSI_GEN_PLD_DATA);
  330. for (j = 0; j < 4 && j + i < len; j++)
  331. buf[i + j] = val >> (8 * j);
  332. }
  333. return ret;
  334. }
  335. static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
  336. const struct mipi_dsi_msg *msg)
  337. {
  338. struct dw_mipi_dsi *dsi = host_to_dsi(host);
  339. struct mipi_dsi_packet packet;
  340. int ret, nb_bytes;
  341. ret = mipi_dsi_create_packet(&packet, msg);
  342. if (ret) {
  343. dev_err(dsi->dev, "failed to create packet: %d\n", ret);
  344. return ret;
  345. }
  346. dw_mipi_message_config(dsi, msg);
  347. ret = dw_mipi_dsi_write(dsi, &packet);
  348. if (ret)
  349. return ret;
  350. if (msg->rx_buf && msg->rx_len) {
  351. ret = dw_mipi_dsi_read(dsi, msg);
  352. if (ret)
  353. return ret;
  354. nb_bytes = msg->rx_len;
  355. } else {
  356. nb_bytes = packet.size;
  357. }
  358. return nb_bytes;
  359. }
  360. static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
  361. .attach = dw_mipi_dsi_host_attach,
  362. .transfer = dw_mipi_dsi_host_transfer,
  363. };
  364. static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
  365. {
  366. struct mipi_dsi_device *device = dsi->device;
  367. u32 val;
  368. /*
  369. * TODO dw drv improvements
  370. * enabling low power is panel-dependent, we should use the
  371. * panel configuration here...
  372. */
  373. val = ENABLE_LOW_POWER;
  374. if (device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
  375. val |= VID_MODE_TYPE_BURST;
  376. else if (device->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
  377. val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
  378. else
  379. val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
  380. dsi_write(dsi, DSI_VID_MODE_CFG, val);
  381. }
  382. static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
  383. unsigned long mode_flags)
  384. {
  385. const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
  386. dsi_write(dsi, DSI_PWR_UP, RESET);
  387. if (mode_flags & MIPI_DSI_MODE_VIDEO) {
  388. dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
  389. dw_mipi_dsi_video_mode_config(dsi);
  390. dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
  391. } else {
  392. dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
  393. }
  394. if (phy_ops->post_set_mode)
  395. phy_ops->post_set_mode(dsi->device, mode_flags);
  396. dsi_write(dsi, DSI_PWR_UP, POWERUP);
  397. }
  398. static void dw_mipi_dsi_init_pll(struct dw_mipi_dsi *dsi)
  399. {
  400. /*
  401. * The maximum permitted escape clock is 20MHz and it is derived from
  402. * lanebyteclk, which is running at "lane_mbps / 8". Thus we want:
  403. *
  404. * (lane_mbps >> 3) / esc_clk_division < 20
  405. * which is:
  406. * (lane_mbps >> 3) / 20 > esc_clk_division
  407. */
  408. u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;
  409. dsi_write(dsi, DSI_PWR_UP, RESET);
  410. /*
  411. * TODO dw drv improvements
  412. * timeout clock division should be computed with the
  413. * high speed transmission counter timeout and byte lane...
  414. */
  415. dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) |
  416. TX_ESC_CLK_DIVISION(esc_clk_division));
  417. }
  418. static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
  419. struct display_timing *timings)
  420. {
  421. struct mipi_dsi_device *device = dsi->device;
  422. u32 val = 0, color = 0;
  423. switch (device->format) {
  424. case MIPI_DSI_FMT_RGB888:
  425. color = DPI_COLOR_CODING_24BIT;
  426. break;
  427. case MIPI_DSI_FMT_RGB666:
  428. color = DPI_COLOR_CODING_18BIT_2 | LOOSELY18_EN;
  429. break;
  430. case MIPI_DSI_FMT_RGB666_PACKED:
  431. color = DPI_COLOR_CODING_18BIT_1;
  432. break;
  433. case MIPI_DSI_FMT_RGB565:
  434. color = DPI_COLOR_CODING_16BIT_1;
  435. break;
  436. }
  437. if (device->mode_flags & DISPLAY_FLAGS_VSYNC_HIGH)
  438. val |= VSYNC_ACTIVE_LOW;
  439. if (device->mode_flags & DISPLAY_FLAGS_HSYNC_HIGH)
  440. val |= HSYNC_ACTIVE_LOW;
  441. dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel));
  442. dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
  443. dsi_write(dsi, DSI_DPI_CFG_POL, val);
  444. /*
  445. * TODO dw drv improvements
  446. * largest packet sizes during hfp or during vsa/vpb/vfp
  447. * should be computed according to byte lane, lane number and only
  448. * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS)
  449. */
  450. dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
  451. | INVACT_LPCMD_TIME(4));
  452. }
  453. static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
  454. {
  455. dsi_write(dsi, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN);
  456. }
  457. static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
  458. struct display_timing *timings)
  459. {
  460. /*
  461. * TODO dw drv improvements
  462. * only burst mode is supported here. For non-burst video modes,
  463. * we should compute DSI_VID_PKT_SIZE, DSI_VCCR.NUMC &
  464. * DSI_VNPCR.NPSIZE... especially because this driver supports
  465. * non-burst video modes, see dw_mipi_dsi_video_mode_config()...
  466. */
  467. dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(timings->hactive.typ));
  468. }
  469. static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
  470. {
  471. const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
  472. /*
  473. * TODO dw drv improvements
  474. * compute high speed transmission counter timeout according
  475. * to the timeout clock division (TO_CLK_DIVISION) and byte lane...
  476. */
  477. dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
  478. /*
  479. * TODO dw drv improvements
  480. * the Bus-Turn-Around Timeout Counter should be computed
  481. * according to byte lane...
  482. */
  483. dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
  484. dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
  485. if (phy_ops->post_set_mode)
  486. phy_ops->post_set_mode(dsi->device, 0);
  487. }
  488. /* Get lane byte clock cycles. */
  489. static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
  490. struct display_timing *timings,
  491. u32 hcomponent)
  492. {
  493. u32 frac, lbcc;
  494. lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
  495. frac = lbcc % (timings->pixelclock.typ / 1000);
  496. lbcc = lbcc / (timings->pixelclock.typ / 1000);
  497. if (frac)
  498. lbcc++;
  499. return lbcc;
  500. }
  501. static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
  502. struct display_timing *timings)
  503. {
  504. u32 htotal, hsa, hbp, lbcc;
  505. htotal = timings->hactive.typ + timings->hfront_porch.typ +
  506. timings->hback_porch.typ + timings->hsync_len.typ;
  507. hsa = timings->hback_porch.typ;
  508. hbp = timings->hsync_len.typ;
  509. /*
  510. * TODO dw drv improvements
  511. * computations below may be improved...
  512. */
  513. lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, timings, htotal);
  514. dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
  515. lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, timings, hsa);
  516. dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
  517. lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, timings, hbp);
  518. dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
  519. }
  520. static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
  521. struct display_timing *timings)
  522. {
  523. u32 vactive, vsa, vfp, vbp;
  524. vactive = timings->vactive.typ;
  525. vsa = timings->vback_porch.typ;
  526. vfp = timings->vfront_porch.typ;
  527. vbp = timings->vsync_len.typ;
  528. dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
  529. dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
  530. dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
  531. dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
  532. }
  533. static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
  534. {
  535. u32 hw_version;
  536. /*
  537. * TODO dw drv improvements
  538. * data & clock lane timers should be computed according to panel
  539. * blankings and to the automatic clock lane control mode...
  540. * note: DSI_PHY_TMR_CFG.MAX_RD_TIME should be in line with
  541. * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP)
  542. */
  543. hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
  544. if (hw_version >= HWVER_131) {
  545. dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME_V131(0x40) |
  546. PHY_LP2HS_TIME_V131(0x40));
  547. dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000));
  548. } else {
  549. dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40) |
  550. PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000));
  551. }
  552. dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
  553. | PHY_CLKLP2HS_TIME(0x40));
  554. }
  555. static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
  556. {
  557. struct mipi_dsi_device *device = dsi->device;
  558. /*
  559. * TODO dw drv improvements
  560. * stop wait time should be the maximum between host dsi
  561. * and panel stop wait times
  562. */
  563. dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
  564. N_LANES(device->lanes));
  565. }
  566. static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
  567. {
  568. /* Clear PHY state */
  569. dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
  570. | PHY_RSTZ | PHY_SHUTDOWNZ);
  571. dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
  572. dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
  573. dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
  574. }
  575. static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
  576. {
  577. u32 val;
  578. int ret;
  579. dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
  580. PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
  581. ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val,
  582. val & PHY_LOCK, PHY_STATUS_TIMEOUT_US);
  583. if (ret)
  584. dev_warn(dsi->dev, "failed to wait phy lock state\n");
  585. ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
  586. val, val & PHY_STOP_STATE_CLK_LANE,
  587. PHY_STATUS_TIMEOUT_US);
  588. if (ret)
  589. dev_warn(dsi->dev, "failed to wait phy clk lane stop state\n");
  590. }
  591. static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
  592. {
  593. dsi_read(dsi, DSI_INT_ST0);
  594. dsi_read(dsi, DSI_INT_ST1);
  595. dsi_write(dsi, DSI_INT_MSK0, 0);
  596. dsi_write(dsi, DSI_INT_MSK1, 0);
  597. }
  598. static void dw_mipi_dsi_bridge_set(struct dw_mipi_dsi *dsi,
  599. struct display_timing *timings)
  600. {
  601. const struct mipi_dsi_phy_ops *phy_ops = dsi->phy_ops;
  602. struct mipi_dsi_device *device = dsi->device;
  603. int ret;
  604. ret = phy_ops->get_lane_mbps(dsi->device, timings, device->lanes,
  605. device->format, &dsi->lane_mbps);
  606. if (ret)
  607. dev_warn(dsi->dev, "Phy get_lane_mbps() failed\n");
  608. dw_mipi_dsi_init_pll(dsi);
  609. dw_mipi_dsi_dpi_config(dsi, timings);
  610. dw_mipi_dsi_packet_handler_config(dsi);
  611. dw_mipi_dsi_video_mode_config(dsi);
  612. dw_mipi_dsi_video_packet_config(dsi, timings);
  613. dw_mipi_dsi_command_mode_config(dsi);
  614. dw_mipi_dsi_line_timer_config(dsi, timings);
  615. dw_mipi_dsi_vertical_timing_config(dsi, timings);
  616. dw_mipi_dsi_dphy_init(dsi);
  617. dw_mipi_dsi_dphy_timing_config(dsi);
  618. dw_mipi_dsi_dphy_interface_config(dsi);
  619. dw_mipi_dsi_clear_err(dsi);
  620. ret = phy_ops->init(dsi->device);
  621. if (ret)
  622. dev_warn(dsi->dev, "Phy init() failed\n");
  623. dw_mipi_dsi_dphy_enable(dsi);
  624. dw_mipi_dsi_wait_for_two_frames(timings);
  625. /* Switch to cmd mode for panel-bridge pre_enable & panel prepare */
  626. dw_mipi_dsi_set_mode(dsi, 0);
  627. }
  628. static int dw_mipi_dsi_init(struct udevice *dev,
  629. struct mipi_dsi_device *device,
  630. struct display_timing *timings,
  631. unsigned int max_data_lanes,
  632. const struct mipi_dsi_phy_ops *phy_ops)
  633. {
  634. struct dw_mipi_dsi *dsi = dev_get_priv(dev);
  635. struct clk clk;
  636. int ret;
  637. if (!phy_ops->init || !phy_ops->get_lane_mbps) {
  638. dev_err(device->dev, "Phy not properly configured\n");
  639. return -ENODEV;
  640. }
  641. dsi->phy_ops = phy_ops;
  642. dsi->max_data_lanes = max_data_lanes;
  643. dsi->device = device;
  644. dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
  645. device->host = &dsi->dsi_host;
  646. dsi->base = (void *)dev_read_addr(device->dev);
  647. if ((fdt_addr_t)dsi->base == FDT_ADDR_T_NONE) {
  648. dev_err(device->dev, "dsi dt register address error\n");
  649. return -EINVAL;
  650. }
  651. ret = clk_get_by_name(device->dev, "px_clk", &clk);
  652. if (ret) {
  653. dev_err(device->dev, "peripheral clock get error %d\n", ret);
  654. return ret;
  655. }
  656. /* get the pixel clock set by the clock framework */
  657. timings->pixelclock.typ = clk_get_rate(&clk);
  658. dw_mipi_dsi_bridge_set(dsi, timings);
  659. return 0;
  660. }
  661. static int dw_mipi_dsi_enable(struct udevice *dev)
  662. {
  663. struct dw_mipi_dsi *dsi = dev_get_priv(dev);
  664. /* Switch to video mode for panel-bridge enable & panel enable */
  665. dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO);
  666. return 0;
  667. }
  668. struct dsi_host_ops dw_mipi_dsi_ops = {
  669. .init = dw_mipi_dsi_init,
  670. .enable = dw_mipi_dsi_enable,
  671. };
  672. static int dw_mipi_dsi_probe(struct udevice *dev)
  673. {
  674. return 0;
  675. }
  676. U_BOOT_DRIVER(dw_mipi_dsi) = {
  677. .name = "dw_mipi_dsi",
  678. .id = UCLASS_DSI_HOST,
  679. .probe = dw_mipi_dsi_probe,
  680. .ops = &dw_mipi_dsi_ops,
  681. .priv_auto_alloc_size = sizeof(struct dw_mipi_dsi),
  682. };
  683. MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
  684. MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
  685. MODULE_AUTHOR("Yannick Fertré <yannick.fertre@st.com>");
  686. MODULE_DESCRIPTION("DW MIPI DSI host controller driver");
  687. MODULE_LICENSE("GPL");
  688. MODULE_ALIAS("platform:dw-mipi-dsi");