da8xx-fb.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Porting to u-boot:
  4. *
  5. * (C) Copyright 2011
  6. * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
  7. *
  8. * Copyright (C) 2008-2009 MontaVista Software Inc.
  9. * Copyright (C) 2008-2009 Texas Instruments Inc
  10. *
  11. * Based on the LCD driver for TI Avalanche processors written by
  12. * Ajay Singh and Shalom Hai.
  13. */
  14. #include <common.h>
  15. #include <malloc.h>
  16. #include <memalign.h>
  17. #include <video_fb.h>
  18. #include <linux/list.h>
  19. #include <linux/fb.h>
  20. #include <linux/errno.h>
  21. #include <asm/io.h>
  22. #include <asm/arch/hardware.h>
  23. #include "videomodes.h"
  24. #include "da8xx-fb.h"
  25. #if !defined(DA8XX_LCD_CNTL_BASE)
  26. #define DA8XX_LCD_CNTL_BASE DAVINCI_LCD_CNTL_BASE
  27. #endif
  28. #define DRIVER_NAME "da8xx_lcdc"
  29. #define LCD_VERSION_1 1
  30. #define LCD_VERSION_2 2
  31. /* LCD Status Register */
  32. #define LCD_END_OF_FRAME1 (1 << 9)
  33. #define LCD_END_OF_FRAME0 (1 << 8)
  34. #define LCD_PL_LOAD_DONE (1 << 6)
  35. #define LCD_FIFO_UNDERFLOW (1 << 5)
  36. #define LCD_SYNC_LOST (1 << 2)
  37. /* LCD DMA Control Register */
  38. #define LCD_DMA_BURST_SIZE(x) ((x) << 4)
  39. #define LCD_DMA_BURST_1 0x0
  40. #define LCD_DMA_BURST_2 0x1
  41. #define LCD_DMA_BURST_4 0x2
  42. #define LCD_DMA_BURST_8 0x3
  43. #define LCD_DMA_BURST_16 0x4
  44. #define LCD_V1_END_OF_FRAME_INT_ENA (1 << 2)
  45. #define LCD_V2_END_OF_FRAME0_INT_ENA (1 << 8)
  46. #define LCD_V2_END_OF_FRAME1_INT_ENA (1 << 9)
  47. #define LCD_DUAL_FRAME_BUFFER_ENABLE (1 << 0)
  48. #define LCD_V2_TFT_24BPP_MODE (1 << 25)
  49. #define LCD_V2_TFT_24BPP_UNPACK (1 << 26)
  50. /* LCD Control Register */
  51. #define LCD_CLK_DIVISOR(x) ((x) << 8)
  52. #define LCD_RASTER_MODE 0x01
  53. /* LCD Raster Control Register */
  54. #define LCD_PALETTE_LOAD_MODE(x) ((x) << 20)
  55. #define PALETTE_AND_DATA 0x00
  56. #define PALETTE_ONLY 0x01
  57. #define DATA_ONLY 0x02
  58. #define LCD_MONO_8BIT_MODE (1 << 9)
  59. #define LCD_RASTER_ORDER (1 << 8)
  60. #define LCD_TFT_MODE (1 << 7)
  61. #define LCD_V1_UNDERFLOW_INT_ENA (1 << 6)
  62. #define LCD_V2_UNDERFLOW_INT_ENA (1 << 5)
  63. #define LCD_V1_PL_INT_ENA (1 << 4)
  64. #define LCD_V2_PL_INT_ENA (1 << 6)
  65. #define LCD_MONOCHROME_MODE (1 << 1)
  66. #define LCD_RASTER_ENABLE (1 << 0)
  67. #define LCD_TFT_ALT_ENABLE (1 << 23)
  68. #define LCD_STN_565_ENABLE (1 << 24)
  69. #define LCD_V2_DMA_CLK_EN (1 << 2)
  70. #define LCD_V2_LIDD_CLK_EN (1 << 1)
  71. #define LCD_V2_CORE_CLK_EN (1 << 0)
  72. #define LCD_V2_LPP_B10 26
  73. #define LCD_V2_TFT_24BPP_MODE (1 << 25)
  74. #define LCD_V2_TFT_24BPP_UNPACK (1 << 26)
  75. /* LCD Raster Timing 2 Register */
  76. #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)
  77. #define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8)
  78. #define LCD_SYNC_CTRL (1 << 25)
  79. #define LCD_SYNC_EDGE (1 << 24)
  80. #define LCD_INVERT_PIXEL_CLOCK (1 << 22)
  81. #define LCD_INVERT_LINE_CLOCK (1 << 21)
  82. #define LCD_INVERT_FRAME_CLOCK (1 << 20)
  83. /* Clock registers available only on Version 2 */
  84. #define LCD_CLK_MAIN_RESET (1 << 3)
  85. /* LCD Block */
  86. struct da8xx_lcd_regs {
  87. u32 revid;
  88. u32 ctrl;
  89. u32 stat;
  90. u32 lidd_ctrl;
  91. u32 lidd_cs0_conf;
  92. u32 lidd_cs0_addr;
  93. u32 lidd_cs0_data;
  94. u32 lidd_cs1_conf;
  95. u32 lidd_cs1_addr;
  96. u32 lidd_cs1_data;
  97. u32 raster_ctrl;
  98. u32 raster_timing_0;
  99. u32 raster_timing_1;
  100. u32 raster_timing_2;
  101. u32 raster_subpanel;
  102. u32 reserved;
  103. u32 dma_ctrl;
  104. u32 dma_frm_buf_base_addr_0;
  105. u32 dma_frm_buf_ceiling_addr_0;
  106. u32 dma_frm_buf_base_addr_1;
  107. u32 dma_frm_buf_ceiling_addr_1;
  108. u32 resv1;
  109. u32 raw_stat;
  110. u32 masked_stat;
  111. u32 int_ena_set;
  112. u32 int_ena_clr;
  113. u32 end_of_int_ind;
  114. /* Clock registers available only on Version 2 */
  115. u32 clk_ena;
  116. u32 clk_reset;
  117. };
  118. #define LCD_NUM_BUFFERS 1
  119. #define WSI_TIMEOUT 50
  120. #define PALETTE_SIZE 256
  121. #define LEFT_MARGIN 64
  122. #define RIGHT_MARGIN 64
  123. #define UPPER_MARGIN 32
  124. #define LOWER_MARGIN 32
  125. #define WAIT_FOR_FRAME_DONE true
  126. #define NO_WAIT_FOR_FRAME_DONE false
  127. #define calc_fbsize() (panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP)
  128. static struct da8xx_lcd_regs *da8xx_fb_reg_base;
  129. DECLARE_GLOBAL_DATA_PTR;
  130. /* graphics setup */
  131. static GraphicDevice gpanel;
  132. static const struct da8xx_panel *lcd_panel;
  133. static struct fb_info *da8xx_fb_info;
  134. static int bits_x_pixel;
  135. static unsigned int lcd_revision;
  136. const struct lcd_ctrl_config *da8xx_lcd_cfg;
  137. static inline unsigned int lcdc_read(u32 *addr)
  138. {
  139. return (unsigned int)readl(addr);
  140. }
  141. static inline void lcdc_write(unsigned int val, u32 *addr)
  142. {
  143. writel(val, addr);
  144. }
  145. struct da8xx_fb_par {
  146. u32 p_palette_base;
  147. unsigned char *v_palette_base;
  148. dma_addr_t vram_phys;
  149. unsigned long vram_size;
  150. void *vram_virt;
  151. unsigned int dma_start;
  152. unsigned int dma_end;
  153. struct clk *lcdc_clk;
  154. int irq;
  155. unsigned short pseudo_palette[16];
  156. unsigned int palette_sz;
  157. unsigned int pxl_clk;
  158. int blank;
  159. int vsync_flag;
  160. int vsync_timeout;
  161. };
  162. /* Variable Screen Information */
  163. static struct fb_var_screeninfo da8xx_fb_var = {
  164. .xoffset = 0,
  165. .yoffset = 0,
  166. .transp = {0, 0, 0},
  167. .nonstd = 0,
  168. .activate = 0,
  169. .height = -1,
  170. .width = -1,
  171. .pixclock = 46666, /* 46us - AUO display */
  172. .accel_flags = 0,
  173. .left_margin = LEFT_MARGIN,
  174. .right_margin = RIGHT_MARGIN,
  175. .upper_margin = UPPER_MARGIN,
  176. .lower_margin = LOWER_MARGIN,
  177. .sync = 0,
  178. .vmode = FB_VMODE_NONINTERLACED
  179. };
  180. static struct fb_fix_screeninfo da8xx_fb_fix = {
  181. .id = "DA8xx FB Drv",
  182. .type = FB_TYPE_PACKED_PIXELS,
  183. .type_aux = 0,
  184. .visual = FB_VISUAL_PSEUDOCOLOR,
  185. .xpanstep = 0,
  186. .ypanstep = 1,
  187. .ywrapstep = 0,
  188. .accel = FB_ACCEL_NONE
  189. };
  190. /* Enable the Raster Engine of the LCD Controller */
  191. static inline void lcd_enable_raster(void)
  192. {
  193. u32 reg;
  194. /* Put LCDC in reset for several cycles */
  195. if (lcd_revision == LCD_VERSION_2)
  196. lcdc_write(LCD_CLK_MAIN_RESET,
  197. &da8xx_fb_reg_base->clk_reset);
  198. udelay(1000);
  199. /* Bring LCDC out of reset */
  200. if (lcd_revision == LCD_VERSION_2)
  201. lcdc_write(0,
  202. &da8xx_fb_reg_base->clk_reset);
  203. udelay(1000);
  204. reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
  205. if (!(reg & LCD_RASTER_ENABLE))
  206. lcdc_write(reg | LCD_RASTER_ENABLE,
  207. &da8xx_fb_reg_base->raster_ctrl);
  208. }
  209. /* Disable the Raster Engine of the LCD Controller */
  210. static inline void lcd_disable_raster(bool wait_for_frame_done)
  211. {
  212. u32 reg;
  213. u32 loop_cnt = 0;
  214. u32 stat;
  215. u32 i = 0;
  216. if (wait_for_frame_done)
  217. loop_cnt = 5000;
  218. reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
  219. if (reg & LCD_RASTER_ENABLE)
  220. lcdc_write(reg & ~LCD_RASTER_ENABLE,
  221. &da8xx_fb_reg_base->raster_ctrl);
  222. /* Wait for the current frame to complete */
  223. do {
  224. if (lcd_revision == LCD_VERSION_1)
  225. stat = lcdc_read(&da8xx_fb_reg_base->stat);
  226. else
  227. stat = lcdc_read(&da8xx_fb_reg_base->raw_stat);
  228. mdelay(1);
  229. } while (!(stat & 0x01) && (i++ < loop_cnt));
  230. if (lcd_revision == LCD_VERSION_1)
  231. lcdc_write(stat, &da8xx_fb_reg_base->stat);
  232. else
  233. lcdc_write(stat, &da8xx_fb_reg_base->raw_stat);
  234. if ((loop_cnt != 0) && (i >= loop_cnt)) {
  235. printf("LCD Controller timed out\n");
  236. return;
  237. }
  238. }
  239. static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
  240. {
  241. u32 start;
  242. u32 end;
  243. u32 reg_ras;
  244. u32 reg_dma;
  245. u32 reg_int;
  246. /* init reg to clear PLM (loading mode) fields */
  247. reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
  248. reg_ras &= ~(3 << 20);
  249. reg_dma = lcdc_read(&da8xx_fb_reg_base->dma_ctrl);
  250. if (load_mode == LOAD_DATA) {
  251. start = par->dma_start;
  252. end = par->dma_end;
  253. reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
  254. if (lcd_revision == LCD_VERSION_1) {
  255. reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;
  256. } else {
  257. reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) |
  258. LCD_V2_END_OF_FRAME0_INT_ENA |
  259. LCD_V2_END_OF_FRAME1_INT_ENA |
  260. LCD_V2_UNDERFLOW_INT_ENA | LCD_SYNC_LOST;
  261. lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set);
  262. }
  263. #if (LCD_NUM_BUFFERS == 2)
  264. reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
  265. lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
  266. lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
  267. lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
  268. lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
  269. #else
  270. reg_dma &= ~LCD_DUAL_FRAME_BUFFER_ENABLE;
  271. lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
  272. lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
  273. lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
  274. lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
  275. #endif
  276. } else if (load_mode == LOAD_PALETTE) {
  277. start = par->p_palette_base;
  278. end = start + par->palette_sz - 1;
  279. reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
  280. if (lcd_revision == LCD_VERSION_1) {
  281. reg_ras |= LCD_V1_PL_INT_ENA;
  282. } else {
  283. reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) |
  284. LCD_V2_PL_INT_ENA;
  285. lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set);
  286. }
  287. lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
  288. lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
  289. }
  290. lcdc_write(reg_dma, &da8xx_fb_reg_base->dma_ctrl);
  291. lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
  292. /*
  293. * The Raster enable bit must be set after all other control fields are
  294. * set.
  295. */
  296. lcd_enable_raster();
  297. }
  298. /* Configure the Burst Size of DMA */
  299. static int lcd_cfg_dma(int burst_size)
  300. {
  301. u32 reg;
  302. reg = lcdc_read(&da8xx_fb_reg_base->dma_ctrl) & 0x00000001;
  303. switch (burst_size) {
  304. case 1:
  305. reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
  306. break;
  307. case 2:
  308. reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
  309. break;
  310. case 4:
  311. reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
  312. break;
  313. case 8:
  314. reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
  315. break;
  316. case 16:
  317. reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
  318. break;
  319. default:
  320. return -EINVAL;
  321. }
  322. lcdc_write(reg, &da8xx_fb_reg_base->dma_ctrl);
  323. return 0;
  324. }
  325. static void lcd_cfg_ac_bias(int period, int transitions_per_int)
  326. {
  327. u32 reg;
  328. /* Set the AC Bias Period and Number of Transitions per Interrupt */
  329. reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2) & 0xFFF00000;
  330. reg |= LCD_AC_BIAS_FREQUENCY(period) |
  331. LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
  332. lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
  333. }
  334. static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
  335. int front_porch)
  336. {
  337. u32 reg;
  338. reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0) & 0xf;
  339. reg |= ((back_porch & 0xff) << 24)
  340. | ((front_porch & 0xff) << 16)
  341. | ((pulse_width & 0x3f) << 10);
  342. lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
  343. }
  344. static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
  345. int front_porch)
  346. {
  347. u32 reg;
  348. reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1) & 0x3ff;
  349. reg |= ((back_porch & 0xff) << 24)
  350. | ((front_porch & 0xff) << 16)
  351. | ((pulse_width & 0x3f) << 10);
  352. lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
  353. }
  354. static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
  355. {
  356. u32 reg;
  357. u32 reg_int;
  358. reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(LCD_TFT_MODE |
  359. LCD_MONO_8BIT_MODE |
  360. LCD_MONOCHROME_MODE);
  361. switch (cfg->p_disp_panel->panel_shade) {
  362. case MONOCHROME:
  363. reg |= LCD_MONOCHROME_MODE;
  364. if (cfg->mono_8bit_mode)
  365. reg |= LCD_MONO_8BIT_MODE;
  366. break;
  367. case COLOR_ACTIVE:
  368. reg |= LCD_TFT_MODE;
  369. if (cfg->tft_alt_mode)
  370. reg |= LCD_TFT_ALT_ENABLE;
  371. break;
  372. case COLOR_PASSIVE:
  373. if (cfg->stn_565_mode)
  374. reg |= LCD_STN_565_ENABLE;
  375. break;
  376. default:
  377. return -EINVAL;
  378. }
  379. /* enable additional interrupts here */
  380. if (lcd_revision == LCD_VERSION_1) {
  381. reg |= LCD_V1_UNDERFLOW_INT_ENA;
  382. } else {
  383. reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) |
  384. LCD_V2_UNDERFLOW_INT_ENA;
  385. lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set);
  386. }
  387. lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
  388. reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2);
  389. if (cfg->sync_ctrl)
  390. reg |= LCD_SYNC_CTRL;
  391. else
  392. reg &= ~LCD_SYNC_CTRL;
  393. if (cfg->sync_edge)
  394. reg |= LCD_SYNC_EDGE;
  395. else
  396. reg &= ~LCD_SYNC_EDGE;
  397. if (cfg->invert_line_clock)
  398. reg |= LCD_INVERT_LINE_CLOCK;
  399. else
  400. reg &= ~LCD_INVERT_LINE_CLOCK;
  401. if (cfg->invert_frm_clock)
  402. reg |= LCD_INVERT_FRAME_CLOCK;
  403. else
  404. reg &= ~LCD_INVERT_FRAME_CLOCK;
  405. lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
  406. return 0;
  407. }
  408. static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
  409. u32 bpp, u32 raster_order)
  410. {
  411. u32 reg;
  412. /* Set the Panel Width */
  413. /* Pixels per line = (PPL + 1)*16 */
  414. if (lcd_revision == LCD_VERSION_1) {
  415. /*
  416. * 0x3F in bits 4..9 gives max horizontal resolution = 1024
  417. * pixels
  418. */
  419. width &= 0x3f0;
  420. } else {
  421. /*
  422. * 0x7F in bits 4..10 gives max horizontal resolution = 2048
  423. * pixels.
  424. */
  425. width &= 0x7f0;
  426. }
  427. reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0);
  428. reg &= 0xfffffc00;
  429. if (lcd_revision == LCD_VERSION_1) {
  430. reg |= ((width >> 4) - 1) << 4;
  431. } else {
  432. width = (width >> 4) - 1;
  433. reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
  434. }
  435. lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
  436. /* Set the Panel Height */
  437. /* Set bits 9:0 of Lines Per Pixel */
  438. reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1);
  439. reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
  440. lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
  441. /* Set bit 10 of Lines Per Pixel */
  442. if (lcd_revision == LCD_VERSION_2) {
  443. reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2);
  444. reg |= ((height - 1) & 0x400) << 16;
  445. lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
  446. }
  447. /* Set the Raster Order of the Frame Buffer */
  448. reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(1 << 8);
  449. if (raster_order)
  450. reg |= LCD_RASTER_ORDER;
  451. if (bpp == 24)
  452. reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE);
  453. else if (bpp == 32)
  454. reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE
  455. | LCD_V2_TFT_24BPP_UNPACK);
  456. lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
  457. switch (bpp) {
  458. case 1:
  459. case 2:
  460. case 4:
  461. case 16:
  462. case 24:
  463. case 32:
  464. par->palette_sz = 16 * 2;
  465. break;
  466. case 8:
  467. par->palette_sz = 256 * 2;
  468. break;
  469. default:
  470. return -EINVAL;
  471. }
  472. return 0;
  473. }
  474. static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
  475. unsigned blue, unsigned transp,
  476. struct fb_info *info)
  477. {
  478. struct da8xx_fb_par *par = info->par;
  479. unsigned short *palette = (unsigned short *) par->v_palette_base;
  480. u_short pal;
  481. int update_hw = 0;
  482. if (regno > 255)
  483. return 1;
  484. if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
  485. return 1;
  486. if (info->var.bits_per_pixel == 8) {
  487. red >>= 4;
  488. green >>= 8;
  489. blue >>= 12;
  490. pal = (red & 0x0f00);
  491. pal |= (green & 0x00f0);
  492. pal |= (blue & 0x000f);
  493. if (palette[regno] != pal) {
  494. update_hw = 1;
  495. palette[regno] = pal;
  496. }
  497. } else if ((info->var.bits_per_pixel == 16) && regno < 16) {
  498. red >>= (16 - info->var.red.length);
  499. red <<= info->var.red.offset;
  500. green >>= (16 - info->var.green.length);
  501. green <<= info->var.green.offset;
  502. blue >>= (16 - info->var.blue.length);
  503. blue <<= info->var.blue.offset;
  504. par->pseudo_palette[regno] = red | green | blue;
  505. if (palette[0] != 0x4000) {
  506. update_hw = 1;
  507. palette[0] = 0x4000;
  508. }
  509. } else if (((info->var.bits_per_pixel == 32) && regno < 32) ||
  510. ((info->var.bits_per_pixel == 24) && regno < 24)) {
  511. red >>= (24 - info->var.red.length);
  512. red <<= info->var.red.offset;
  513. green >>= (24 - info->var.green.length);
  514. green <<= info->var.green.offset;
  515. blue >>= (24 - info->var.blue.length);
  516. blue <<= info->var.blue.offset;
  517. par->pseudo_palette[regno] = red | green | blue;
  518. if (palette[0] != 0x4000) {
  519. update_hw = 1;
  520. palette[0] = 0x4000;
  521. }
  522. }
  523. /* Update the palette in the h/w as needed. */
  524. if (update_hw)
  525. lcd_blit(LOAD_PALETTE, par);
  526. return 0;
  527. }
  528. static void lcd_reset(struct da8xx_fb_par *par)
  529. {
  530. /* Disable the Raster if previously Enabled */
  531. lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
  532. /* DMA has to be disabled */
  533. lcdc_write(0, &da8xx_fb_reg_base->dma_ctrl);
  534. lcdc_write(0, &da8xx_fb_reg_base->raster_ctrl);
  535. if (lcd_revision == LCD_VERSION_2) {
  536. lcdc_write(0, &da8xx_fb_reg_base->int_ena_set);
  537. /* Write 1 to reset */
  538. lcdc_write(LCD_CLK_MAIN_RESET, &da8xx_fb_reg_base->clk_reset);
  539. lcdc_write(0, &da8xx_fb_reg_base->clk_reset);
  540. }
  541. }
  542. static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
  543. {
  544. unsigned int lcd_clk, div;
  545. /* Get clock from sysclk2 */
  546. lcd_clk = clk_get(2);
  547. div = lcd_clk / par->pxl_clk;
  548. debug("LCD Clock: %d Divider: %d PixClk: %d\n",
  549. lcd_clk, div, par->pxl_clk);
  550. /* Configure the LCD clock divisor. */
  551. lcdc_write(LCD_CLK_DIVISOR(div) |
  552. (LCD_RASTER_MODE & 0x1), &da8xx_fb_reg_base->ctrl);
  553. if (lcd_revision == LCD_VERSION_2)
  554. lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
  555. LCD_V2_CORE_CLK_EN,
  556. &da8xx_fb_reg_base->clk_ena);
  557. }
  558. static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
  559. const struct da8xx_panel *panel)
  560. {
  561. u32 bpp;
  562. int ret = 0;
  563. lcd_reset(par);
  564. /* Calculate the divider */
  565. lcd_calc_clk_divider(par);
  566. if (panel->invert_pxl_clk)
  567. lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) |
  568. LCD_INVERT_PIXEL_CLOCK),
  569. &da8xx_fb_reg_base->raster_timing_2);
  570. else
  571. lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) &
  572. ~LCD_INVERT_PIXEL_CLOCK),
  573. &da8xx_fb_reg_base->raster_timing_2);
  574. /* Configure the DMA burst size. */
  575. ret = lcd_cfg_dma(cfg->dma_burst_sz);
  576. if (ret < 0)
  577. return ret;
  578. /* Configure the AC bias properties. */
  579. lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
  580. /* Configure the vertical and horizontal sync properties. */
  581. lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
  582. lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
  583. /* Configure for display */
  584. ret = lcd_cfg_display(cfg);
  585. if (ret < 0)
  586. return ret;
  587. if ((QVGA != cfg->p_disp_panel->panel_type) &&
  588. (WVGA != cfg->p_disp_panel->panel_type))
  589. return -EINVAL;
  590. if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
  591. cfg->bpp >= cfg->p_disp_panel->min_bpp)
  592. bpp = cfg->bpp;
  593. else
  594. bpp = cfg->p_disp_panel->max_bpp;
  595. if (bpp == 12)
  596. bpp = 16;
  597. ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
  598. (unsigned int)panel->height, bpp,
  599. cfg->raster_order);
  600. if (ret < 0)
  601. return ret;
  602. /* Configure FDD */
  603. lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & 0xfff00fff) |
  604. (cfg->fdd << 12), &da8xx_fb_reg_base->raster_ctrl);
  605. return 0;
  606. }
  607. static void lcdc_dma_start(void)
  608. {
  609. struct da8xx_fb_par *par = da8xx_fb_info->par;
  610. lcdc_write(par->dma_start,
  611. &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
  612. lcdc_write(par->dma_end,
  613. &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
  614. lcdc_write(0,
  615. &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
  616. lcdc_write(0,
  617. &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
  618. }
  619. static u32 lcdc_irq_handler_rev01(void)
  620. {
  621. struct da8xx_fb_par *par = da8xx_fb_info->par;
  622. u32 stat = lcdc_read(&da8xx_fb_reg_base->stat);
  623. u32 reg_ras;
  624. if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
  625. debug("LCD_SYNC_LOST\n");
  626. lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
  627. lcdc_write(stat, &da8xx_fb_reg_base->stat);
  628. lcd_enable_raster();
  629. return LCD_SYNC_LOST;
  630. } else if (stat & LCD_PL_LOAD_DONE) {
  631. debug("LCD_PL_LOAD_DONE\n");
  632. /*
  633. * Must disable raster before changing state of any control bit.
  634. * And also must be disabled before clearing the PL loading
  635. * interrupt via the following write to the status register. If
  636. * this is done after then one gets multiple PL done interrupts.
  637. */
  638. lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
  639. lcdc_write(stat, &da8xx_fb_reg_base->stat);
  640. /* Disable PL completion interrupt */
  641. reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
  642. reg_ras &= ~LCD_V1_PL_INT_ENA;
  643. lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
  644. /* Setup and start data loading mode */
  645. lcd_blit(LOAD_DATA, par);
  646. return LCD_PL_LOAD_DONE;
  647. } else {
  648. lcdc_write(stat, &da8xx_fb_reg_base->stat);
  649. if (stat & LCD_END_OF_FRAME0)
  650. debug("LCD_END_OF_FRAME0\n");
  651. lcdc_write(par->dma_start,
  652. &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
  653. lcdc_write(par->dma_end,
  654. &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
  655. par->vsync_flag = 1;
  656. return LCD_END_OF_FRAME0;
  657. }
  658. return stat;
  659. }
  660. static u32 lcdc_irq_handler_rev02(void)
  661. {
  662. struct da8xx_fb_par *par = da8xx_fb_info->par;
  663. u32 stat = lcdc_read(&da8xx_fb_reg_base->masked_stat);
  664. u32 reg_int;
  665. if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
  666. debug("LCD_SYNC_LOST\n");
  667. lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
  668. lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
  669. lcd_enable_raster();
  670. lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
  671. return LCD_SYNC_LOST;
  672. } else if (stat & LCD_PL_LOAD_DONE) {
  673. debug("LCD_PL_LOAD_DONE\n");
  674. /*
  675. * Must disable raster before changing state of any control bit.
  676. * And also must be disabled before clearing the PL loading
  677. * interrupt via the following write to the status register. If
  678. * this is done after then one gets multiple PL done interrupts.
  679. */
  680. lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
  681. lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
  682. /* Disable PL completion interrupt */
  683. reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_clr) |
  684. (LCD_V2_PL_INT_ENA);
  685. lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_clr);
  686. /* Setup and start data loading mode */
  687. lcd_blit(LOAD_DATA, par);
  688. lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
  689. return LCD_PL_LOAD_DONE;
  690. } else {
  691. lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
  692. if (stat & LCD_END_OF_FRAME0)
  693. debug("LCD_END_OF_FRAME0\n");
  694. lcdc_write(par->dma_start,
  695. &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
  696. lcdc_write(par->dma_end,
  697. &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
  698. par->vsync_flag = 1;
  699. lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
  700. return LCD_END_OF_FRAME0;
  701. }
  702. lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
  703. return stat;
  704. }
  705. static u32 lcdc_irq_handler(void)
  706. {
  707. if (lcd_revision == LCD_VERSION_1)
  708. return lcdc_irq_handler_rev01();
  709. else
  710. return lcdc_irq_handler_rev02();
  711. }
  712. static u32 wait_for_event(u32 event)
  713. {
  714. u32 timeout = 50000;
  715. u32 ret;
  716. do {
  717. ret = lcdc_irq_handler();
  718. udelay(1000);
  719. --timeout;
  720. } while (!(ret & event) && timeout);
  721. if (!(ret & event)) {
  722. printf("%s: event %d not hit\n", __func__, event);
  723. return -1;
  724. }
  725. return 0;
  726. }
  727. void *video_hw_init(void)
  728. {
  729. struct da8xx_fb_par *par;
  730. u32 size;
  731. u32 rev;
  732. char *p;
  733. if (!lcd_panel) {
  734. printf("Display not initialized\n");
  735. return NULL;
  736. }
  737. gpanel.winSizeX = lcd_panel->width;
  738. gpanel.winSizeY = lcd_panel->height;
  739. gpanel.plnSizeX = lcd_panel->width;
  740. gpanel.plnSizeY = lcd_panel->height;
  741. switch (bits_x_pixel) {
  742. case 32:
  743. gpanel.gdfBytesPP = 4;
  744. gpanel.gdfIndex = GDF_32BIT_X888RGB;
  745. break;
  746. case 24:
  747. gpanel.gdfBytesPP = 4;
  748. gpanel.gdfIndex = GDF_32BIT_X888RGB;
  749. break;
  750. case 16:
  751. gpanel.gdfBytesPP = 2;
  752. gpanel.gdfIndex = GDF_16BIT_565RGB;
  753. break;
  754. default:
  755. gpanel.gdfBytesPP = 1;
  756. gpanel.gdfIndex = GDF__8BIT_INDEX;
  757. break;
  758. }
  759. da8xx_fb_reg_base = (struct da8xx_lcd_regs *)DA8XX_LCD_CNTL_BASE;
  760. /* Determine LCD IP Version */
  761. rev = lcdc_read(&da8xx_fb_reg_base->revid);
  762. switch (rev) {
  763. case 0x4C100102:
  764. lcd_revision = LCD_VERSION_1;
  765. break;
  766. case 0x4F200800:
  767. case 0x4F201000:
  768. lcd_revision = LCD_VERSION_2;
  769. break;
  770. default:
  771. printf("Unknown PID Reg value 0x%x, defaulting to LCD revision 1\n",
  772. rev);
  773. lcd_revision = LCD_VERSION_1;
  774. break;
  775. }
  776. debug("rev: 0x%x Resolution: %dx%d %d\n", rev,
  777. gpanel.winSizeX,
  778. gpanel.winSizeY,
  779. da8xx_lcd_cfg->bpp);
  780. size = sizeof(struct fb_info) + sizeof(struct da8xx_fb_par);
  781. da8xx_fb_info = malloc_cache_aligned(size);
  782. debug("da8xx_fb_info at %x\n", (unsigned int)da8xx_fb_info);
  783. if (!da8xx_fb_info) {
  784. printf("Memory allocation failed for fb_info\n");
  785. return NULL;
  786. }
  787. memset(da8xx_fb_info, 0, size);
  788. p = (char *)da8xx_fb_info;
  789. da8xx_fb_info->par = p + sizeof(struct fb_info);
  790. debug("da8xx_par at %x\n", (unsigned int)da8xx_fb_info->par);
  791. par = da8xx_fb_info->par;
  792. par->pxl_clk = lcd_panel->pxl_clk;
  793. if (lcd_init(par, da8xx_lcd_cfg, lcd_panel) < 0) {
  794. printf("lcd_init failed\n");
  795. goto err_release_fb;
  796. }
  797. /* allocate frame buffer */
  798. par->vram_size = lcd_panel->width * lcd_panel->height *
  799. da8xx_lcd_cfg->bpp;
  800. par->vram_size = par->vram_size * LCD_NUM_BUFFERS / 8;
  801. par->vram_virt = malloc_cache_aligned(par->vram_size);
  802. par->vram_phys = (dma_addr_t) par->vram_virt;
  803. debug("Requesting 0x%x bytes for framebuffer at 0x%x\n",
  804. (unsigned int)par->vram_size,
  805. (unsigned int)par->vram_virt);
  806. if (!par->vram_virt) {
  807. printf("GLCD: malloc for frame buffer failed\n");
  808. goto err_release_fb;
  809. }
  810. gd->fb_base = (int)par->vram_virt;
  811. gpanel.frameAdrs = (unsigned int)par->vram_virt;
  812. da8xx_fb_info->screen_base = (char *) par->vram_virt;
  813. da8xx_fb_fix.smem_start = gpanel.frameAdrs;
  814. da8xx_fb_fix.smem_len = par->vram_size;
  815. da8xx_fb_fix.line_length = (lcd_panel->width * da8xx_lcd_cfg->bpp) / 8;
  816. par->dma_start = par->vram_phys;
  817. par->dma_end = par->dma_start + lcd_panel->height *
  818. da8xx_fb_fix.line_length - 1;
  819. /* allocate palette buffer */
  820. par->v_palette_base = malloc_cache_aligned(PALETTE_SIZE);
  821. if (!par->v_palette_base) {
  822. printf("GLCD: malloc for palette buffer failed\n");
  823. goto err_release_fb_mem;
  824. }
  825. memset(par->v_palette_base, 0, PALETTE_SIZE);
  826. par->p_palette_base = (unsigned int)par->v_palette_base;
  827. /* Initialize par */
  828. da8xx_fb_info->var.bits_per_pixel = da8xx_lcd_cfg->bpp;
  829. da8xx_fb_var.xres = lcd_panel->width;
  830. da8xx_fb_var.xres_virtual = lcd_panel->width;
  831. da8xx_fb_var.yres = lcd_panel->height;
  832. da8xx_fb_var.yres_virtual = lcd_panel->height * LCD_NUM_BUFFERS;
  833. da8xx_fb_var.grayscale =
  834. da8xx_lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
  835. da8xx_fb_var.bits_per_pixel = da8xx_lcd_cfg->bpp;
  836. da8xx_fb_var.hsync_len = lcd_panel->hsw;
  837. da8xx_fb_var.vsync_len = lcd_panel->vsw;
  838. /* Initialize fbinfo */
  839. da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
  840. da8xx_fb_info->fix = da8xx_fb_fix;
  841. da8xx_fb_info->var = da8xx_fb_var;
  842. da8xx_fb_info->pseudo_palette = par->pseudo_palette;
  843. da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
  844. FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
  845. /* Clear interrupt */
  846. memset((void *)par->vram_virt, 0, par->vram_size);
  847. lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
  848. if (lcd_revision == LCD_VERSION_1)
  849. lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat);
  850. else
  851. lcdc_write(0xFFFF, &da8xx_fb_reg_base->masked_stat);
  852. debug("Palette at 0x%x size %d\n", par->p_palette_base,
  853. par->palette_sz);
  854. lcdc_dma_start();
  855. /* Load a default palette */
  856. fb_setcolreg(0, 0, 0, 0, 0xffff, da8xx_fb_info);
  857. /* Check that the palette is loaded */
  858. wait_for_event(LCD_PL_LOAD_DONE);
  859. /* Wait until DMA is working */
  860. wait_for_event(LCD_END_OF_FRAME0);
  861. return (void *)&gpanel;
  862. err_release_fb_mem:
  863. free(par->vram_virt);
  864. err_release_fb:
  865. free(da8xx_fb_info);
  866. return NULL;
  867. }
  868. void da8xx_video_init(const struct da8xx_panel *panel,
  869. const struct lcd_ctrl_config *lcd_cfg, int bits_pixel)
  870. {
  871. lcd_panel = panel;
  872. da8xx_lcd_cfg = lcd_cfg;
  873. bits_x_pixel = bits_pixel;
  874. }