broadwell_igd.c 19 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * From coreboot src/soc/intel/broadwell/igd.c
  4. *
  5. * Copyright (C) 2016 Google, Inc
  6. */
  7. #include <common.h>
  8. #include <bios_emul.h>
  9. #include <dm.h>
  10. #include <init.h>
  11. #include <vbe.h>
  12. #include <video.h>
  13. #include <asm/cpu.h>
  14. #include <asm/intel_regs.h>
  15. #include <asm/io.h>
  16. #include <asm/mtrr.h>
  17. #include <asm/arch/cpu.h>
  18. #include <asm/arch/iomap.h>
  19. #include <asm/arch/pch.h>
  20. #include "i915_reg.h"
  21. struct broadwell_igd_priv {
  22. u8 *regs;
  23. };
  24. struct broadwell_igd_plat {
  25. u32 dp_hotplug[3];
  26. int port_select;
  27. int power_up_delay;
  28. int power_backlight_on_delay;
  29. int power_down_delay;
  30. int power_backlight_off_delay;
  31. int power_cycle_delay;
  32. int cpu_backlight;
  33. int pch_backlight;
  34. int cdclk;
  35. int pre_graphics_delay;
  36. };
  37. #define GT_RETRY 1000
  38. #define GT_CDCLK_337 0
  39. #define GT_CDCLK_450 1
  40. #define GT_CDCLK_540 2
  41. #define GT_CDCLK_675 3
  42. u32 board_map_oprom_vendev(u32 vendev)
  43. {
  44. return SA_IGD_OPROM_VENDEV;
  45. }
  46. static int poll32(u8 *addr, uint mask, uint value)
  47. {
  48. ulong start;
  49. start = get_timer(0);
  50. debug("%s: addr %p = %x\n", __func__, addr, readl(addr));
  51. while ((readl(addr) & mask) != value) {
  52. if (get_timer(start) > GT_RETRY) {
  53. debug("poll32: timeout: %x\n", readl(addr));
  54. return -ETIMEDOUT;
  55. }
  56. }
  57. return 0;
  58. }
  59. static int haswell_early_init(struct udevice *dev)
  60. {
  61. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  62. u8 *regs = priv->regs;
  63. int ret;
  64. /* Enable Force Wake */
  65. writel(0x00000020, regs + 0xa180);
  66. writel(0x00010001, regs + 0xa188);
  67. ret = poll32(regs + 0x130044, 1, 1);
  68. if (ret)
  69. goto err;
  70. /* Enable Counters */
  71. setbits_le32(regs + 0xa248, 0x00000016);
  72. /* GFXPAUSE settings */
  73. writel(0x00070020, regs + 0xa000);
  74. /* ECO Settings */
  75. clrsetbits_le32(regs + 0xa180, ~0xff3fffff, 0x15000000);
  76. /* Enable DOP Clock Gating */
  77. writel(0x000003fd, regs + 0x9424);
  78. /* Enable Unit Level Clock Gating */
  79. writel(0x00000080, regs + 0x9400);
  80. writel(0x40401000, regs + 0x9404);
  81. writel(0x00000000, regs + 0x9408);
  82. writel(0x02000001, regs + 0x940c);
  83. /*
  84. * RC6 Settings
  85. */
  86. /* Wake Rate Limits */
  87. setbits_le32(regs + 0xa090, 0x00000000);
  88. setbits_le32(regs + 0xa098, 0x03e80000);
  89. setbits_le32(regs + 0xa09c, 0x00280000);
  90. setbits_le32(regs + 0xa0a8, 0x0001e848);
  91. setbits_le32(regs + 0xa0ac, 0x00000019);
  92. /* Render/Video/Blitter Idle Max Count */
  93. writel(0x0000000a, regs + 0x02054);
  94. writel(0x0000000a, regs + 0x12054);
  95. writel(0x0000000a, regs + 0x22054);
  96. writel(0x0000000a, regs + 0x1a054);
  97. /* RC Sleep / RCx Thresholds */
  98. setbits_le32(regs + 0xa0b0, 0x00000000);
  99. setbits_le32(regs + 0xa0b4, 0x000003e8);
  100. setbits_le32(regs + 0xa0b8, 0x0000c350);
  101. /* RP Settings */
  102. setbits_le32(regs + 0xa010, 0x000f4240);
  103. setbits_le32(regs + 0xa014, 0x12060000);
  104. setbits_le32(regs + 0xa02c, 0x0000e808);
  105. setbits_le32(regs + 0xa030, 0x0003bd08);
  106. setbits_le32(regs + 0xa068, 0x000101d0);
  107. setbits_le32(regs + 0xa06c, 0x00055730);
  108. setbits_le32(regs + 0xa070, 0x0000000a);
  109. /* RP Control */
  110. writel(0x00000b92, regs + 0xa024);
  111. /* HW RC6 Control */
  112. writel(0x88040000, regs + 0xa090);
  113. /* Video Frequency Request */
  114. writel(0x08000000, regs + 0xa00c);
  115. /* Set RC6 VIDs */
  116. ret = poll32(regs + 0x138124, (1 << 31), 0);
  117. if (ret)
  118. goto err;
  119. writel(0, regs + 0x138128);
  120. writel(0x80000004, regs + 0x138124);
  121. ret = poll32(regs + 0x138124, (1 << 31), 0);
  122. if (ret)
  123. goto err;
  124. /* Enable PM Interrupts */
  125. writel(0x03000076, regs + 0x4402c);
  126. /* Enable RC6 in idle */
  127. writel(0x00040000, regs + 0xa094);
  128. return 0;
  129. err:
  130. debug("%s: ret=%d\n", __func__, ret);
  131. return ret;
  132. };
  133. static int haswell_late_init(struct udevice *dev)
  134. {
  135. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  136. u8 *regs = priv->regs;
  137. int ret;
  138. /* Lock settings */
  139. setbits_le32(regs + 0x0a248, (1 << 31));
  140. setbits_le32(regs + 0x0a004, (1 << 4));
  141. setbits_le32(regs + 0x0a080, (1 << 2));
  142. setbits_le32(regs + 0x0a180, (1 << 31));
  143. /* Disable Force Wake */
  144. writel(0x00010000, regs + 0xa188);
  145. ret = poll32(regs + 0x130044, 1, 0);
  146. if (ret)
  147. goto err;
  148. writel(0x00000001, regs + 0xa188);
  149. /* Enable power well for DP and Audio */
  150. setbits_le32(regs + 0x45400, (1 << 31));
  151. ret = poll32(regs + 0x45400, 1 << 30, 1 << 30);
  152. if (ret)
  153. goto err;
  154. return 0;
  155. err:
  156. debug("%s: ret=%d\n", __func__, ret);
  157. return ret;
  158. };
  159. static int broadwell_early_init(struct udevice *dev)
  160. {
  161. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  162. u8 *regs = priv->regs;
  163. int ret;
  164. /* Enable Force Wake */
  165. writel(0x00010001, regs + 0xa188);
  166. ret = poll32(regs + 0x130044, 1, 1);
  167. if (ret)
  168. goto err;
  169. /* Enable push bus metric control and shift */
  170. writel(0x00000004, regs + 0xa248);
  171. writel(0x000000ff, regs + 0xa250);
  172. writel(0x00000010, regs + 0xa25c);
  173. /* GFXPAUSE settings (set based on stepping) */
  174. /* ECO Settings */
  175. writel(0x45200000, regs + 0xa180);
  176. /* Enable DOP Clock Gating */
  177. writel(0x000000fd, regs + 0x9424);
  178. /* Enable Unit Level Clock Gating */
  179. writel(0x00000000, regs + 0x9400);
  180. writel(0x40401000, regs + 0x9404);
  181. writel(0x00000000, regs + 0x9408);
  182. writel(0x02000001, regs + 0x940c);
  183. writel(0x0000000a, regs + 0x1a054);
  184. /* Video Frequency Request */
  185. writel(0x08000000, regs + 0xa00c);
  186. writel(0x00000009, regs + 0x138158);
  187. writel(0x0000000d, regs + 0x13815c);
  188. /*
  189. * RC6 Settings
  190. */
  191. /* Wake Rate Limits */
  192. clrsetbits_le32(regs + 0x0a090, ~0, 0);
  193. setbits_le32(regs + 0x0a098, 0x03e80000);
  194. setbits_le32(regs + 0x0a09c, 0x00280000);
  195. setbits_le32(regs + 0x0a0a8, 0x0001e848);
  196. setbits_le32(regs + 0x0a0ac, 0x00000019);
  197. /* Render/Video/Blitter Idle Max Count */
  198. writel(0x0000000a, regs + 0x02054);
  199. writel(0x0000000a, regs + 0x12054);
  200. writel(0x0000000a, regs + 0x22054);
  201. /* RC Sleep / RCx Thresholds */
  202. setbits_le32(regs + 0x0a0b0, 0x00000000);
  203. setbits_le32(regs + 0x0a0b8, 0x00000271);
  204. /* RP Settings */
  205. setbits_le32(regs + 0x0a010, 0x000f4240);
  206. setbits_le32(regs + 0x0a014, 0x12060000);
  207. setbits_le32(regs + 0x0a02c, 0x0000e808);
  208. setbits_le32(regs + 0x0a030, 0x0003bd08);
  209. setbits_le32(regs + 0x0a068, 0x000101d0);
  210. setbits_le32(regs + 0x0a06c, 0x00055730);
  211. setbits_le32(regs + 0x0a070, 0x0000000a);
  212. setbits_le32(regs + 0x0a168, 0x00000006);
  213. /* RP Control */
  214. writel(0x00000b92, regs + 0xa024);
  215. /* HW RC6 Control */
  216. writel(0x90040000, regs + 0xa090);
  217. /* Set RC6 VIDs */
  218. ret = poll32(regs + 0x138124, (1 << 31), 0);
  219. if (ret)
  220. goto err;
  221. writel(0, regs + 0x138128);
  222. writel(0x80000004, regs + 0x138124);
  223. ret = poll32(regs + 0x138124, (1 << 31), 0);
  224. if (ret)
  225. goto err;
  226. /* Enable PM Interrupts */
  227. writel(0x03000076, regs + 0x4402c);
  228. /* Enable RC6 in idle */
  229. writel(0x00040000, regs + 0xa094);
  230. return 0;
  231. err:
  232. debug("%s: ret=%d\n", __func__, ret);
  233. return ret;
  234. }
  235. static int broadwell_late_init(struct udevice *dev)
  236. {
  237. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  238. u8 *regs = priv->regs;
  239. int ret;
  240. /* Lock settings */
  241. setbits_le32(regs + 0x0a248, 1 << 31);
  242. setbits_le32(regs + 0x0a000, 1 << 18);
  243. setbits_le32(regs + 0x0a180, 1 << 31);
  244. /* Disable Force Wake */
  245. writel(0x00010000, regs + 0xa188);
  246. ret = poll32(regs + 0x130044, 1, 0);
  247. if (ret)
  248. goto err;
  249. /* Enable power well for DP and Audio */
  250. setbits_le32(regs + 0x45400, 1 << 31);
  251. ret = poll32(regs + 0x45400, 1 << 30, 1 << 30);
  252. if (ret)
  253. goto err;
  254. return 0;
  255. err:
  256. debug("%s: ret=%d\n", __func__, ret);
  257. return ret;
  258. };
  259. static unsigned long gtt_read(struct broadwell_igd_priv *priv,
  260. unsigned long reg)
  261. {
  262. return readl(priv->regs + reg);
  263. }
  264. static void gtt_write(struct broadwell_igd_priv *priv, unsigned long reg,
  265. unsigned long data)
  266. {
  267. writel(data, priv->regs + reg);
  268. }
  269. static inline void gtt_clrsetbits(struct broadwell_igd_priv *priv, u32 reg,
  270. u32 bic, u32 or)
  271. {
  272. clrsetbits_le32(priv->regs + reg, bic, or);
  273. }
  274. static int gtt_poll(struct broadwell_igd_priv *priv, u32 reg, u32 mask,
  275. u32 value)
  276. {
  277. unsigned try = GT_RETRY;
  278. u32 data;
  279. while (try--) {
  280. data = gtt_read(priv, reg);
  281. if ((data & mask) == value)
  282. return 0;
  283. udelay(10);
  284. }
  285. debug("GT init timeout\n");
  286. return -ETIMEDOUT;
  287. }
  288. static void igd_setup_panel(struct udevice *dev)
  289. {
  290. struct broadwell_igd_plat *plat = dev_get_platdata(dev);
  291. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  292. u32 reg32;
  293. /* Setup Digital Port Hotplug */
  294. reg32 = (plat->dp_hotplug[0] & 0x7) << 2;
  295. reg32 |= (plat->dp_hotplug[1] & 0x7) << 10;
  296. reg32 |= (plat->dp_hotplug[2] & 0x7) << 18;
  297. gtt_write(priv, PCH_PORT_HOTPLUG, reg32);
  298. /* Setup Panel Power On Delays */
  299. reg32 = (plat->port_select & 0x3) << 30;
  300. reg32 |= (plat->power_up_delay & 0x1fff) << 16;
  301. reg32 |= (plat->power_backlight_on_delay & 0x1fff);
  302. gtt_write(priv, PCH_PP_ON_DELAYS, reg32);
  303. /* Setup Panel Power Off Delays */
  304. reg32 = (plat->power_down_delay & 0x1fff) << 16;
  305. reg32 |= (plat->power_backlight_off_delay & 0x1fff);
  306. gtt_write(priv, PCH_PP_OFF_DELAYS, reg32);
  307. /* Setup Panel Power Cycle Delay */
  308. if (plat->power_cycle_delay) {
  309. reg32 = gtt_read(priv, PCH_PP_DIVISOR);
  310. reg32 &= ~0xff;
  311. reg32 |= plat->power_cycle_delay & 0xff;
  312. gtt_write(priv, PCH_PP_DIVISOR, reg32);
  313. }
  314. /* Enable Backlight if needed */
  315. if (plat->cpu_backlight) {
  316. gtt_write(priv, BLC_PWM_CPU_CTL2, BLC_PWM2_ENABLE);
  317. gtt_write(priv, BLC_PWM_CPU_CTL, plat->cpu_backlight);
  318. }
  319. if (plat->pch_backlight) {
  320. gtt_write(priv, BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE);
  321. gtt_write(priv, BLC_PWM_PCH_CTL2, plat->pch_backlight);
  322. }
  323. }
  324. static int igd_cdclk_init_haswell(struct udevice *dev)
  325. {
  326. struct broadwell_igd_plat *plat = dev_get_platdata(dev);
  327. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  328. int cdclk = plat->cdclk;
  329. u16 devid;
  330. int gpu_is_ulx = 0;
  331. u32 dpdiv, lpcll;
  332. int ret;
  333. dm_pci_read_config16(dev, PCI_DEVICE_ID, &devid);
  334. /* Check for ULX GT1 or GT2 */
  335. if (devid == 0x0a0e || devid == 0x0a1e)
  336. gpu_is_ulx = 1;
  337. /* 675MHz is not supported on haswell */
  338. if (cdclk == GT_CDCLK_675)
  339. cdclk = GT_CDCLK_337;
  340. /* If CD clock is fixed or ULT then set to 450MHz */
  341. if ((gtt_read(priv, 0x42014) & 0x1000000) || cpu_is_ult())
  342. cdclk = GT_CDCLK_450;
  343. /* 540MHz is not supported on ULX */
  344. if (gpu_is_ulx && cdclk == GT_CDCLK_540)
  345. cdclk = GT_CDCLK_337;
  346. /* 337.5MHz is not supported on non-ULT/ULX */
  347. if (!gpu_is_ulx && !cpu_is_ult() && cdclk == GT_CDCLK_337)
  348. cdclk = GT_CDCLK_450;
  349. /* Set variables based on CD Clock setting */
  350. switch (cdclk) {
  351. case GT_CDCLK_337:
  352. dpdiv = 169;
  353. lpcll = (1 << 26);
  354. break;
  355. case GT_CDCLK_450:
  356. dpdiv = 225;
  357. lpcll = 0;
  358. break;
  359. case GT_CDCLK_540:
  360. dpdiv = 270;
  361. lpcll = (1 << 26);
  362. break;
  363. default:
  364. ret = -EDOM;
  365. goto err;
  366. }
  367. /* Set LPCLL_CTL CD Clock Frequency Select */
  368. gtt_clrsetbits(priv, 0x130040, ~0xf3ffffff, lpcll);
  369. /* ULX: Inform power controller of selected frequency */
  370. if (gpu_is_ulx) {
  371. if (cdclk == GT_CDCLK_450)
  372. gtt_write(priv, 0x138128, 0x00000000); /* 450MHz */
  373. else
  374. gtt_write(priv, 0x138128, 0x00000001); /* 337.5MHz */
  375. gtt_write(priv, 0x13812c, 0x00000000);
  376. gtt_write(priv, 0x138124, 0x80000017);
  377. }
  378. /* Set CPU DP AUX 2X bit clock dividers */
  379. gtt_clrsetbits(priv, 0x64010, ~0xfffff800, dpdiv);
  380. gtt_clrsetbits(priv, 0x64810, ~0xfffff800, dpdiv);
  381. return 0;
  382. err:
  383. debug("%s: ret=%d\n", __func__, ret);
  384. return ret;
  385. }
  386. static int igd_cdclk_init_broadwell(struct udevice *dev)
  387. {
  388. struct broadwell_igd_plat *plat = dev_get_platdata(dev);
  389. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  390. int cdclk = plat->cdclk;
  391. u32 dpdiv, lpcll, pwctl, cdset;
  392. int ret;
  393. /* Inform power controller of upcoming frequency change */
  394. gtt_write(priv, 0x138128, 0);
  395. gtt_write(priv, 0x13812c, 0);
  396. gtt_write(priv, 0x138124, 0x80000018);
  397. /* Poll GT driver mailbox for run/busy clear */
  398. if (gtt_poll(priv, 0x138124, 1 << 31, 0 << 31))
  399. cdclk = GT_CDCLK_450;
  400. if (gtt_read(priv, 0x42014) & 0x1000000) {
  401. /* If CD clock is fixed then set to 450MHz */
  402. cdclk = GT_CDCLK_450;
  403. } else {
  404. /* Program CD clock to highest supported freq */
  405. if (cpu_is_ult())
  406. cdclk = GT_CDCLK_540;
  407. else
  408. cdclk = GT_CDCLK_675;
  409. }
  410. /* CD clock frequency 675MHz not supported on ULT */
  411. if (cpu_is_ult() && cdclk == GT_CDCLK_675)
  412. cdclk = GT_CDCLK_540;
  413. /* Set variables based on CD Clock setting */
  414. switch (cdclk) {
  415. case GT_CDCLK_337:
  416. cdset = 337;
  417. lpcll = (1 << 27);
  418. pwctl = 2;
  419. dpdiv = 169;
  420. break;
  421. case GT_CDCLK_450:
  422. cdset = 449;
  423. lpcll = 0;
  424. pwctl = 0;
  425. dpdiv = 225;
  426. break;
  427. case GT_CDCLK_540:
  428. cdset = 539;
  429. lpcll = (1 << 26);
  430. pwctl = 1;
  431. dpdiv = 270;
  432. break;
  433. case GT_CDCLK_675:
  434. cdset = 674;
  435. lpcll = (1 << 26) | (1 << 27);
  436. pwctl = 3;
  437. dpdiv = 338;
  438. break;
  439. default:
  440. ret = -EDOM;
  441. goto err;
  442. }
  443. debug("%s: frequency = %d\n", __func__, cdclk);
  444. /* Set LPCLL_CTL CD Clock Frequency Select */
  445. gtt_clrsetbits(priv, 0x130040, ~0xf3ffffff, lpcll);
  446. /* Inform power controller of selected frequency */
  447. gtt_write(priv, 0x138128, pwctl);
  448. gtt_write(priv, 0x13812c, 0);
  449. gtt_write(priv, 0x138124, 0x80000017);
  450. /* Program CD Clock Frequency */
  451. gtt_clrsetbits(priv, 0x46200, ~0xfffffc00, cdset);
  452. /* Set CPU DP AUX 2X bit clock dividers */
  453. gtt_clrsetbits(priv, 0x64010, ~0xfffff800, dpdiv);
  454. gtt_clrsetbits(priv, 0x64810, ~0xfffff800, dpdiv);
  455. return 0;
  456. err:
  457. debug("%s: ret=%d\n", __func__, ret);
  458. return ret;
  459. }
  460. u8 systemagent_revision(struct udevice *bus)
  461. {
  462. ulong val;
  463. pci_bus_read_config(bus, PCI_BDF(0, 0, 0), PCI_REVISION_ID, &val,
  464. PCI_SIZE_32);
  465. return val;
  466. }
  467. static int igd_pre_init(struct udevice *dev, bool is_broadwell)
  468. {
  469. struct broadwell_igd_plat *plat = dev_get_platdata(dev);
  470. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  471. u32 rp1_gfx_freq;
  472. int ret;
  473. mdelay(plat->pre_graphics_delay);
  474. /* Early init steps */
  475. if (is_broadwell) {
  476. ret = broadwell_early_init(dev);
  477. if (ret)
  478. goto err;
  479. /* Set GFXPAUSE based on stepping */
  480. if (cpu_get_stepping() <= (CPUID_BROADWELL_E0 & 0xf) &&
  481. systemagent_revision(pci_get_controller(dev)) <= 9) {
  482. gtt_write(priv, 0xa000, 0x300ff);
  483. } else {
  484. gtt_write(priv, 0xa000, 0x30020);
  485. }
  486. } else {
  487. ret = haswell_early_init(dev);
  488. if (ret)
  489. goto err;
  490. }
  491. /* Set RP1 graphics frequency */
  492. rp1_gfx_freq = (readl(MCHBAR_REG(0x5998)) >> 8) & 0xff;
  493. gtt_write(priv, 0xa008, rp1_gfx_freq << 24);
  494. /* Post VBIOS panel setup */
  495. igd_setup_panel(dev);
  496. return 0;
  497. err:
  498. debug("%s: ret=%d\n", __func__, ret);
  499. return ret;
  500. }
  501. static int igd_post_init(struct udevice *dev, bool is_broadwell)
  502. {
  503. int ret;
  504. /* Late init steps */
  505. if (is_broadwell) {
  506. ret = igd_cdclk_init_broadwell(dev);
  507. if (ret)
  508. return ret;
  509. ret = broadwell_late_init(dev);
  510. if (ret)
  511. return ret;
  512. } else {
  513. igd_cdclk_init_haswell(dev);
  514. ret = haswell_late_init(dev);
  515. if (ret)
  516. return ret;
  517. }
  518. return 0;
  519. }
  520. static int broadwell_igd_int15_handler(void)
  521. {
  522. int res = 0;
  523. debug("%s: INT15 function %04x!\n", __func__, M.x86.R_AX);
  524. switch (M.x86.R_AX) {
  525. case 0x5f35:
  526. /*
  527. * Boot Display Device Hook:
  528. * bit 0 = CRT
  529. * bit 1 = TV (eDP)
  530. * bit 2 = EFP
  531. * bit 3 = LFP
  532. * bit 4 = CRT2
  533. * bit 5 = TV2 (eDP)
  534. * bit 6 = EFP2
  535. * bit 7 = LFP2
  536. */
  537. M.x86.R_AX = 0x005f;
  538. M.x86.R_CX = 0x0000; /* Use video bios default */
  539. res = 1;
  540. break;
  541. default:
  542. debug("Unknown INT15 function %04x!\n", M.x86.R_AX);
  543. break;
  544. }
  545. return res;
  546. }
  547. static int broadwell_igd_probe(struct udevice *dev)
  548. {
  549. struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
  550. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  551. bool is_broadwell;
  552. int ret;
  553. if (!ll_boot_init()) {
  554. /*
  555. * If we are running from EFI or coreboot, this driver can't
  556. * work.
  557. */
  558. printf("Not available (previous bootloader prevents it)\n");
  559. return -EPERM;
  560. }
  561. is_broadwell = cpu_get_family_model() == BROADWELL_FAMILY_ULT;
  562. bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display");
  563. debug("%s: is_broadwell=%d\n", __func__, is_broadwell);
  564. ret = igd_pre_init(dev, is_broadwell);
  565. if (!ret) {
  566. ret = vbe_setup_video(dev, broadwell_igd_int15_handler);
  567. if (ret)
  568. debug("failed to run video BIOS: %d\n", ret);
  569. }
  570. if (!ret)
  571. ret = igd_post_init(dev, is_broadwell);
  572. bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
  573. if (ret)
  574. return ret;
  575. /* Use write-combining for the graphics memory, 256MB */
  576. ret = mtrr_add_request(MTRR_TYPE_WRCOMB, plat->base, 256 << 20);
  577. if (!ret)
  578. ret = mtrr_commit(true);
  579. if (ret && ret != -ENOSYS) {
  580. printf("Failed to add MTRR: Display will be slow (err %d)\n",
  581. ret);
  582. }
  583. debug("fb=%lx, size %x, display size=%d %d %d\n", plat->base,
  584. plat->size, uc_priv->xsize, uc_priv->ysize, uc_priv->bpix);
  585. return 0;
  586. }
  587. static int broadwell_igd_ofdata_to_platdata(struct udevice *dev)
  588. {
  589. struct broadwell_igd_plat *plat = dev_get_platdata(dev);
  590. struct broadwell_igd_priv *priv = dev_get_priv(dev);
  591. int node = dev_of_offset(dev);
  592. const void *blob = gd->fdt_blob;
  593. if (fdtdec_get_int_array(blob, node, "intel,dp-hotplug",
  594. plat->dp_hotplug,
  595. ARRAY_SIZE(plat->dp_hotplug)))
  596. return -EINVAL;
  597. plat->port_select = fdtdec_get_int(blob, node, "intel,port-select", 0);
  598. plat->power_cycle_delay = fdtdec_get_int(blob, node,
  599. "intel,power-cycle-delay", 0);
  600. plat->power_up_delay = fdtdec_get_int(blob, node,
  601. "intel,power-up-delay", 0);
  602. plat->power_down_delay = fdtdec_get_int(blob, node,
  603. "intel,power-down-delay", 0);
  604. plat->power_backlight_on_delay = fdtdec_get_int(blob, node,
  605. "intel,power-backlight-on-delay", 0);
  606. plat->power_backlight_off_delay = fdtdec_get_int(blob, node,
  607. "intel,power-backlight-off-delay", 0);
  608. plat->cpu_backlight = fdtdec_get_int(blob, node,
  609. "intel,cpu-backlight", 0);
  610. plat->pch_backlight = fdtdec_get_int(blob, node,
  611. "intel,pch-backlight", 0);
  612. plat->pre_graphics_delay = fdtdec_get_int(blob, node,
  613. "intel,pre-graphics-delay", 0);
  614. priv->regs = (u8 *)dm_pci_read_bar32(dev, 0);
  615. debug("%s: regs at %p\n", __func__, priv->regs);
  616. debug("dp_hotplug %d %d %d\n", plat->dp_hotplug[0], plat->dp_hotplug[1],
  617. plat->dp_hotplug[2]);
  618. debug("port_select = %d\n", plat->port_select);
  619. debug("power_up_delay = %d\n", plat->power_up_delay);
  620. debug("power_backlight_on_delay = %d\n",
  621. plat->power_backlight_on_delay);
  622. debug("power_down_delay = %d\n", plat->power_down_delay);
  623. debug("power_backlight_off_delay = %d\n",
  624. plat->power_backlight_off_delay);
  625. debug("power_cycle_delay = %d\n", plat->power_cycle_delay);
  626. debug("cpu_backlight = %x\n", plat->cpu_backlight);
  627. debug("pch_backlight = %x\n", plat->pch_backlight);
  628. debug("cdclk = %d\n", plat->cdclk);
  629. debug("pre_graphics_delay = %d\n", plat->pre_graphics_delay);
  630. return 0;
  631. }
  632. static const struct video_ops broadwell_igd_ops = {
  633. };
  634. static const struct udevice_id broadwell_igd_ids[] = {
  635. { .compatible = "intel,broadwell-igd" },
  636. { }
  637. };
  638. U_BOOT_DRIVER(broadwell_igd) = {
  639. .name = "broadwell_igd",
  640. .id = UCLASS_VIDEO,
  641. .of_match = broadwell_igd_ids,
  642. .ops = &broadwell_igd_ops,
  643. .ofdata_to_platdata = broadwell_igd_ofdata_to_platdata,
  644. .probe = broadwell_igd_probe,
  645. .priv_auto_alloc_size = sizeof(struct broadwell_igd_priv),
  646. .platdata_auto_alloc_size = sizeof(struct broadwell_igd_plat),
  647. };