atmel_lcdfb.c 8.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Driver for AT91/AT32 LCD Controller
  4. *
  5. * Copyright (C) 2007 Atmel Corporation
  6. */
  7. #include <common.h>
  8. #include <atmel_lcd.h>
  9. #include <dm.h>
  10. #include <fdtdec.h>
  11. #include <video.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/gpio.h>
  14. #include <asm/arch/clk.h>
  15. #include <lcd.h>
  16. #include <bmp_layout.h>
  17. #include <atmel_lcdc.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. #ifdef CONFIG_DM_VIDEO
  20. enum {
  21. /* Maximum LCD size we support */
  22. LCD_MAX_WIDTH = 1366,
  23. LCD_MAX_HEIGHT = 768,
  24. LCD_MAX_LOG2_BPP = VIDEO_BPP16,
  25. };
  26. #endif
  27. struct atmel_fb_priv {
  28. struct display_timing timing;
  29. };
  30. /* configurable parameters */
  31. #define ATMEL_LCDC_CVAL_DEFAULT 0xc8
  32. #define ATMEL_LCDC_DMA_BURST_LEN 8
  33. #ifndef ATMEL_LCDC_GUARD_TIME
  34. #define ATMEL_LCDC_GUARD_TIME 1
  35. #endif
  36. #if defined(CONFIG_AT91SAM9263)
  37. #define ATMEL_LCDC_FIFO_SIZE 2048
  38. #else
  39. #define ATMEL_LCDC_FIFO_SIZE 512
  40. #endif
  41. #define lcdc_readl(mmio, reg) __raw_readl((mmio)+(reg))
  42. #define lcdc_writel(mmio, reg, val) __raw_writel((val), (mmio)+(reg))
  43. #ifndef CONFIG_DM_VIDEO
  44. ushort *configuration_get_cmap(void)
  45. {
  46. return (ushort *)(panel_info.mmio + ATMEL_LCDC_LUT(0));
  47. }
  48. #if defined(CONFIG_BMP_16BPP) && defined(CONFIG_ATMEL_LCD_BGR555)
  49. void fb_put_word(uchar **fb, uchar **from)
  50. {
  51. *(*fb)++ = (((*from)[0] & 0x1f) << 2) | ((*from)[1] & 0x03);
  52. *(*fb)++ = ((*from)[0] & 0xe0) | (((*from)[1] & 0x7c) >> 2);
  53. *from += 2;
  54. }
  55. #endif
  56. #ifdef CONFIG_LCD_LOGO
  57. #include <bmp_logo.h>
  58. void lcd_logo_set_cmap(void)
  59. {
  60. int i;
  61. uint lut_entry;
  62. ushort colreg;
  63. uint *cmap = (uint *)configuration_get_cmap();
  64. for (i = 0; i < BMP_LOGO_COLORS; ++i) {
  65. colreg = bmp_logo_palette[i];
  66. #ifdef CONFIG_ATMEL_LCD_BGR555
  67. lut_entry = ((colreg & 0x000F) << 11) |
  68. ((colreg & 0x00F0) << 2) |
  69. ((colreg & 0x0F00) >> 7);
  70. #else
  71. lut_entry = ((colreg & 0x000F) << 1) |
  72. ((colreg & 0x00F0) << 3) |
  73. ((colreg & 0x0F00) << 4);
  74. #endif
  75. *(cmap + BMP_LOGO_OFFSET) = lut_entry;
  76. cmap++;
  77. }
  78. }
  79. #endif
  80. void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
  81. {
  82. #if defined(CONFIG_ATMEL_LCD_BGR555)
  83. lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
  84. (red >> 3) | ((green & 0xf8) << 2) | ((blue & 0xf8) << 7));
  85. #else
  86. lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
  87. (blue >> 3) | ((green & 0xfc) << 3) | ((red & 0xf8) << 8));
  88. #endif
  89. }
  90. void lcd_set_cmap(struct bmp_image *bmp, unsigned colors)
  91. {
  92. int i;
  93. for (i = 0; i < colors; ++i) {
  94. struct bmp_color_table_entry cte = bmp->color_table[i];
  95. lcd_setcolreg(i, cte.red, cte.green, cte.blue);
  96. }
  97. }
  98. #endif
  99. static void atmel_fb_init(ulong addr, struct display_timing *timing, int bpix,
  100. bool tft, bool cont_pol_low, ulong lcdbase)
  101. {
  102. unsigned long value;
  103. void *reg = (void *)addr;
  104. /* Turn off the LCD controller and the DMA controller */
  105. lcdc_writel(reg, ATMEL_LCDC_PWRCON,
  106. ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET);
  107. /* Wait for the LCDC core to become idle */
  108. while (lcdc_readl(reg, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
  109. udelay(10);
  110. lcdc_writel(reg, ATMEL_LCDC_DMACON, 0);
  111. /* Reset LCDC DMA */
  112. lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMARST);
  113. /* ...set frame size and burst length = 8 words (?) */
  114. value = (timing->hactive.typ * timing->vactive.typ *
  115. (1 << bpix)) / 32;
  116. value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
  117. lcdc_writel(reg, ATMEL_LCDC_DMAFRMCFG, value);
  118. /* Set pixel clock */
  119. value = get_lcdc_clk_rate(0) / timing->pixelclock.typ;
  120. if (get_lcdc_clk_rate(0) % timing->pixelclock.typ)
  121. value++;
  122. value = (value / 2) - 1;
  123. if (!value) {
  124. lcdc_writel(reg, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
  125. } else
  126. lcdc_writel(reg, ATMEL_LCDC_LCDCON1,
  127. value << ATMEL_LCDC_CLKVAL_OFFSET);
  128. /* Initialize control register 2 */
  129. value = ATMEL_LCDC_MEMOR_LITTLE | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE;
  130. if (tft)
  131. value |= ATMEL_LCDC_DISTYPE_TFT;
  132. if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH))
  133. value |= ATMEL_LCDC_INVLINE_INVERTED;
  134. if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH))
  135. value |= ATMEL_LCDC_INVFRAME_INVERTED;
  136. value |= bpix << 5;
  137. lcdc_writel(reg, ATMEL_LCDC_LCDCON2, value);
  138. /* Vertical timing */
  139. value = (timing->vsync_len.typ - 1) << ATMEL_LCDC_VPW_OFFSET;
  140. value |= timing->vback_porch.typ << ATMEL_LCDC_VBP_OFFSET;
  141. value |= timing->vfront_porch.typ;
  142. /* Magic! (Datasheet says "Bit 31 must be written to 1") */
  143. value |= 1U << 31;
  144. lcdc_writel(reg, ATMEL_LCDC_TIM1, value);
  145. /* Horizontal timing */
  146. value = (timing->hfront_porch.typ - 1) << ATMEL_LCDC_HFP_OFFSET;
  147. value |= (timing->hsync_len.typ - 1) << ATMEL_LCDC_HPW_OFFSET;
  148. value |= (timing->hback_porch.typ - 1);
  149. lcdc_writel(reg, ATMEL_LCDC_TIM2, value);
  150. /* Display size */
  151. value = (timing->hactive.typ - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
  152. value |= timing->vactive.typ - 1;
  153. lcdc_writel(reg, ATMEL_LCDC_LCDFRMCFG, value);
  154. /* FIFO Threshold: Use formula from data sheet */
  155. value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
  156. lcdc_writel(reg, ATMEL_LCDC_FIFO, value);
  157. /* Toggle LCD_MODE every frame */
  158. lcdc_writel(reg, ATMEL_LCDC_MVAL, 0);
  159. /* Disable all interrupts */
  160. lcdc_writel(reg, ATMEL_LCDC_IDR, ~0UL);
  161. /* Set contrast */
  162. value = ATMEL_LCDC_PS_DIV8 |
  163. ATMEL_LCDC_ENA_PWMENABLE;
  164. if (!cont_pol_low)
  165. value |= ATMEL_LCDC_POL_POSITIVE;
  166. lcdc_writel(reg, ATMEL_LCDC_CONTRAST_CTR, value);
  167. lcdc_writel(reg, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
  168. /* Set framebuffer DMA base address and pixel offset */
  169. lcdc_writel(reg, ATMEL_LCDC_DMABADDR1, lcdbase);
  170. lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMAEN);
  171. lcdc_writel(reg, ATMEL_LCDC_PWRCON,
  172. (ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR);
  173. }
  174. #ifndef CONFIG_DM_VIDEO
  175. void lcd_ctrl_init(void *lcdbase)
  176. {
  177. struct display_timing timing;
  178. timing.flags = 0;
  179. if (!(panel_info.vl_sync & ATMEL_LCDC_INVLINE_INVERTED))
  180. timing.flags |= DISPLAY_FLAGS_HSYNC_HIGH;
  181. if (!(panel_info.vl_sync & ATMEL_LCDC_INVFRAME_INVERTED))
  182. timing.flags |= DISPLAY_FLAGS_VSYNC_LOW;
  183. timing.pixelclock.typ = panel_info.vl_clk;
  184. timing.hactive.typ = panel_info.vl_col;
  185. timing.hfront_porch.typ = panel_info.vl_right_margin;
  186. timing.hback_porch.typ = panel_info.vl_left_margin;
  187. timing.hsync_len.typ = panel_info.vl_hsync_len;
  188. timing.vactive.typ = panel_info.vl_row;
  189. timing.vfront_porch.typ = panel_info.vl_clk;
  190. timing.vback_porch.typ = panel_info.vl_clk;
  191. timing.vsync_len.typ = panel_info.vl_clk;
  192. atmel_fb_init(panel_info.mmio, &timing, panel_info.vl_bpix,
  193. panel_info.vl_tft, panel_info.vl_cont_pol_low,
  194. (ulong)lcdbase);
  195. }
  196. ulong calc_fbsize(void)
  197. {
  198. return ((panel_info.vl_col * panel_info.vl_row *
  199. NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE;
  200. }
  201. #endif
  202. #ifdef CONFIG_DM_VIDEO
  203. static int atmel_fb_lcd_probe(struct udevice *dev)
  204. {
  205. struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
  206. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  207. struct atmel_fb_priv *priv = dev_get_priv(dev);
  208. struct display_timing *timing = &priv->timing;
  209. /*
  210. * For now some values are hard-coded. We could use the device tree
  211. * bindings in simple-framebuffer.txt to specify the format/bpp and
  212. * some Atmel-specific binding for tft and cont_pol_low.
  213. */
  214. atmel_fb_init(ATMEL_BASE_LCDC, timing, VIDEO_BPP16, true, false,
  215. uc_plat->base);
  216. uc_priv->xsize = timing->hactive.typ;
  217. uc_priv->ysize = timing->vactive.typ;
  218. uc_priv->bpix = VIDEO_BPP16;
  219. video_set_flush_dcache(dev, true);
  220. debug("LCD frame buffer at %lx, size %x, %dx%d pixels\n", uc_plat->base,
  221. uc_plat->size, uc_priv->xsize, uc_priv->ysize);
  222. return 0;
  223. }
  224. static int atmel_fb_ofdata_to_platdata(struct udevice *dev)
  225. {
  226. struct atmel_lcd_platdata *plat = dev_get_platdata(dev);
  227. struct atmel_fb_priv *priv = dev_get_priv(dev);
  228. struct display_timing *timing = &priv->timing;
  229. const void *blob = gd->fdt_blob;
  230. if (fdtdec_decode_display_timing(blob, dev_of_offset(dev),
  231. plat->timing_index, timing)) {
  232. debug("%s: Failed to decode display timing\n", __func__);
  233. return -EINVAL;
  234. }
  235. return 0;
  236. }
  237. static int atmel_fb_lcd_bind(struct udevice *dev)
  238. {
  239. struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
  240. uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
  241. (1 << VIDEO_BPP16) / 8;
  242. debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
  243. return 0;
  244. }
  245. static const struct udevice_id atmel_fb_lcd_ids[] = {
  246. { .compatible = "atmel,at91sam9g45-lcdc" },
  247. { }
  248. };
  249. U_BOOT_DRIVER(atmel_fb) = {
  250. .name = "atmel_fb",
  251. .id = UCLASS_VIDEO,
  252. .of_match = atmel_fb_lcd_ids,
  253. .bind = atmel_fb_lcd_bind,
  254. .ofdata_to_platdata = atmel_fb_ofdata_to_platdata,
  255. .probe = atmel_fb_lcd_probe,
  256. .platdata_auto_alloc_size = sizeof(struct atmel_lcd_platdata),
  257. .priv_auto_alloc_size = sizeof(struct atmel_fb_priv),
  258. };
  259. #endif