atmel_hlcdfb.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Driver for AT91/AT32 MULTI LAYER LCD Controller
  4. *
  5. * Copyright (C) 2012 Atmel Corporation
  6. */
  7. #include <common.h>
  8. #include <cpu_func.h>
  9. #include <malloc.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/gpio.h>
  12. #include <asm/arch/clk.h>
  13. #include <clk.h>
  14. #include <dm.h>
  15. #include <fdtdec.h>
  16. #include <lcd.h>
  17. #include <video.h>
  18. #include <wait_bit.h>
  19. #include <atmel_hlcdc.h>
  20. #if defined(CONFIG_LCD_LOGO)
  21. #include <bmp_logo.h>
  22. #endif
  23. DECLARE_GLOBAL_DATA_PTR;
  24. #ifndef CONFIG_DM_VIDEO
  25. /* configurable parameters */
  26. #define ATMEL_LCDC_CVAL_DEFAULT 0xc8
  27. #define ATMEL_LCDC_DMA_BURST_LEN 8
  28. #ifndef ATMEL_LCDC_GUARD_TIME
  29. #define ATMEL_LCDC_GUARD_TIME 1
  30. #endif
  31. #define ATMEL_LCDC_FIFO_SIZE 512
  32. /*
  33. * the CLUT register map as following
  34. * RCLUT(24 ~ 16), GCLUT(15 ~ 8), BCLUT(7 ~ 0)
  35. */
  36. void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
  37. {
  38. writel(panel_info.mmio + ATMEL_LCDC_LUT(regno),
  39. ((red << LCDC_BASECLUT_RCLUT_Pos) & LCDC_BASECLUT_RCLUT_Msk)
  40. | ((green << LCDC_BASECLUT_GCLUT_Pos) & LCDC_BASECLUT_GCLUT_Msk)
  41. | ((blue << LCDC_BASECLUT_BCLUT_Pos) & LCDC_BASECLUT_BCLUT_Msk));
  42. }
  43. ushort *configuration_get_cmap(void)
  44. {
  45. #if defined(CONFIG_LCD_LOGO)
  46. return bmp_logo_palette;
  47. #else
  48. return NULL;
  49. #endif
  50. }
  51. void lcd_ctrl_init(void *lcdbase)
  52. {
  53. unsigned long value;
  54. struct lcd_dma_desc *desc;
  55. struct atmel_hlcd_regs *regs;
  56. int ret;
  57. if (!has_lcdc())
  58. return; /* No lcdc */
  59. regs = (struct atmel_hlcd_regs *)panel_info.mmio;
  60. /* Disable DISP signal */
  61. writel(LCDC_LCDDIS_DISPDIS, &regs->lcdc_lcddis);
  62. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
  63. false, 1000, false);
  64. if (ret)
  65. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  66. /* Disable synchronization */
  67. writel(LCDC_LCDDIS_SYNCDIS, &regs->lcdc_lcddis);
  68. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
  69. false, 1000, false);
  70. if (ret)
  71. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  72. /* Disable pixel clock */
  73. writel(LCDC_LCDDIS_CLKDIS, &regs->lcdc_lcddis);
  74. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
  75. false, 1000, false);
  76. if (ret)
  77. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  78. /* Disable PWM */
  79. writel(LCDC_LCDDIS_PWMDIS, &regs->lcdc_lcddis);
  80. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
  81. false, 1000, false);
  82. if (ret)
  83. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  84. /* Set pixel clock */
  85. value = get_lcdc_clk_rate(0) / panel_info.vl_clk;
  86. if (get_lcdc_clk_rate(0) % panel_info.vl_clk)
  87. value++;
  88. if (value < 1) {
  89. /* Using system clock as pixel clock */
  90. writel(LCDC_LCDCFG0_CLKDIV(0)
  91. | LCDC_LCDCFG0_CGDISHCR
  92. | LCDC_LCDCFG0_CGDISHEO
  93. | LCDC_LCDCFG0_CGDISOVR1
  94. | LCDC_LCDCFG0_CGDISBASE
  95. | panel_info.vl_clk_pol
  96. | LCDC_LCDCFG0_CLKSEL,
  97. &regs->lcdc_lcdcfg0);
  98. } else {
  99. writel(LCDC_LCDCFG0_CLKDIV(value - 2)
  100. | LCDC_LCDCFG0_CGDISHCR
  101. | LCDC_LCDCFG0_CGDISHEO
  102. | LCDC_LCDCFG0_CGDISOVR1
  103. | LCDC_LCDCFG0_CGDISBASE
  104. | panel_info.vl_clk_pol,
  105. &regs->lcdc_lcdcfg0);
  106. }
  107. /* Initialize control register 5 */
  108. value = 0;
  109. value |= panel_info.vl_sync;
  110. #ifndef LCD_OUTPUT_BPP
  111. /* Output is 24bpp */
  112. value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
  113. #else
  114. switch (LCD_OUTPUT_BPP) {
  115. case 12:
  116. value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP;
  117. break;
  118. case 16:
  119. value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP;
  120. break;
  121. case 18:
  122. value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP;
  123. break;
  124. case 24:
  125. value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
  126. break;
  127. default:
  128. BUG();
  129. break;
  130. }
  131. #endif
  132. value |= LCDC_LCDCFG5_GUARDTIME(ATMEL_LCDC_GUARD_TIME);
  133. value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS);
  134. writel(value, &regs->lcdc_lcdcfg5);
  135. /* Vertical & Horizontal Timing */
  136. value = LCDC_LCDCFG1_VSPW(panel_info.vl_vsync_len - 1);
  137. value |= LCDC_LCDCFG1_HSPW(panel_info.vl_hsync_len - 1);
  138. writel(value, &regs->lcdc_lcdcfg1);
  139. value = LCDC_LCDCFG2_VBPW(panel_info.vl_upper_margin);
  140. value |= LCDC_LCDCFG2_VFPW(panel_info.vl_lower_margin - 1);
  141. writel(value, &regs->lcdc_lcdcfg2);
  142. value = LCDC_LCDCFG3_HBPW(panel_info.vl_left_margin - 1);
  143. value |= LCDC_LCDCFG3_HFPW(panel_info.vl_right_margin - 1);
  144. writel(value, &regs->lcdc_lcdcfg3);
  145. /* Display size */
  146. value = LCDC_LCDCFG4_RPF(panel_info.vl_row - 1);
  147. value |= LCDC_LCDCFG4_PPL(panel_info.vl_col - 1);
  148. writel(value, &regs->lcdc_lcdcfg4);
  149. writel(LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO,
  150. &regs->lcdc_basecfg0);
  151. switch (NBITS(panel_info.vl_bpix)) {
  152. case 16:
  153. writel(LCDC_BASECFG1_RGBMODE_16BPP_RGB_565,
  154. &regs->lcdc_basecfg1);
  155. break;
  156. case 32:
  157. writel(LCDC_BASECFG1_RGBMODE_24BPP_RGB_888,
  158. &regs->lcdc_basecfg1);
  159. break;
  160. default:
  161. BUG();
  162. break;
  163. }
  164. writel(LCDC_BASECFG2_XSTRIDE(0), &regs->lcdc_basecfg2);
  165. writel(0, &regs->lcdc_basecfg3);
  166. writel(LCDC_BASECFG4_DMA, &regs->lcdc_basecfg4);
  167. /* Disable all interrupts */
  168. writel(~0UL, &regs->lcdc_lcdidr);
  169. writel(~0UL, &regs->lcdc_baseidr);
  170. /* Setup the DMA descriptor, this descriptor will loop to itself */
  171. desc = (struct lcd_dma_desc *)(lcdbase - 16);
  172. desc->address = (u32)lcdbase;
  173. /* Disable DMA transfer interrupt & descriptor loaded interrupt. */
  174. desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN
  175. | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
  176. desc->next = (u32)desc;
  177. /* Flush the DMA descriptor if we enabled dcache */
  178. flush_dcache_range((u32)desc, (u32)desc + sizeof(*desc));
  179. writel(desc->address, &regs->lcdc_baseaddr);
  180. writel(desc->control, &regs->lcdc_basectrl);
  181. writel(desc->next, &regs->lcdc_basenext);
  182. writel(LCDC_BASECHER_CHEN | LCDC_BASECHER_UPDATEEN,
  183. &regs->lcdc_basecher);
  184. /* Enable LCD */
  185. value = readl(&regs->lcdc_lcden);
  186. writel(value | LCDC_LCDEN_CLKEN, &regs->lcdc_lcden);
  187. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
  188. true, 1000, false);
  189. if (ret)
  190. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  191. value = readl(&regs->lcdc_lcden);
  192. writel(value | LCDC_LCDEN_SYNCEN, &regs->lcdc_lcden);
  193. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
  194. true, 1000, false);
  195. if (ret)
  196. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  197. value = readl(&regs->lcdc_lcden);
  198. writel(value | LCDC_LCDEN_DISPEN, &regs->lcdc_lcden);
  199. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
  200. true, 1000, false);
  201. if (ret)
  202. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  203. value = readl(&regs->lcdc_lcden);
  204. writel(value | LCDC_LCDEN_PWMEN, &regs->lcdc_lcden);
  205. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
  206. true, 1000, false);
  207. if (ret)
  208. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  209. /* Enable flushing if we enabled dcache */
  210. lcd_set_flush_dcache(1);
  211. }
  212. #else
  213. enum {
  214. LCD_MAX_WIDTH = 1024,
  215. LCD_MAX_HEIGHT = 768,
  216. LCD_MAX_LOG2_BPP = VIDEO_BPP16,
  217. };
  218. struct atmel_hlcdc_priv {
  219. struct atmel_hlcd_regs *regs;
  220. struct display_timing timing;
  221. unsigned int vl_bpix;
  222. unsigned int output_mode;
  223. unsigned int guard_time;
  224. ulong clk_rate;
  225. };
  226. static int at91_hlcdc_enable_clk(struct udevice *dev)
  227. {
  228. struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
  229. struct clk clk;
  230. ulong clk_rate;
  231. int ret;
  232. ret = clk_get_by_index(dev, 0, &clk);
  233. if (ret)
  234. return -EINVAL;
  235. ret = clk_enable(&clk);
  236. if (ret)
  237. return ret;
  238. clk_rate = clk_get_rate(&clk);
  239. if (!clk_rate) {
  240. clk_disable(&clk);
  241. return -ENODEV;
  242. }
  243. priv->clk_rate = clk_rate;
  244. clk_free(&clk);
  245. return 0;
  246. }
  247. static void atmel_hlcdc_init(struct udevice *dev)
  248. {
  249. struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
  250. struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
  251. struct atmel_hlcd_regs *regs = priv->regs;
  252. struct display_timing *timing = &priv->timing;
  253. struct lcd_dma_desc *desc;
  254. unsigned long value, vl_clk_pol;
  255. int ret;
  256. /* Disable DISP signal */
  257. writel(LCDC_LCDDIS_DISPDIS, &regs->lcdc_lcddis);
  258. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
  259. false, 1000, false);
  260. if (ret)
  261. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  262. /* Disable synchronization */
  263. writel(LCDC_LCDDIS_SYNCDIS, &regs->lcdc_lcddis);
  264. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
  265. false, 1000, false);
  266. if (ret)
  267. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  268. /* Disable pixel clock */
  269. writel(LCDC_LCDDIS_CLKDIS, &regs->lcdc_lcddis);
  270. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
  271. false, 1000, false);
  272. if (ret)
  273. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  274. /* Disable PWM */
  275. writel(LCDC_LCDDIS_PWMDIS, &regs->lcdc_lcddis);
  276. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
  277. false, 1000, false);
  278. if (ret)
  279. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  280. /* Set pixel clock */
  281. value = priv->clk_rate / timing->pixelclock.typ;
  282. if (priv->clk_rate % timing->pixelclock.typ)
  283. value++;
  284. vl_clk_pol = 0;
  285. if (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
  286. vl_clk_pol = LCDC_LCDCFG0_CLKPOL;
  287. if (value < 1) {
  288. /* Using system clock as pixel clock */
  289. writel(LCDC_LCDCFG0_CLKDIV(0)
  290. | LCDC_LCDCFG0_CGDISHCR
  291. | LCDC_LCDCFG0_CGDISHEO
  292. | LCDC_LCDCFG0_CGDISOVR1
  293. | LCDC_LCDCFG0_CGDISBASE
  294. | vl_clk_pol
  295. | LCDC_LCDCFG0_CLKSEL,
  296. &regs->lcdc_lcdcfg0);
  297. } else {
  298. writel(LCDC_LCDCFG0_CLKDIV(value - 2)
  299. | LCDC_LCDCFG0_CGDISHCR
  300. | LCDC_LCDCFG0_CGDISHEO
  301. | LCDC_LCDCFG0_CGDISOVR1
  302. | LCDC_LCDCFG0_CGDISBASE
  303. | vl_clk_pol,
  304. &regs->lcdc_lcdcfg0);
  305. }
  306. /* Initialize control register 5 */
  307. value = 0;
  308. if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH))
  309. value |= LCDC_LCDCFG5_HSPOL;
  310. if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH))
  311. value |= LCDC_LCDCFG5_VSPOL;
  312. switch (priv->output_mode) {
  313. case 12:
  314. value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP;
  315. break;
  316. case 16:
  317. value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP;
  318. break;
  319. case 18:
  320. value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP;
  321. break;
  322. case 24:
  323. value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
  324. break;
  325. default:
  326. BUG();
  327. break;
  328. }
  329. value |= LCDC_LCDCFG5_GUARDTIME(priv->guard_time);
  330. value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS);
  331. writel(value, &regs->lcdc_lcdcfg5);
  332. /* Vertical & Horizontal Timing */
  333. value = LCDC_LCDCFG1_VSPW(timing->vsync_len.typ - 1);
  334. value |= LCDC_LCDCFG1_HSPW(timing->hsync_len.typ - 1);
  335. writel(value, &regs->lcdc_lcdcfg1);
  336. value = LCDC_LCDCFG2_VBPW(timing->vback_porch.typ);
  337. value |= LCDC_LCDCFG2_VFPW(timing->vfront_porch.typ - 1);
  338. writel(value, &regs->lcdc_lcdcfg2);
  339. value = LCDC_LCDCFG3_HBPW(timing->hback_porch.typ - 1);
  340. value |= LCDC_LCDCFG3_HFPW(timing->hfront_porch.typ - 1);
  341. writel(value, &regs->lcdc_lcdcfg3);
  342. /* Display size */
  343. value = LCDC_LCDCFG4_RPF(timing->vactive.typ - 1);
  344. value |= LCDC_LCDCFG4_PPL(timing->hactive.typ - 1);
  345. writel(value, &regs->lcdc_lcdcfg4);
  346. writel(LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO,
  347. &regs->lcdc_basecfg0);
  348. switch (VNBITS(priv->vl_bpix)) {
  349. case 16:
  350. writel(LCDC_BASECFG1_RGBMODE_16BPP_RGB_565,
  351. &regs->lcdc_basecfg1);
  352. break;
  353. case 32:
  354. writel(LCDC_BASECFG1_RGBMODE_24BPP_RGB_888,
  355. &regs->lcdc_basecfg1);
  356. break;
  357. default:
  358. BUG();
  359. break;
  360. }
  361. writel(LCDC_BASECFG2_XSTRIDE(0), &regs->lcdc_basecfg2);
  362. writel(0, &regs->lcdc_basecfg3);
  363. writel(LCDC_BASECFG4_DMA, &regs->lcdc_basecfg4);
  364. /* Disable all interrupts */
  365. writel(~0UL, &regs->lcdc_lcdidr);
  366. writel(~0UL, &regs->lcdc_baseidr);
  367. /* Setup the DMA descriptor, this descriptor will loop to itself */
  368. desc = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*desc));
  369. if (!desc)
  370. return;
  371. desc->address = (u32)uc_plat->base;
  372. /* Disable DMA transfer interrupt & descriptor loaded interrupt. */
  373. desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN
  374. | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
  375. desc->next = (u32)desc;
  376. /* Flush the DMA descriptor if we enabled dcache */
  377. flush_dcache_range((u32)desc,
  378. ALIGN(((u32)desc + sizeof(*desc)),
  379. CONFIG_SYS_CACHELINE_SIZE));
  380. writel(desc->address, &regs->lcdc_baseaddr);
  381. writel(desc->control, &regs->lcdc_basectrl);
  382. writel(desc->next, &regs->lcdc_basenext);
  383. writel(LCDC_BASECHER_CHEN | LCDC_BASECHER_UPDATEEN,
  384. &regs->lcdc_basecher);
  385. /* Enable LCD */
  386. value = readl(&regs->lcdc_lcden);
  387. writel(value | LCDC_LCDEN_CLKEN, &regs->lcdc_lcden);
  388. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
  389. true, 1000, false);
  390. if (ret)
  391. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  392. value = readl(&regs->lcdc_lcden);
  393. writel(value | LCDC_LCDEN_SYNCEN, &regs->lcdc_lcden);
  394. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
  395. true, 1000, false);
  396. if (ret)
  397. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  398. value = readl(&regs->lcdc_lcden);
  399. writel(value | LCDC_LCDEN_DISPEN, &regs->lcdc_lcden);
  400. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
  401. true, 1000, false);
  402. if (ret)
  403. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  404. value = readl(&regs->lcdc_lcden);
  405. writel(value | LCDC_LCDEN_PWMEN, &regs->lcdc_lcden);
  406. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
  407. true, 1000, false);
  408. if (ret)
  409. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  410. }
  411. static int atmel_hlcdc_probe(struct udevice *dev)
  412. {
  413. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  414. struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
  415. int ret;
  416. ret = at91_hlcdc_enable_clk(dev);
  417. if (ret)
  418. return ret;
  419. atmel_hlcdc_init(dev);
  420. uc_priv->xsize = priv->timing.hactive.typ;
  421. uc_priv->ysize = priv->timing.vactive.typ;
  422. uc_priv->bpix = priv->vl_bpix;
  423. /* Enable flushing if we enabled dcache */
  424. video_set_flush_dcache(dev, true);
  425. return 0;
  426. }
  427. static int atmel_hlcdc_ofdata_to_platdata(struct udevice *dev)
  428. {
  429. struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
  430. const void *blob = gd->fdt_blob;
  431. int node = dev_of_offset(dev);
  432. priv->regs = (struct atmel_hlcd_regs *)devfdt_get_addr(dev);
  433. if (!priv->regs) {
  434. debug("%s: No display controller address\n", __func__);
  435. return -EINVAL;
  436. }
  437. if (fdtdec_decode_display_timing(blob, dev_of_offset(dev),
  438. 0, &priv->timing)) {
  439. debug("%s: Failed to decode display timing\n", __func__);
  440. return -EINVAL;
  441. }
  442. if (priv->timing.hactive.typ > LCD_MAX_WIDTH)
  443. priv->timing.hactive.typ = LCD_MAX_WIDTH;
  444. if (priv->timing.vactive.typ > LCD_MAX_HEIGHT)
  445. priv->timing.vactive.typ = LCD_MAX_HEIGHT;
  446. priv->vl_bpix = fdtdec_get_int(blob, node, "atmel,vl-bpix", 0);
  447. if (!priv->vl_bpix) {
  448. debug("%s: Failed to get bits per pixel\n", __func__);
  449. return -EINVAL;
  450. }
  451. priv->output_mode = fdtdec_get_int(blob, node, "atmel,output-mode", 24);
  452. priv->guard_time = fdtdec_get_int(blob, node, "atmel,guard-time", 1);
  453. return 0;
  454. }
  455. static int atmel_hlcdc_bind(struct udevice *dev)
  456. {
  457. struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
  458. uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
  459. (1 << LCD_MAX_LOG2_BPP) / 8;
  460. debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
  461. return 0;
  462. }
  463. static const struct udevice_id atmel_hlcdc_ids[] = {
  464. { .compatible = "atmel,sama5d2-hlcdc" },
  465. { .compatible = "atmel,at91sam9x5-hlcdc" },
  466. { }
  467. };
  468. U_BOOT_DRIVER(atmel_hlcdfb) = {
  469. .name = "atmel_hlcdfb",
  470. .id = UCLASS_VIDEO,
  471. .of_match = atmel_hlcdc_ids,
  472. .bind = atmel_hlcdc_bind,
  473. .probe = atmel_hlcdc_probe,
  474. .ofdata_to_platdata = atmel_hlcdc_ofdata_to_platdata,
  475. .priv_auto_alloc_size = sizeof(struct atmel_hlcdc_priv),
  476. };
  477. #endif