anx9804.c 4.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) 2015 Hans de Goede <hdegoede@redhat.com>
  4. */
  5. /*
  6. * Support for the ANX9804 bridge chip, which can take pixel data coming
  7. * from a parallel LCD interface and translate it on the flight into a DP
  8. * interface for driving eDP TFT displays.
  9. */
  10. #include <common.h>
  11. #include <i2c.h>
  12. #include "anx98xx-edp.h"
  13. #include "anx9804.h"
  14. /**
  15. * anx9804_init() - Init anx9804 parallel lcd to edp bridge chip
  16. *
  17. * This function will init an anx9804 parallel lcd to dp bridge chip
  18. * using the passed in parameters.
  19. *
  20. * @i2c_bus: Number of the i2c bus to which the anx9804 is connected.
  21. * @lanes: Number of displayport lanes to use
  22. * @data_rate: Register value for the bandwidth reg 0x06: 1.62G, 0x0a: 2.7G
  23. * @bpp: Bits per pixel, must be 18 or 24
  24. */
  25. void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp)
  26. {
  27. unsigned int orig_i2c_bus = i2c_get_bus_num();
  28. u8 c, colordepth;
  29. int i;
  30. i2c_set_bus_num(i2c_bus);
  31. if (bpp == 18)
  32. colordepth = 0x00; /* 6 bit */
  33. else
  34. colordepth = 0x10; /* 8 bit */
  35. /* Reset */
  36. i2c_reg_write(0x39, ANX9804_RST_CTRL_REG, 1);
  37. mdelay(100);
  38. i2c_reg_write(0x39, ANX9804_RST_CTRL_REG, 0);
  39. /* Write 0 to the powerdown reg (powerup everything) */
  40. i2c_reg_write(0x39, ANX9804_POWERD_CTRL_REG, 0);
  41. c = i2c_reg_read(0x39, ANX9804_DEV_IDH_REG);
  42. if (c != 0x98) {
  43. printf("Error anx9804 chipid mismatch\n");
  44. i2c_set_bus_num(orig_i2c_bus);
  45. return;
  46. }
  47. for (i = 0; i < 100; i++) {
  48. c = i2c_reg_read(0x38, ANX9804_SYS_CTRL2_REG);
  49. i2c_reg_write(0x38, ANX9804_SYS_CTRL2_REG, c);
  50. c = i2c_reg_read(0x38, ANX9804_SYS_CTRL2_REG);
  51. if ((c & ANX9804_SYS_CTRL2_CHA_STA) == 0)
  52. break;
  53. mdelay(5);
  54. }
  55. if (i == 100)
  56. printf("Error anx9804 clock is not stable\n");
  57. i2c_reg_write(0x39, ANX9804_VID_CTRL2_REG, colordepth);
  58. /* Set a bunch of analog related register values */
  59. i2c_reg_write(0x38, ANX9804_PLL_CTRL_REG, 0x07);
  60. i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL3, 0x19);
  61. i2c_reg_write(0x39, ANX9804_PLL_CTRL3, 0xd9);
  62. i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG, ANX9804_RST_CTRL2_AC_MODE);
  63. i2c_reg_write(0x39, ANX9804_ANALOG_DEBUG_REG1, 0xf0);
  64. i2c_reg_write(0x39, ANX9804_ANALOG_DEBUG_REG3, 0x99);
  65. i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL1, 0x7b);
  66. i2c_reg_write(0x38, ANX9804_LINK_DEBUG_REG, 0x30);
  67. i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL, 0x06);
  68. /* Force HPD */
  69. i2c_reg_write(0x38, ANX9804_SYS_CTRL3_REG,
  70. ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL);
  71. /* Power up and configure lanes */
  72. i2c_reg_write(0x38, ANX9804_ANALOG_POWER_DOWN_REG, 0x00);
  73. i2c_reg_write(0x38, ANX9804_TRAINING_LANE0_SET_REG, 0x00);
  74. i2c_reg_write(0x38, ANX9804_TRAINING_LANE1_SET_REG, 0x00);
  75. i2c_reg_write(0x38, ANX9804_TRAINING_LANE2_SET_REG, 0x00);
  76. i2c_reg_write(0x38, ANX9804_TRAINING_LANE3_SET_REG, 0x00);
  77. /* Reset AUX CH */
  78. i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG,
  79. ANX9804_RST_CTRL2_AC_MODE | ANX9804_RST_CTRL2_AUX);
  80. i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG,
  81. ANX9804_RST_CTRL2_AC_MODE);
  82. /* Powerdown audio and some other unused bits */
  83. i2c_reg_write(0x39, ANX9804_POWERD_CTRL_REG, ANX9804_POWERD_AUDIO);
  84. i2c_reg_write(0x38, ANX9804_HDCP_CONTROL_0_REG, 0x00);
  85. i2c_reg_write(0x38, 0xa7, 0x00);
  86. /* Set data-rate / lanes */
  87. i2c_reg_write(0x38, ANX9804_LINK_BW_SET_REG, data_rate);
  88. i2c_reg_write(0x38, ANX9804_LANE_COUNT_SET_REG, lanes);
  89. /* Link training */
  90. i2c_reg_write(0x38, ANX9804_LINK_TRAINING_CTRL_REG,
  91. ANX9804_LINK_TRAINING_CTRL_EN);
  92. mdelay(5);
  93. for (i = 0; i < 100; i++) {
  94. c = i2c_reg_read(0x38, ANX9804_LINK_TRAINING_CTRL_REG);
  95. if ((c & 0x01) == 0)
  96. break;
  97. mdelay(5);
  98. }
  99. if(i == 100) {
  100. printf("Error anx9804 link training timeout\n");
  101. i2c_set_bus_num(orig_i2c_bus);
  102. return;
  103. }
  104. /* Enable */
  105. i2c_reg_write(0x39, ANX9804_VID_CTRL1_REG,
  106. ANX9804_VID_CTRL1_VID_EN | ANX9804_VID_CTRL1_EDGE);
  107. /* Force stream valid */
  108. i2c_reg_write(0x38, ANX9804_SYS_CTRL3_REG,
  109. ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL |
  110. ANX9804_SYS_CTRL3_F_VALID | ANX9804_SYS_CTRL3_VALID_CTRL);
  111. i2c_set_bus_num(orig_i2c_bus);
  112. }