xhci.c 42 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * USB HOST XHCI Controller stack
  4. *
  5. * Based on xHCI host controller driver in linux-kernel
  6. * by Sarah Sharp.
  7. *
  8. * Copyright (C) 2008 Intel Corp.
  9. * Author: Sarah Sharp
  10. *
  11. * Copyright (C) 2013 Samsung Electronics Co.Ltd
  12. * Authors: Vivek Gautam <gautam.vivek@samsung.com>
  13. * Vikas Sajjan <vikas.sajjan@samsung.com>
  14. */
  15. /**
  16. * This file gives the xhci stack for usb3.0 looking into
  17. * xhci specification Rev1.0 (5/21/10).
  18. * The quirk devices support hasn't been given yet.
  19. */
  20. #include <common.h>
  21. #include <cpu_func.h>
  22. #include <dm.h>
  23. #include <asm/byteorder.h>
  24. #include <usb.h>
  25. #include <malloc.h>
  26. #include <watchdog.h>
  27. #include <asm/cache.h>
  28. #include <asm/unaligned.h>
  29. #include <linux/errno.h>
  30. #include <usb/xhci.h>
  31. #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
  32. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  33. #endif
  34. static struct descriptor {
  35. struct usb_hub_descriptor hub;
  36. struct usb_device_descriptor device;
  37. struct usb_config_descriptor config;
  38. struct usb_interface_descriptor interface;
  39. struct usb_endpoint_descriptor endpoint;
  40. struct usb_ss_ep_comp_descriptor ep_companion;
  41. } __attribute__ ((packed)) descriptor = {
  42. {
  43. 0xc, /* bDescLength */
  44. 0x2a, /* bDescriptorType: hub descriptor */
  45. 2, /* bNrPorts -- runtime modified */
  46. cpu_to_le16(0x8), /* wHubCharacteristics */
  47. 10, /* bPwrOn2PwrGood */
  48. 0, /* bHubCntrCurrent */
  49. { /* Device removable */
  50. } /* at most 7 ports! XXX */
  51. },
  52. {
  53. 0x12, /* bLength */
  54. 1, /* bDescriptorType: UDESC_DEVICE */
  55. cpu_to_le16(0x0300), /* bcdUSB: v3.0 */
  56. 9, /* bDeviceClass: UDCLASS_HUB */
  57. 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
  58. 3, /* bDeviceProtocol: UDPROTO_SSHUBSTT */
  59. 9, /* bMaxPacketSize: 512 bytes 2^9 */
  60. 0x0000, /* idVendor */
  61. 0x0000, /* idProduct */
  62. cpu_to_le16(0x0100), /* bcdDevice */
  63. 1, /* iManufacturer */
  64. 2, /* iProduct */
  65. 0, /* iSerialNumber */
  66. 1 /* bNumConfigurations: 1 */
  67. },
  68. {
  69. 0x9,
  70. 2, /* bDescriptorType: UDESC_CONFIG */
  71. cpu_to_le16(0x1f), /* includes SS endpoint descriptor */
  72. 1, /* bNumInterface */
  73. 1, /* bConfigurationValue */
  74. 0, /* iConfiguration */
  75. 0x40, /* bmAttributes: UC_SELF_POWER */
  76. 0 /* bMaxPower */
  77. },
  78. {
  79. 0x9, /* bLength */
  80. 4, /* bDescriptorType: UDESC_INTERFACE */
  81. 0, /* bInterfaceNumber */
  82. 0, /* bAlternateSetting */
  83. 1, /* bNumEndpoints */
  84. 9, /* bInterfaceClass: UICLASS_HUB */
  85. 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
  86. 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
  87. 0 /* iInterface */
  88. },
  89. {
  90. 0x7, /* bLength */
  91. 5, /* bDescriptorType: UDESC_ENDPOINT */
  92. 0x81, /* bEndpointAddress: IN endpoint 1 */
  93. 3, /* bmAttributes: UE_INTERRUPT */
  94. 8, /* wMaxPacketSize */
  95. 255 /* bInterval */
  96. },
  97. {
  98. 0x06, /* ss_bLength */
  99. 0x30, /* ss_bDescriptorType: SS EP Companion */
  100. 0x00, /* ss_bMaxBurst: allows 1 TX between ACKs */
  101. /* ss_bmAttributes: 1 packet per service interval */
  102. 0x00,
  103. /* ss_wBytesPerInterval: 15 bits for max 15 ports */
  104. cpu_to_le16(0x02),
  105. },
  106. };
  107. #if !CONFIG_IS_ENABLED(DM_USB)
  108. static struct xhci_ctrl xhcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
  109. #endif
  110. struct xhci_ctrl *xhci_get_ctrl(struct usb_device *udev)
  111. {
  112. #if CONFIG_IS_ENABLED(DM_USB)
  113. struct udevice *dev;
  114. /* Find the USB controller */
  115. for (dev = udev->dev;
  116. device_get_uclass_id(dev) != UCLASS_USB;
  117. dev = dev->parent)
  118. ;
  119. return dev_get_priv(dev);
  120. #else
  121. return udev->controller;
  122. #endif
  123. }
  124. /**
  125. * Waits for as per specified amount of time
  126. * for the "result" to match with "done"
  127. *
  128. * @param ptr pointer to the register to be read
  129. * @param mask mask for the value read
  130. * @param done value to be campared with result
  131. * @param usec time to wait till
  132. * @return 0 if handshake is success else < 0 on failure
  133. */
  134. static int handshake(uint32_t volatile *ptr, uint32_t mask,
  135. uint32_t done, int usec)
  136. {
  137. uint32_t result;
  138. do {
  139. result = xhci_readl(ptr);
  140. if (result == ~(uint32_t)0)
  141. return -ENODEV;
  142. result &= mask;
  143. if (result == done)
  144. return 0;
  145. usec--;
  146. udelay(1);
  147. } while (usec > 0);
  148. return -ETIMEDOUT;
  149. }
  150. /**
  151. * Set the run bit and wait for the host to be running.
  152. *
  153. * @param hcor pointer to host controller operation registers
  154. * @return status of the Handshake
  155. */
  156. static int xhci_start(struct xhci_hcor *hcor)
  157. {
  158. u32 temp;
  159. int ret;
  160. puts("Starting the controller\n");
  161. temp = xhci_readl(&hcor->or_usbcmd);
  162. temp |= (CMD_RUN);
  163. xhci_writel(&hcor->or_usbcmd, temp);
  164. /*
  165. * Wait for the HCHalted Status bit to be 0 to indicate the host is
  166. * running.
  167. */
  168. ret = handshake(&hcor->or_usbsts, STS_HALT, 0, XHCI_MAX_HALT_USEC);
  169. if (ret)
  170. debug("Host took too long to start, "
  171. "waited %u microseconds.\n",
  172. XHCI_MAX_HALT_USEC);
  173. return ret;
  174. }
  175. /**
  176. * Resets the XHCI Controller
  177. *
  178. * @param hcor pointer to host controller operation registers
  179. * @return -EBUSY if XHCI Controller is not halted else status of handshake
  180. */
  181. static int xhci_reset(struct xhci_hcor *hcor)
  182. {
  183. u32 cmd;
  184. u32 state;
  185. int ret;
  186. /* Halting the Host first */
  187. debug("// Halt the HC: %p\n", hcor);
  188. state = xhci_readl(&hcor->or_usbsts) & STS_HALT;
  189. if (!state) {
  190. cmd = xhci_readl(&hcor->or_usbcmd);
  191. cmd &= ~CMD_RUN;
  192. xhci_writel(&hcor->or_usbcmd, cmd);
  193. }
  194. ret = handshake(&hcor->or_usbsts,
  195. STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
  196. if (ret) {
  197. printf("Host not halted after %u microseconds.\n",
  198. XHCI_MAX_HALT_USEC);
  199. return -EBUSY;
  200. }
  201. debug("// Reset the HC\n");
  202. cmd = xhci_readl(&hcor->or_usbcmd);
  203. cmd |= CMD_RESET;
  204. xhci_writel(&hcor->or_usbcmd, cmd);
  205. ret = handshake(&hcor->or_usbcmd, CMD_RESET, 0, XHCI_MAX_RESET_USEC);
  206. if (ret)
  207. return ret;
  208. /*
  209. * xHCI cannot write to any doorbells or operational registers other
  210. * than status until the "Controller Not Ready" flag is cleared.
  211. */
  212. return handshake(&hcor->or_usbsts, STS_CNR, 0, XHCI_MAX_RESET_USEC);
  213. }
  214. /**
  215. * Used for passing endpoint bitmasks between the core and HCDs.
  216. * Find the index for an endpoint given its descriptor.
  217. * Use the return value to right shift 1 for the bitmask.
  218. *
  219. * Index = (epnum * 2) + direction - 1,
  220. * where direction = 0 for OUT, 1 for IN.
  221. * For control endpoints, the IN index is used (OUT index is unused), so
  222. * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
  223. *
  224. * @param desc USB enpdoint Descriptor
  225. * @return index of the Endpoint
  226. */
  227. static unsigned int xhci_get_ep_index(struct usb_endpoint_descriptor *desc)
  228. {
  229. unsigned int index;
  230. if (usb_endpoint_xfer_control(desc))
  231. index = (unsigned int)(usb_endpoint_num(desc) * 2);
  232. else
  233. index = (unsigned int)((usb_endpoint_num(desc) * 2) -
  234. (usb_endpoint_dir_in(desc) ? 0 : 1));
  235. return index;
  236. }
  237. /*
  238. * Convert bInterval expressed in microframes (in 1-255 range) to exponent of
  239. * microframes, rounded down to nearest power of 2.
  240. */
  241. static unsigned int xhci_microframes_to_exponent(unsigned int desc_interval,
  242. unsigned int min_exponent,
  243. unsigned int max_exponent)
  244. {
  245. unsigned int interval;
  246. interval = fls(desc_interval) - 1;
  247. interval = clamp_val(interval, min_exponent, max_exponent);
  248. if ((1 << interval) != desc_interval)
  249. debug("rounding interval to %d microframes, "\
  250. "ep desc says %d microframes\n",
  251. 1 << interval, desc_interval);
  252. return interval;
  253. }
  254. static unsigned int xhci_parse_microframe_interval(struct usb_device *udev,
  255. struct usb_endpoint_descriptor *endpt_desc)
  256. {
  257. if (endpt_desc->bInterval == 0)
  258. return 0;
  259. return xhci_microframes_to_exponent(endpt_desc->bInterval, 0, 15);
  260. }
  261. static unsigned int xhci_parse_frame_interval(struct usb_device *udev,
  262. struct usb_endpoint_descriptor *endpt_desc)
  263. {
  264. return xhci_microframes_to_exponent(endpt_desc->bInterval * 8, 3, 10);
  265. }
  266. /*
  267. * Convert interval expressed as 2^(bInterval - 1) == interval into
  268. * straight exponent value 2^n == interval.
  269. */
  270. static unsigned int xhci_parse_exponent_interval(struct usb_device *udev,
  271. struct usb_endpoint_descriptor *endpt_desc)
  272. {
  273. unsigned int interval;
  274. interval = clamp_val(endpt_desc->bInterval, 1, 16) - 1;
  275. if (interval != endpt_desc->bInterval - 1)
  276. debug("ep %#x - rounding interval to %d %sframes\n",
  277. endpt_desc->bEndpointAddress, 1 << interval,
  278. udev->speed == USB_SPEED_FULL ? "" : "micro");
  279. if (udev->speed == USB_SPEED_FULL) {
  280. /*
  281. * Full speed isoc endpoints specify interval in frames,
  282. * not microframes. We are using microframes everywhere,
  283. * so adjust accordingly.
  284. */
  285. interval += 3; /* 1 frame = 2^3 uframes */
  286. }
  287. return interval;
  288. }
  289. /*
  290. * Return the polling or NAK interval.
  291. *
  292. * The polling interval is expressed in "microframes". If xHCI's Interval field
  293. * is set to N, it will service the endpoint every 2^(Interval)*125us.
  294. *
  295. * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
  296. * is set to 0.
  297. */
  298. static unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
  299. struct usb_endpoint_descriptor *endpt_desc)
  300. {
  301. unsigned int interval = 0;
  302. switch (udev->speed) {
  303. case USB_SPEED_HIGH:
  304. /* Max NAK rate */
  305. if (usb_endpoint_xfer_control(endpt_desc) ||
  306. usb_endpoint_xfer_bulk(endpt_desc)) {
  307. interval = xhci_parse_microframe_interval(udev,
  308. endpt_desc);
  309. break;
  310. }
  311. /* Fall through - SS and HS isoc/int have same decoding */
  312. case USB_SPEED_SUPER:
  313. if (usb_endpoint_xfer_int(endpt_desc) ||
  314. usb_endpoint_xfer_isoc(endpt_desc)) {
  315. interval = xhci_parse_exponent_interval(udev,
  316. endpt_desc);
  317. }
  318. break;
  319. case USB_SPEED_FULL:
  320. if (usb_endpoint_xfer_isoc(endpt_desc)) {
  321. interval = xhci_parse_exponent_interval(udev,
  322. endpt_desc);
  323. break;
  324. }
  325. /*
  326. * Fall through for interrupt endpoint interval decoding
  327. * since it uses the same rules as low speed interrupt
  328. * endpoints.
  329. */
  330. case USB_SPEED_LOW:
  331. if (usb_endpoint_xfer_int(endpt_desc) ||
  332. usb_endpoint_xfer_isoc(endpt_desc)) {
  333. interval = xhci_parse_frame_interval(udev, endpt_desc);
  334. }
  335. break;
  336. default:
  337. BUG();
  338. }
  339. return interval;
  340. }
  341. /*
  342. * The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
  343. * High speed endpoint descriptors can define "the number of additional
  344. * transaction opportunities per microframe", but that goes in the Max Burst
  345. * endpoint context field.
  346. */
  347. static u32 xhci_get_endpoint_mult(struct usb_device *udev,
  348. struct usb_endpoint_descriptor *endpt_desc,
  349. struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc)
  350. {
  351. if (udev->speed < USB_SPEED_SUPER ||
  352. !usb_endpoint_xfer_isoc(endpt_desc))
  353. return 0;
  354. return ss_ep_comp_desc->bmAttributes;
  355. }
  356. static u32 xhci_get_endpoint_max_burst(struct usb_device *udev,
  357. struct usb_endpoint_descriptor *endpt_desc,
  358. struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc)
  359. {
  360. /* Super speed and Plus have max burst in ep companion desc */
  361. if (udev->speed >= USB_SPEED_SUPER)
  362. return ss_ep_comp_desc->bMaxBurst;
  363. if (udev->speed == USB_SPEED_HIGH &&
  364. (usb_endpoint_xfer_isoc(endpt_desc) ||
  365. usb_endpoint_xfer_int(endpt_desc)))
  366. return usb_endpoint_maxp_mult(endpt_desc) - 1;
  367. return 0;
  368. }
  369. /*
  370. * Return the maximum endpoint service interval time (ESIT) payload.
  371. * Basically, this is the maxpacket size, multiplied by the burst size
  372. * and mult size.
  373. */
  374. static u32 xhci_get_max_esit_payload(struct usb_device *udev,
  375. struct usb_endpoint_descriptor *endpt_desc,
  376. struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc)
  377. {
  378. int max_burst;
  379. int max_packet;
  380. /* Only applies for interrupt or isochronous endpoints */
  381. if (usb_endpoint_xfer_control(endpt_desc) ||
  382. usb_endpoint_xfer_bulk(endpt_desc))
  383. return 0;
  384. /* SuperSpeed Isoc ep with less than 48k per esit */
  385. if (udev->speed >= USB_SPEED_SUPER)
  386. return le16_to_cpu(ss_ep_comp_desc->wBytesPerInterval);
  387. max_packet = usb_endpoint_maxp(endpt_desc);
  388. max_burst = usb_endpoint_maxp_mult(endpt_desc);
  389. /* A 0 in max burst means 1 transfer per ESIT */
  390. return max_packet * max_burst;
  391. }
  392. /**
  393. * Issue a configure endpoint command or evaluate context command
  394. * and wait for it to finish.
  395. *
  396. * @param udev pointer to the Device Data Structure
  397. * @param ctx_change flag to indicate the Context has changed or NOT
  398. * @return 0 on success, -1 on failure
  399. */
  400. static int xhci_configure_endpoints(struct usb_device *udev, bool ctx_change)
  401. {
  402. struct xhci_container_ctx *in_ctx;
  403. struct xhci_virt_device *virt_dev;
  404. struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
  405. union xhci_trb *event;
  406. virt_dev = ctrl->devs[udev->slot_id];
  407. in_ctx = virt_dev->in_ctx;
  408. xhci_flush_cache((uintptr_t)in_ctx->bytes, in_ctx->size);
  409. xhci_queue_command(ctrl, in_ctx->bytes, udev->slot_id, 0,
  410. ctx_change ? TRB_EVAL_CONTEXT : TRB_CONFIG_EP);
  411. event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
  412. BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
  413. != udev->slot_id);
  414. switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) {
  415. case COMP_SUCCESS:
  416. debug("Successful %s command\n",
  417. ctx_change ? "Evaluate Context" : "Configure Endpoint");
  418. break;
  419. default:
  420. printf("ERROR: %s command returned completion code %d.\n",
  421. ctx_change ? "Evaluate Context" : "Configure Endpoint",
  422. GET_COMP_CODE(le32_to_cpu(event->event_cmd.status)));
  423. return -EINVAL;
  424. }
  425. xhci_acknowledge_event(ctrl);
  426. return 0;
  427. }
  428. /**
  429. * Configure the endpoint, programming the device contexts.
  430. *
  431. * @param udev pointer to the USB device structure
  432. * @return returns the status of the xhci_configure_endpoints
  433. */
  434. static int xhci_set_configuration(struct usb_device *udev)
  435. {
  436. struct xhci_container_ctx *in_ctx;
  437. struct xhci_container_ctx *out_ctx;
  438. struct xhci_input_control_ctx *ctrl_ctx;
  439. struct xhci_slot_ctx *slot_ctx;
  440. struct xhci_ep_ctx *ep_ctx[MAX_EP_CTX_NUM];
  441. int cur_ep;
  442. int max_ep_flag = 0;
  443. int ep_index;
  444. unsigned int dir;
  445. unsigned int ep_type;
  446. struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
  447. int num_of_ep;
  448. int ep_flag = 0;
  449. u64 trb_64 = 0;
  450. int slot_id = udev->slot_id;
  451. struct xhci_virt_device *virt_dev = ctrl->devs[slot_id];
  452. struct usb_interface *ifdesc;
  453. u32 max_esit_payload;
  454. unsigned int interval;
  455. unsigned int mult;
  456. unsigned int max_burst;
  457. unsigned int avg_trb_len;
  458. unsigned int err_count = 0;
  459. out_ctx = virt_dev->out_ctx;
  460. in_ctx = virt_dev->in_ctx;
  461. num_of_ep = udev->config.if_desc[0].no_of_ep;
  462. ifdesc = &udev->config.if_desc[0];
  463. ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
  464. /* Initialize the input context control */
  465. ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
  466. ctrl_ctx->drop_flags = 0;
  467. /* EP_FLAG gives values 1 & 4 for EP1OUT and EP2IN */
  468. for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) {
  469. ep_flag = xhci_get_ep_index(&ifdesc->ep_desc[cur_ep]);
  470. ctrl_ctx->add_flags |= cpu_to_le32(1 << (ep_flag + 1));
  471. if (max_ep_flag < ep_flag)
  472. max_ep_flag = ep_flag;
  473. }
  474. xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size);
  475. /* slot context */
  476. xhci_slot_copy(ctrl, in_ctx, out_ctx);
  477. slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx);
  478. slot_ctx->dev_info &= ~(cpu_to_le32(LAST_CTX_MASK));
  479. slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(max_ep_flag + 1) | 0);
  480. xhci_endpoint_copy(ctrl, in_ctx, out_ctx, 0);
  481. /* filling up ep contexts */
  482. for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) {
  483. struct usb_endpoint_descriptor *endpt_desc = NULL;
  484. struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc = NULL;
  485. endpt_desc = &ifdesc->ep_desc[cur_ep];
  486. ss_ep_comp_desc = &ifdesc->ss_ep_comp_desc[cur_ep];
  487. trb_64 = 0;
  488. /*
  489. * Get values to fill the endpoint context, mostly from ep
  490. * descriptor. The average TRB buffer lengt for bulk endpoints
  491. * is unclear as we have no clue on scatter gather list entry
  492. * size. For Isoc and Int, set it to max available.
  493. * See xHCI 1.1 spec 4.14.1.1 for details.
  494. */
  495. max_esit_payload = xhci_get_max_esit_payload(udev, endpt_desc,
  496. ss_ep_comp_desc);
  497. interval = xhci_get_endpoint_interval(udev, endpt_desc);
  498. mult = xhci_get_endpoint_mult(udev, endpt_desc,
  499. ss_ep_comp_desc);
  500. max_burst = xhci_get_endpoint_max_burst(udev, endpt_desc,
  501. ss_ep_comp_desc);
  502. avg_trb_len = max_esit_payload;
  503. ep_index = xhci_get_ep_index(endpt_desc);
  504. ep_ctx[ep_index] = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
  505. /* Allocate the ep rings */
  506. virt_dev->eps[ep_index].ring = xhci_ring_alloc(1, true);
  507. if (!virt_dev->eps[ep_index].ring)
  508. return -ENOMEM;
  509. /*NOTE: ep_desc[0] actually represents EP1 and so on */
  510. dir = (((endpt_desc->bEndpointAddress) & (0x80)) >> 7);
  511. ep_type = (((endpt_desc->bmAttributes) & (0x3)) | (dir << 2));
  512. ep_ctx[ep_index]->ep_info =
  513. cpu_to_le32(EP_MAX_ESIT_PAYLOAD_HI(max_esit_payload) |
  514. EP_INTERVAL(interval) | EP_MULT(mult));
  515. ep_ctx[ep_index]->ep_info2 =
  516. cpu_to_le32(ep_type << EP_TYPE_SHIFT);
  517. ep_ctx[ep_index]->ep_info2 |=
  518. cpu_to_le32(MAX_PACKET
  519. (get_unaligned(&endpt_desc->wMaxPacketSize)));
  520. /* Allow 3 retries for everything but isoc, set CErr = 3 */
  521. if (!usb_endpoint_xfer_isoc(endpt_desc))
  522. err_count = 3;
  523. ep_ctx[ep_index]->ep_info2 |=
  524. cpu_to_le32(MAX_BURST(max_burst) |
  525. ERROR_COUNT(err_count));
  526. trb_64 = (uintptr_t)
  527. virt_dev->eps[ep_index].ring->enqueue;
  528. ep_ctx[ep_index]->deq = cpu_to_le64(trb_64 |
  529. virt_dev->eps[ep_index].ring->cycle_state);
  530. /*
  531. * xHCI spec 6.2.3:
  532. * 'Average TRB Length' should be 8 for control endpoints.
  533. */
  534. if (usb_endpoint_xfer_control(endpt_desc))
  535. avg_trb_len = 8;
  536. ep_ctx[ep_index]->tx_info =
  537. cpu_to_le32(EP_MAX_ESIT_PAYLOAD_LO(max_esit_payload) |
  538. EP_AVG_TRB_LENGTH(avg_trb_len));
  539. /*
  540. * The MediaTek xHCI defines some extra SW parameters which
  541. * are put into reserved DWs in Slot and Endpoint Contexts
  542. * for synchronous endpoints.
  543. */
  544. if (IS_ENABLED(CONFIG_USB_XHCI_MTK)) {
  545. ep_ctx[ep_index]->reserved[0] =
  546. cpu_to_le32(EP_BPKTS(1) | EP_BBM(1));
  547. }
  548. }
  549. return xhci_configure_endpoints(udev, false);
  550. }
  551. /**
  552. * Issue an Address Device command (which will issue a SetAddress request to
  553. * the device).
  554. *
  555. * @param udev pointer to the Device Data Structure
  556. * @return 0 if successful else error code on failure
  557. */
  558. static int xhci_address_device(struct usb_device *udev, int root_portnr)
  559. {
  560. int ret = 0;
  561. struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
  562. struct xhci_slot_ctx *slot_ctx;
  563. struct xhci_input_control_ctx *ctrl_ctx;
  564. struct xhci_virt_device *virt_dev;
  565. int slot_id = udev->slot_id;
  566. union xhci_trb *event;
  567. virt_dev = ctrl->devs[slot_id];
  568. /*
  569. * This is the first Set Address since device plug-in
  570. * so setting up the slot context.
  571. */
  572. debug("Setting up addressable devices %p\n", ctrl->dcbaa);
  573. xhci_setup_addressable_virt_dev(ctrl, udev, root_portnr);
  574. ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
  575. ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
  576. ctrl_ctx->drop_flags = 0;
  577. xhci_queue_command(ctrl, (void *)ctrl_ctx, slot_id, 0, TRB_ADDR_DEV);
  578. event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
  579. BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags)) != slot_id);
  580. switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) {
  581. case COMP_CTX_STATE:
  582. case COMP_EBADSLT:
  583. printf("Setup ERROR: address device command for slot %d.\n",
  584. slot_id);
  585. ret = -EINVAL;
  586. break;
  587. case COMP_TX_ERR:
  588. puts("Device not responding to set address.\n");
  589. ret = -EPROTO;
  590. break;
  591. case COMP_DEV_ERR:
  592. puts("ERROR: Incompatible device"
  593. "for address device command.\n");
  594. ret = -ENODEV;
  595. break;
  596. case COMP_SUCCESS:
  597. debug("Successful Address Device command\n");
  598. udev->status = 0;
  599. break;
  600. default:
  601. printf("ERROR: unexpected command completion code 0x%x.\n",
  602. GET_COMP_CODE(le32_to_cpu(event->event_cmd.status)));
  603. ret = -EINVAL;
  604. break;
  605. }
  606. xhci_acknowledge_event(ctrl);
  607. if (ret < 0)
  608. /*
  609. * TODO: Unsuccessful Address Device command shall leave the
  610. * slot in default state. So, issue Disable Slot command now.
  611. */
  612. return ret;
  613. xhci_inval_cache((uintptr_t)virt_dev->out_ctx->bytes,
  614. virt_dev->out_ctx->size);
  615. slot_ctx = xhci_get_slot_ctx(ctrl, virt_dev->out_ctx);
  616. debug("xHC internal address is: %d\n",
  617. le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
  618. return 0;
  619. }
  620. /**
  621. * Issue Enable slot command to the controller to allocate
  622. * device slot and assign the slot id. It fails if the xHC
  623. * ran out of device slots, the Enable Slot command timed out,
  624. * or allocating memory failed.
  625. *
  626. * @param udev pointer to the Device Data Structure
  627. * @return Returns 0 on succes else return error code on failure
  628. */
  629. static int _xhci_alloc_device(struct usb_device *udev)
  630. {
  631. struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
  632. union xhci_trb *event;
  633. int ret;
  634. /*
  635. * Root hub will be first device to be initailized.
  636. * If this device is root-hub, don't do any xHC related
  637. * stuff.
  638. */
  639. if (ctrl->rootdev == 0) {
  640. udev->speed = USB_SPEED_SUPER;
  641. return 0;
  642. }
  643. xhci_queue_command(ctrl, NULL, 0, 0, TRB_ENABLE_SLOT);
  644. event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
  645. BUG_ON(GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))
  646. != COMP_SUCCESS);
  647. udev->slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags));
  648. xhci_acknowledge_event(ctrl);
  649. ret = xhci_alloc_virt_device(ctrl, udev->slot_id);
  650. if (ret < 0) {
  651. /*
  652. * TODO: Unsuccessful Address Device command shall leave
  653. * the slot in default. So, issue Disable Slot command now.
  654. */
  655. puts("Could not allocate xHCI USB device data structures\n");
  656. return ret;
  657. }
  658. return 0;
  659. }
  660. #if !CONFIG_IS_ENABLED(DM_USB)
  661. int usb_alloc_device(struct usb_device *udev)
  662. {
  663. return _xhci_alloc_device(udev);
  664. }
  665. #endif
  666. /*
  667. * Full speed devices may have a max packet size greater than 8 bytes, but the
  668. * USB core doesn't know that until it reads the first 8 bytes of the
  669. * descriptor. If the usb_device's max packet size changes after that point,
  670. * we need to issue an evaluate context command and wait on it.
  671. *
  672. * @param udev pointer to the Device Data Structure
  673. * @return returns the status of the xhci_configure_endpoints
  674. */
  675. int xhci_check_maxpacket(struct usb_device *udev)
  676. {
  677. struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
  678. unsigned int slot_id = udev->slot_id;
  679. int ep_index = 0; /* control endpoint */
  680. struct xhci_container_ctx *in_ctx;
  681. struct xhci_container_ctx *out_ctx;
  682. struct xhci_input_control_ctx *ctrl_ctx;
  683. struct xhci_ep_ctx *ep_ctx;
  684. int max_packet_size;
  685. int hw_max_packet_size;
  686. int ret = 0;
  687. out_ctx = ctrl->devs[slot_id]->out_ctx;
  688. xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size);
  689. ep_ctx = xhci_get_ep_ctx(ctrl, out_ctx, ep_index);
  690. hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
  691. max_packet_size = udev->epmaxpacketin[0];
  692. if (hw_max_packet_size != max_packet_size) {
  693. debug("Max Packet Size for ep 0 changed.\n");
  694. debug("Max packet size in usb_device = %d\n", max_packet_size);
  695. debug("Max packet size in xHCI HW = %d\n", hw_max_packet_size);
  696. debug("Issuing evaluate context command.\n");
  697. /* Set up the modified control endpoint 0 */
  698. xhci_endpoint_copy(ctrl, ctrl->devs[slot_id]->in_ctx,
  699. ctrl->devs[slot_id]->out_ctx, ep_index);
  700. in_ctx = ctrl->devs[slot_id]->in_ctx;
  701. ep_ctx = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
  702. ep_ctx->ep_info2 &= cpu_to_le32(~((0xffff & MAX_PACKET_MASK)
  703. << MAX_PACKET_SHIFT));
  704. ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
  705. /*
  706. * Set up the input context flags for the command
  707. * FIXME: This won't work if a non-default control endpoint
  708. * changes max packet sizes.
  709. */
  710. ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
  711. ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
  712. ctrl_ctx->drop_flags = 0;
  713. ret = xhci_configure_endpoints(udev, true);
  714. }
  715. return ret;
  716. }
  717. /**
  718. * Clears the Change bits of the Port Status Register
  719. *
  720. * @param wValue request value
  721. * @param wIndex request index
  722. * @param addr address of posrt status register
  723. * @param port_status state of port status register
  724. * @return none
  725. */
  726. static void xhci_clear_port_change_bit(u16 wValue,
  727. u16 wIndex, volatile uint32_t *addr, u32 port_status)
  728. {
  729. char *port_change_bit;
  730. u32 status;
  731. switch (wValue) {
  732. case USB_PORT_FEAT_C_RESET:
  733. status = PORT_RC;
  734. port_change_bit = "reset";
  735. break;
  736. case USB_PORT_FEAT_C_CONNECTION:
  737. status = PORT_CSC;
  738. port_change_bit = "connect";
  739. break;
  740. case USB_PORT_FEAT_C_OVER_CURRENT:
  741. status = PORT_OCC;
  742. port_change_bit = "over-current";
  743. break;
  744. case USB_PORT_FEAT_C_ENABLE:
  745. status = PORT_PEC;
  746. port_change_bit = "enable/disable";
  747. break;
  748. case USB_PORT_FEAT_C_SUSPEND:
  749. status = PORT_PLC;
  750. port_change_bit = "suspend/resume";
  751. break;
  752. default:
  753. /* Should never happen */
  754. return;
  755. }
  756. /* Change bits are all write 1 to clear */
  757. xhci_writel(addr, port_status | status);
  758. port_status = xhci_readl(addr);
  759. debug("clear port %s change, actual port %d status = 0x%x\n",
  760. port_change_bit, wIndex, port_status);
  761. }
  762. /**
  763. * Save Read Only (RO) bits and save read/write bits where
  764. * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
  765. * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
  766. *
  767. * @param state state of the Port Status and Control Regsiter
  768. * @return a value that would result in the port being in the
  769. * same state, if the value was written to the port
  770. * status control register.
  771. */
  772. static u32 xhci_port_state_to_neutral(u32 state)
  773. {
  774. /* Save read-only status and port state */
  775. return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
  776. }
  777. /**
  778. * Submits the Requests to the XHCI Host Controller
  779. *
  780. * @param udev pointer to the USB device structure
  781. * @param pipe contains the DIR_IN or OUT , devnum
  782. * @param buffer buffer to be read/written based on the request
  783. * @return returns 0 if successful else -1 on failure
  784. */
  785. static int xhci_submit_root(struct usb_device *udev, unsigned long pipe,
  786. void *buffer, struct devrequest *req)
  787. {
  788. uint8_t tmpbuf[4];
  789. u16 typeReq;
  790. void *srcptr = NULL;
  791. int len, srclen;
  792. uint32_t reg;
  793. volatile uint32_t *status_reg;
  794. struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
  795. struct xhci_hccr *hccr = ctrl->hccr;
  796. struct xhci_hcor *hcor = ctrl->hcor;
  797. int max_ports = HCS_MAX_PORTS(xhci_readl(&hccr->cr_hcsparams1));
  798. if ((req->requesttype & USB_RT_PORT) &&
  799. le16_to_cpu(req->index) > max_ports) {
  800. printf("The request port(%d) exceeds maximum port number\n",
  801. le16_to_cpu(req->index) - 1);
  802. return -EINVAL;
  803. }
  804. status_reg = (volatile uint32_t *)
  805. (&hcor->portregs[le16_to_cpu(req->index) - 1].or_portsc);
  806. srclen = 0;
  807. typeReq = req->request | req->requesttype << 8;
  808. switch (typeReq) {
  809. case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
  810. switch (le16_to_cpu(req->value) >> 8) {
  811. case USB_DT_DEVICE:
  812. debug("USB_DT_DEVICE request\n");
  813. srcptr = &descriptor.device;
  814. srclen = 0x12;
  815. break;
  816. case USB_DT_CONFIG:
  817. debug("USB_DT_CONFIG config\n");
  818. srcptr = &descriptor.config;
  819. srclen = 0x19;
  820. break;
  821. case USB_DT_STRING:
  822. debug("USB_DT_STRING config\n");
  823. switch (le16_to_cpu(req->value) & 0xff) {
  824. case 0: /* Language */
  825. srcptr = "\4\3\11\4";
  826. srclen = 4;
  827. break;
  828. case 1: /* Vendor String */
  829. srcptr = "\16\3U\0-\0B\0o\0o\0t\0";
  830. srclen = 14;
  831. break;
  832. case 2: /* Product Name */
  833. srcptr = "\52\3X\0H\0C\0I\0 "
  834. "\0H\0o\0s\0t\0 "
  835. "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
  836. srclen = 42;
  837. break;
  838. default:
  839. printf("unknown value DT_STRING %x\n",
  840. le16_to_cpu(req->value));
  841. goto unknown;
  842. }
  843. break;
  844. default:
  845. printf("unknown value %x\n", le16_to_cpu(req->value));
  846. goto unknown;
  847. }
  848. break;
  849. case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
  850. switch (le16_to_cpu(req->value) >> 8) {
  851. case USB_DT_HUB:
  852. case USB_DT_SS_HUB:
  853. debug("USB_DT_HUB config\n");
  854. srcptr = &descriptor.hub;
  855. srclen = 0x8;
  856. break;
  857. default:
  858. printf("unknown value %x\n", le16_to_cpu(req->value));
  859. goto unknown;
  860. }
  861. break;
  862. case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
  863. debug("USB_REQ_SET_ADDRESS\n");
  864. ctrl->rootdev = le16_to_cpu(req->value);
  865. break;
  866. case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
  867. /* Do nothing */
  868. break;
  869. case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
  870. tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
  871. tmpbuf[1] = 0;
  872. srcptr = tmpbuf;
  873. srclen = 2;
  874. break;
  875. case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
  876. memset(tmpbuf, 0, 4);
  877. reg = xhci_readl(status_reg);
  878. if (reg & PORT_CONNECT) {
  879. tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
  880. switch (reg & DEV_SPEED_MASK) {
  881. case XDEV_FS:
  882. debug("SPEED = FULLSPEED\n");
  883. break;
  884. case XDEV_LS:
  885. debug("SPEED = LOWSPEED\n");
  886. tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
  887. break;
  888. case XDEV_HS:
  889. debug("SPEED = HIGHSPEED\n");
  890. tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
  891. break;
  892. case XDEV_SS:
  893. debug("SPEED = SUPERSPEED\n");
  894. tmpbuf[1] |= USB_PORT_STAT_SUPER_SPEED >> 8;
  895. break;
  896. }
  897. }
  898. if (reg & PORT_PE)
  899. tmpbuf[0] |= USB_PORT_STAT_ENABLE;
  900. if ((reg & PORT_PLS_MASK) == XDEV_U3)
  901. tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
  902. if (reg & PORT_OC)
  903. tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
  904. if (reg & PORT_RESET)
  905. tmpbuf[0] |= USB_PORT_STAT_RESET;
  906. if (reg & PORT_POWER)
  907. /*
  908. * XXX: This Port power bit (for USB 3.0 hub)
  909. * we are faking in USB 2.0 hub port status;
  910. * since there's a change in bit positions in
  911. * two:
  912. * USB 2.0 port status PP is at position[8]
  913. * USB 3.0 port status PP is at position[9]
  914. * So, we are still keeping it at position [8]
  915. */
  916. tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
  917. if (reg & PORT_CSC)
  918. tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
  919. if (reg & PORT_PEC)
  920. tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
  921. if (reg & PORT_OCC)
  922. tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
  923. if (reg & PORT_RC)
  924. tmpbuf[2] |= USB_PORT_STAT_C_RESET;
  925. srcptr = tmpbuf;
  926. srclen = 4;
  927. break;
  928. case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
  929. reg = xhci_readl(status_reg);
  930. reg = xhci_port_state_to_neutral(reg);
  931. switch (le16_to_cpu(req->value)) {
  932. case USB_PORT_FEAT_ENABLE:
  933. reg |= PORT_PE;
  934. xhci_writel(status_reg, reg);
  935. break;
  936. case USB_PORT_FEAT_POWER:
  937. reg |= PORT_POWER;
  938. xhci_writel(status_reg, reg);
  939. break;
  940. case USB_PORT_FEAT_RESET:
  941. reg |= PORT_RESET;
  942. xhci_writel(status_reg, reg);
  943. break;
  944. default:
  945. printf("unknown feature %x\n", le16_to_cpu(req->value));
  946. goto unknown;
  947. }
  948. break;
  949. case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
  950. reg = xhci_readl(status_reg);
  951. reg = xhci_port_state_to_neutral(reg);
  952. switch (le16_to_cpu(req->value)) {
  953. case USB_PORT_FEAT_ENABLE:
  954. reg &= ~PORT_PE;
  955. break;
  956. case USB_PORT_FEAT_POWER:
  957. reg &= ~PORT_POWER;
  958. break;
  959. case USB_PORT_FEAT_C_RESET:
  960. case USB_PORT_FEAT_C_CONNECTION:
  961. case USB_PORT_FEAT_C_OVER_CURRENT:
  962. case USB_PORT_FEAT_C_ENABLE:
  963. xhci_clear_port_change_bit((le16_to_cpu(req->value)),
  964. le16_to_cpu(req->index),
  965. status_reg, reg);
  966. break;
  967. default:
  968. printf("unknown feature %x\n", le16_to_cpu(req->value));
  969. goto unknown;
  970. }
  971. xhci_writel(status_reg, reg);
  972. break;
  973. default:
  974. puts("Unknown request\n");
  975. goto unknown;
  976. }
  977. debug("scrlen = %d\n req->length = %d\n",
  978. srclen, le16_to_cpu(req->length));
  979. len = min(srclen, (int)le16_to_cpu(req->length));
  980. if (srcptr != NULL && len > 0)
  981. memcpy(buffer, srcptr, len);
  982. else
  983. debug("Len is 0\n");
  984. udev->act_len = len;
  985. udev->status = 0;
  986. return 0;
  987. unknown:
  988. udev->act_len = 0;
  989. udev->status = USB_ST_STALLED;
  990. return -ENODEV;
  991. }
  992. /**
  993. * Submits the INT request to XHCI Host cotroller
  994. *
  995. * @param udev pointer to the USB device
  996. * @param pipe contains the DIR_IN or OUT , devnum
  997. * @param buffer buffer to be read/written based on the request
  998. * @param length length of the buffer
  999. * @param interval interval of the interrupt
  1000. * @return 0
  1001. */
  1002. static int _xhci_submit_int_msg(struct usb_device *udev, unsigned long pipe,
  1003. void *buffer, int length, int interval,
  1004. bool nonblock)
  1005. {
  1006. if (usb_pipetype(pipe) != PIPE_INTERRUPT) {
  1007. printf("non-interrupt pipe (type=%lu)", usb_pipetype(pipe));
  1008. return -EINVAL;
  1009. }
  1010. /*
  1011. * xHCI uses normal TRBs for both bulk and interrupt. When the
  1012. * interrupt endpoint is to be serviced, the xHC will consume
  1013. * (at most) one TD. A TD (comprised of sg list entries) can
  1014. * take several service intervals to transmit.
  1015. */
  1016. return xhci_bulk_tx(udev, pipe, length, buffer);
  1017. }
  1018. /**
  1019. * submit the BULK type of request to the USB Device
  1020. *
  1021. * @param udev pointer to the USB device
  1022. * @param pipe contains the DIR_IN or OUT , devnum
  1023. * @param buffer buffer to be read/written based on the request
  1024. * @param length length of the buffer
  1025. * @return returns 0 if successful else -1 on failure
  1026. */
  1027. static int _xhci_submit_bulk_msg(struct usb_device *udev, unsigned long pipe,
  1028. void *buffer, int length)
  1029. {
  1030. if (usb_pipetype(pipe) != PIPE_BULK) {
  1031. printf("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
  1032. return -EINVAL;
  1033. }
  1034. return xhci_bulk_tx(udev, pipe, length, buffer);
  1035. }
  1036. /**
  1037. * submit the control type of request to the Root hub/Device based on the devnum
  1038. *
  1039. * @param udev pointer to the USB device
  1040. * @param pipe contains the DIR_IN or OUT , devnum
  1041. * @param buffer buffer to be read/written based on the request
  1042. * @param length length of the buffer
  1043. * @param setup Request type
  1044. * @param root_portnr Root port number that this device is on
  1045. * @return returns 0 if successful else -1 on failure
  1046. */
  1047. static int _xhci_submit_control_msg(struct usb_device *udev, unsigned long pipe,
  1048. void *buffer, int length,
  1049. struct devrequest *setup, int root_portnr)
  1050. {
  1051. struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
  1052. int ret = 0;
  1053. if (usb_pipetype(pipe) != PIPE_CONTROL) {
  1054. printf("non-control pipe (type=%lu)", usb_pipetype(pipe));
  1055. return -EINVAL;
  1056. }
  1057. if (usb_pipedevice(pipe) == ctrl->rootdev)
  1058. return xhci_submit_root(udev, pipe, buffer, setup);
  1059. if (setup->request == USB_REQ_SET_ADDRESS &&
  1060. (setup->requesttype & USB_TYPE_MASK) == USB_TYPE_STANDARD)
  1061. return xhci_address_device(udev, root_portnr);
  1062. if (setup->request == USB_REQ_SET_CONFIGURATION &&
  1063. (setup->requesttype & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
  1064. ret = xhci_set_configuration(udev);
  1065. if (ret) {
  1066. puts("Failed to configure xHCI endpoint\n");
  1067. return ret;
  1068. }
  1069. }
  1070. return xhci_ctrl_tx(udev, pipe, setup, length, buffer);
  1071. }
  1072. static int xhci_lowlevel_init(struct xhci_ctrl *ctrl)
  1073. {
  1074. struct xhci_hccr *hccr;
  1075. struct xhci_hcor *hcor;
  1076. uint32_t val;
  1077. uint32_t val2;
  1078. uint32_t reg;
  1079. hccr = ctrl->hccr;
  1080. hcor = ctrl->hcor;
  1081. /*
  1082. * Program the Number of Device Slots Enabled field in the CONFIG
  1083. * register with the max value of slots the HC can handle.
  1084. */
  1085. val = (xhci_readl(&hccr->cr_hcsparams1) & HCS_SLOTS_MASK);
  1086. val2 = xhci_readl(&hcor->or_config);
  1087. val |= (val2 & ~HCS_SLOTS_MASK);
  1088. xhci_writel(&hcor->or_config, val);
  1089. /* initializing xhci data structures */
  1090. if (xhci_mem_init(ctrl, hccr, hcor) < 0)
  1091. return -ENOMEM;
  1092. reg = xhci_readl(&hccr->cr_hcsparams1);
  1093. descriptor.hub.bNbrPorts = ((reg & HCS_MAX_PORTS_MASK) >>
  1094. HCS_MAX_PORTS_SHIFT);
  1095. printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
  1096. /* Port Indicators */
  1097. reg = xhci_readl(&hccr->cr_hccparams);
  1098. if (HCS_INDICATOR(reg))
  1099. put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
  1100. | 0x80, &descriptor.hub.wHubCharacteristics);
  1101. /* Port Power Control */
  1102. if (HCC_PPC(reg))
  1103. put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
  1104. | 0x01, &descriptor.hub.wHubCharacteristics);
  1105. if (xhci_start(hcor)) {
  1106. xhci_reset(hcor);
  1107. return -ENODEV;
  1108. }
  1109. /* Zero'ing IRQ control register and IRQ pending register */
  1110. xhci_writel(&ctrl->ir_set->irq_control, 0x0);
  1111. xhci_writel(&ctrl->ir_set->irq_pending, 0x0);
  1112. reg = HC_VERSION(xhci_readl(&hccr->cr_capbase));
  1113. printf("USB XHCI %x.%02x\n", reg >> 8, reg & 0xff);
  1114. return 0;
  1115. }
  1116. static int xhci_lowlevel_stop(struct xhci_ctrl *ctrl)
  1117. {
  1118. u32 temp;
  1119. xhci_reset(ctrl->hcor);
  1120. debug("// Disabling event ring interrupts\n");
  1121. temp = xhci_readl(&ctrl->hcor->or_usbsts);
  1122. xhci_writel(&ctrl->hcor->or_usbsts, temp & ~STS_EINT);
  1123. temp = xhci_readl(&ctrl->ir_set->irq_pending);
  1124. xhci_writel(&ctrl->ir_set->irq_pending, ER_IRQ_DISABLE(temp));
  1125. return 0;
  1126. }
  1127. #if !CONFIG_IS_ENABLED(DM_USB)
  1128. int submit_control_msg(struct usb_device *udev, unsigned long pipe,
  1129. void *buffer, int length, struct devrequest *setup)
  1130. {
  1131. struct usb_device *hop = udev;
  1132. if (hop->parent)
  1133. while (hop->parent->parent)
  1134. hop = hop->parent;
  1135. return _xhci_submit_control_msg(udev, pipe, buffer, length, setup,
  1136. hop->portnr);
  1137. }
  1138. int submit_bulk_msg(struct usb_device *udev, unsigned long pipe, void *buffer,
  1139. int length)
  1140. {
  1141. return _xhci_submit_bulk_msg(udev, pipe, buffer, length);
  1142. }
  1143. int submit_int_msg(struct usb_device *udev, unsigned long pipe, void *buffer,
  1144. int length, int interval, bool nonblock)
  1145. {
  1146. return _xhci_submit_int_msg(udev, pipe, buffer, length, interval,
  1147. nonblock);
  1148. }
  1149. /**
  1150. * Intialises the XHCI host controller
  1151. * and allocates the necessary data structures
  1152. *
  1153. * @param index index to the host controller data structure
  1154. * @return pointer to the intialised controller
  1155. */
  1156. int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
  1157. {
  1158. struct xhci_hccr *hccr;
  1159. struct xhci_hcor *hcor;
  1160. struct xhci_ctrl *ctrl;
  1161. int ret;
  1162. *controller = NULL;
  1163. if (xhci_hcd_init(index, &hccr, (struct xhci_hcor **)&hcor) != 0)
  1164. return -ENODEV;
  1165. if (xhci_reset(hcor) != 0)
  1166. return -ENODEV;
  1167. ctrl = &xhcic[index];
  1168. ctrl->hccr = hccr;
  1169. ctrl->hcor = hcor;
  1170. ret = xhci_lowlevel_init(ctrl);
  1171. if (ret) {
  1172. ctrl->hccr = NULL;
  1173. ctrl->hcor = NULL;
  1174. } else {
  1175. *controller = &xhcic[index];
  1176. }
  1177. return ret;
  1178. }
  1179. /**
  1180. * Stops the XHCI host controller
  1181. * and cleans up all the related data structures
  1182. *
  1183. * @param index index to the host controller data structure
  1184. * @return none
  1185. */
  1186. int usb_lowlevel_stop(int index)
  1187. {
  1188. struct xhci_ctrl *ctrl = (xhcic + index);
  1189. if (ctrl->hcor) {
  1190. xhci_lowlevel_stop(ctrl);
  1191. xhci_hcd_stop(index);
  1192. xhci_cleanup(ctrl);
  1193. }
  1194. return 0;
  1195. }
  1196. #endif /* CONFIG_IS_ENABLED(DM_USB) */
  1197. #if CONFIG_IS_ENABLED(DM_USB)
  1198. static int xhci_submit_control_msg(struct udevice *dev, struct usb_device *udev,
  1199. unsigned long pipe, void *buffer, int length,
  1200. struct devrequest *setup)
  1201. {
  1202. struct usb_device *uhop;
  1203. struct udevice *hub;
  1204. int root_portnr = 0;
  1205. debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
  1206. dev->name, udev, udev->dev->name, udev->portnr);
  1207. hub = udev->dev;
  1208. if (device_get_uclass_id(hub) == UCLASS_USB_HUB) {
  1209. /* Figure out our port number on the root hub */
  1210. if (usb_hub_is_root_hub(hub)) {
  1211. root_portnr = udev->portnr;
  1212. } else {
  1213. while (!usb_hub_is_root_hub(hub->parent))
  1214. hub = hub->parent;
  1215. uhop = dev_get_parent_priv(hub);
  1216. root_portnr = uhop->portnr;
  1217. }
  1218. }
  1219. /*
  1220. struct usb_device *hop = udev;
  1221. if (hop->parent)
  1222. while (hop->parent->parent)
  1223. hop = hop->parent;
  1224. */
  1225. return _xhci_submit_control_msg(udev, pipe, buffer, length, setup,
  1226. root_portnr);
  1227. }
  1228. static int xhci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
  1229. unsigned long pipe, void *buffer, int length)
  1230. {
  1231. debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
  1232. return _xhci_submit_bulk_msg(udev, pipe, buffer, length);
  1233. }
  1234. static int xhci_submit_int_msg(struct udevice *dev, struct usb_device *udev,
  1235. unsigned long pipe, void *buffer, int length,
  1236. int interval, bool nonblock)
  1237. {
  1238. debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
  1239. return _xhci_submit_int_msg(udev, pipe, buffer, length, interval,
  1240. nonblock);
  1241. }
  1242. static int xhci_alloc_device(struct udevice *dev, struct usb_device *udev)
  1243. {
  1244. debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
  1245. return _xhci_alloc_device(udev);
  1246. }
  1247. static int xhci_update_hub_device(struct udevice *dev, struct usb_device *udev)
  1248. {
  1249. struct xhci_ctrl *ctrl = dev_get_priv(dev);
  1250. struct usb_hub_device *hub = dev_get_uclass_priv(udev->dev);
  1251. struct xhci_virt_device *virt_dev;
  1252. struct xhci_input_control_ctx *ctrl_ctx;
  1253. struct xhci_container_ctx *out_ctx;
  1254. struct xhci_container_ctx *in_ctx;
  1255. struct xhci_slot_ctx *slot_ctx;
  1256. int slot_id = udev->slot_id;
  1257. unsigned think_time;
  1258. debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
  1259. /* Ignore root hubs */
  1260. if (usb_hub_is_root_hub(udev->dev))
  1261. return 0;
  1262. virt_dev = ctrl->devs[slot_id];
  1263. BUG_ON(!virt_dev);
  1264. out_ctx = virt_dev->out_ctx;
  1265. in_ctx = virt_dev->in_ctx;
  1266. ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
  1267. /* Initialize the input context control */
  1268. ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
  1269. ctrl_ctx->drop_flags = 0;
  1270. xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size);
  1271. /* slot context */
  1272. xhci_slot_copy(ctrl, in_ctx, out_ctx);
  1273. slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx);
  1274. /* Update hub related fields */
  1275. slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
  1276. /*
  1277. * refer to section 6.2.2: MTT should be 0 for full speed hub,
  1278. * but it may be already set to 1 when setup an xHCI virtual
  1279. * device, so clear it anyway.
  1280. */
  1281. if (hub->tt.multi)
  1282. slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
  1283. else if (udev->speed == USB_SPEED_FULL)
  1284. slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
  1285. slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(udev->maxchild));
  1286. /*
  1287. * Set TT think time - convert from ns to FS bit times.
  1288. * Note 8 FS bit times == (8 bits / 12000000 bps) ~= 666ns
  1289. *
  1290. * 0 = 8 FS bit times, 1 = 16 FS bit times,
  1291. * 2 = 24 FS bit times, 3 = 32 FS bit times.
  1292. *
  1293. * This field shall be 0 if the device is not a high-spped hub.
  1294. */
  1295. think_time = hub->tt.think_time;
  1296. if (think_time != 0)
  1297. think_time = (think_time / 666) - 1;
  1298. if (udev->speed == USB_SPEED_HIGH)
  1299. slot_ctx->tt_info |= cpu_to_le32(TT_THINK_TIME(think_time));
  1300. slot_ctx->dev_state = 0;
  1301. return xhci_configure_endpoints(udev, false);
  1302. }
  1303. static int xhci_get_max_xfer_size(struct udevice *dev, size_t *size)
  1304. {
  1305. /*
  1306. * xHCD allocates one segment which includes 64 TRBs for each endpoint
  1307. * and the last TRB in this segment is configured as a link TRB to form
  1308. * a TRB ring. Each TRB can transfer up to 64K bytes, however data
  1309. * buffers referenced by transfer TRBs shall not span 64KB boundaries.
  1310. * Hence the maximum number of TRBs we can use in one transfer is 62.
  1311. */
  1312. *size = (TRBS_PER_SEGMENT - 2) * TRB_MAX_BUFF_SIZE;
  1313. return 0;
  1314. }
  1315. int xhci_register(struct udevice *dev, struct xhci_hccr *hccr,
  1316. struct xhci_hcor *hcor)
  1317. {
  1318. struct xhci_ctrl *ctrl = dev_get_priv(dev);
  1319. struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
  1320. int ret;
  1321. debug("%s: dev='%s', ctrl=%p, hccr=%p, hcor=%p\n", __func__, dev->name,
  1322. ctrl, hccr, hcor);
  1323. ctrl->dev = dev;
  1324. /*
  1325. * XHCI needs to issue a Address device command to setup
  1326. * proper device context structures, before it can interact
  1327. * with the device. So a get_descriptor will fail before any
  1328. * of that is done for XHCI unlike EHCI.
  1329. */
  1330. priv->desc_before_addr = false;
  1331. ret = xhci_reset(hcor);
  1332. if (ret)
  1333. goto err;
  1334. ctrl->hccr = hccr;
  1335. ctrl->hcor = hcor;
  1336. ret = xhci_lowlevel_init(ctrl);
  1337. if (ret)
  1338. goto err;
  1339. return 0;
  1340. err:
  1341. free(ctrl);
  1342. debug("%s: failed, ret=%d\n", __func__, ret);
  1343. return ret;
  1344. }
  1345. int xhci_deregister(struct udevice *dev)
  1346. {
  1347. struct xhci_ctrl *ctrl = dev_get_priv(dev);
  1348. xhci_lowlevel_stop(ctrl);
  1349. xhci_cleanup(ctrl);
  1350. return 0;
  1351. }
  1352. struct dm_usb_ops xhci_usb_ops = {
  1353. .control = xhci_submit_control_msg,
  1354. .bulk = xhci_submit_bulk_msg,
  1355. .interrupt = xhci_submit_int_msg,
  1356. .alloc_device = xhci_alloc_device,
  1357. .update_hub_device = xhci_update_hub_device,
  1358. .get_max_xfer_size = xhci_get_max_xfer_size,
  1359. };
  1360. #endif