xhci-rockchip.c 4.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2016 Rockchip, Inc.
  4. * Authors: Daniel Meng <daniel.meng@rock-chips.com>
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <malloc.h>
  9. #include <usb.h>
  10. #include <watchdog.h>
  11. #include <linux/errno.h>
  12. #include <linux/compat.h>
  13. #include <linux/usb/dwc3.h>
  14. #include <power/regulator.h>
  15. #include <usb/xhci.h>
  16. struct rockchip_xhci_platdata {
  17. fdt_addr_t hcd_base;
  18. struct udevice *vbus_supply;
  19. };
  20. /*
  21. * Contains pointers to register base addresses
  22. * for the usb controller.
  23. */
  24. struct rockchip_xhci {
  25. struct usb_platdata usb_plat;
  26. struct xhci_ctrl ctrl;
  27. struct xhci_hccr *hcd;
  28. struct dwc3 *dwc3_reg;
  29. };
  30. static int xhci_usb_ofdata_to_platdata(struct udevice *dev)
  31. {
  32. struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
  33. int ret = 0;
  34. /*
  35. * Get the base address for XHCI controller from the device node
  36. */
  37. plat->hcd_base = dev_read_addr(dev);
  38. if (plat->hcd_base == FDT_ADDR_T_NONE) {
  39. pr_err("Can't get the XHCI register base address\n");
  40. return -ENXIO;
  41. }
  42. /* Vbus regulator */
  43. ret = device_get_supply_regulator(dev, "vbus-supply",
  44. &plat->vbus_supply);
  45. if (ret)
  46. debug("Can't get VBus regulator!\n");
  47. return 0;
  48. }
  49. /*
  50. * rockchip_dwc3_phy_setup() - Configure USB PHY Interface of DWC3 Core
  51. * @dwc: Pointer to our controller context structure
  52. * @dev: Pointer to ulcass device
  53. */
  54. static void rockchip_dwc3_phy_setup(struct dwc3 *dwc3_reg,
  55. struct udevice *dev)
  56. {
  57. u32 reg;
  58. u32 utmi_bits;
  59. /* Set dwc3 usb2 phy config */
  60. reg = readl(&dwc3_reg->g_usb2phycfg[0]);
  61. if (dev_read_bool(dev, "snps,dis-enblslpm-quirk"))
  62. reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
  63. utmi_bits = dev_read_u32_default(dev, "snps,phyif-utmi-bits", -1);
  64. if (utmi_bits == 16) {
  65. reg |= DWC3_GUSB2PHYCFG_PHYIF;
  66. reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
  67. reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;
  68. } else if (utmi_bits == 8) {
  69. reg &= ~DWC3_GUSB2PHYCFG_PHYIF;
  70. reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
  71. reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT;
  72. }
  73. if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk"))
  74. reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
  75. if (dev_read_bool(dev, "snps,dis-u2-susphy-quirk"))
  76. reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
  77. writel(reg, &dwc3_reg->g_usb2phycfg[0]);
  78. }
  79. static int rockchip_xhci_core_init(struct rockchip_xhci *rkxhci,
  80. struct udevice *dev)
  81. {
  82. int ret;
  83. ret = dwc3_core_init(rkxhci->dwc3_reg);
  84. if (ret) {
  85. pr_err("failed to initialize core\n");
  86. return ret;
  87. }
  88. rockchip_dwc3_phy_setup(rkxhci->dwc3_reg, dev);
  89. /* We are hard-coding DWC3 core to Host Mode */
  90. dwc3_set_mode(rkxhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
  91. return 0;
  92. }
  93. static int rockchip_xhci_core_exit(struct rockchip_xhci *rkxhci)
  94. {
  95. return 0;
  96. }
  97. static int xhci_usb_probe(struct udevice *dev)
  98. {
  99. struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
  100. struct rockchip_xhci *ctx = dev_get_priv(dev);
  101. struct xhci_hcor *hcor;
  102. int ret;
  103. ctx->hcd = (struct xhci_hccr *)plat->hcd_base;
  104. ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
  105. hcor = (struct xhci_hcor *)((uint64_t)ctx->hcd +
  106. HC_LENGTH(xhci_readl(&ctx->hcd->cr_capbase)));
  107. if (plat->vbus_supply) {
  108. ret = regulator_set_enable(plat->vbus_supply, true);
  109. if (ret) {
  110. pr_err("XHCI: failed to set VBus supply\n");
  111. return ret;
  112. }
  113. }
  114. ret = rockchip_xhci_core_init(ctx, dev);
  115. if (ret) {
  116. pr_err("XHCI: failed to initialize controller\n");
  117. return ret;
  118. }
  119. return xhci_register(dev, ctx->hcd, hcor);
  120. }
  121. static int xhci_usb_remove(struct udevice *dev)
  122. {
  123. struct rockchip_xhci_platdata *plat = dev_get_platdata(dev);
  124. struct rockchip_xhci *ctx = dev_get_priv(dev);
  125. int ret;
  126. ret = xhci_deregister(dev);
  127. if (ret)
  128. return ret;
  129. ret = rockchip_xhci_core_exit(ctx);
  130. if (ret)
  131. return ret;
  132. if (plat->vbus_supply) {
  133. ret = regulator_set_enable(plat->vbus_supply, false);
  134. if (ret)
  135. pr_err("XHCI: failed to set VBus supply\n");
  136. }
  137. return ret;
  138. }
  139. static const struct udevice_id xhci_usb_ids[] = {
  140. { .compatible = "rockchip,rk3328-xhci" },
  141. { }
  142. };
  143. U_BOOT_DRIVER(usb_xhci) = {
  144. .name = "xhci_rockchip",
  145. .id = UCLASS_USB,
  146. .of_match = xhci_usb_ids,
  147. .ofdata_to_platdata = xhci_usb_ofdata_to_platdata,
  148. .probe = xhci_usb_probe,
  149. .remove = xhci_usb_remove,
  150. .ops = &xhci_usb_ops,
  151. .bind = dm_scan_fdt_dev,
  152. .platdata_auto_alloc_size = sizeof(struct rockchip_xhci_platdata),
  153. .priv_auto_alloc_size = sizeof(struct rockchip_xhci),
  154. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  155. };
  156. static const struct udevice_id usb_phy_ids[] = {
  157. { .compatible = "rockchip,rk3328-usb3-phy" },
  158. { }
  159. };
  160. U_BOOT_DRIVER(usb_phy) = {
  161. .name = "usb_phy_rockchip",
  162. .of_match = usb_phy_ids,
  163. };