xhci-mtk.c 6.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2019 MediaTek, Inc.
  4. * Authors: Chunfeng Yun <chunfeng.yun@mediatek.com>
  5. */
  6. #include <clk.h>
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <dm/devres.h>
  10. #include <generic-phy.h>
  11. #include <malloc.h>
  12. #include <usb.h>
  13. #include <linux/errno.h>
  14. #include <linux/compat.h>
  15. #include <power/regulator.h>
  16. #include <linux/iopoll.h>
  17. #include <usb/xhci.h>
  18. /* IPPC (IP Port Control) registers */
  19. #define IPPC_IP_PW_CTRL0 0x00
  20. #define CTRL0_IP_SW_RST BIT(0)
  21. #define IPPC_IP_PW_CTRL1 0x04
  22. #define CTRL1_IP_HOST_PDN BIT(0)
  23. #define IPPC_IP_PW_STS1 0x10
  24. #define STS1_IP_SLEEP_STS BIT(30)
  25. #define STS1_U3_MAC_RST BIT(16)
  26. #define STS1_XHCI_RST BIT(11)
  27. #define STS1_SYS125_RST BIT(10)
  28. #define STS1_REF_RST BIT(8)
  29. #define STS1_SYSPLL_STABLE BIT(0)
  30. #define IPPC_IP_XHCI_CAP 0x24
  31. #define CAP_U3_PORT_NUM(p) ((p) & 0xff)
  32. #define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff)
  33. #define IPPC_U3_CTRL_0P 0x30
  34. #define CTRL_U3_PORT_HOST_SEL BIT(2)
  35. #define CTRL_U3_PORT_PDN BIT(1)
  36. #define CTRL_U3_PORT_DIS BIT(0)
  37. #define IPPC_U2_CTRL_0P 0x50
  38. #define CTRL_U2_PORT_HOST_SEL BIT(2)
  39. #define CTRL_U2_PORT_PDN BIT(1)
  40. #define CTRL_U2_PORT_DIS BIT(0)
  41. #define IPPC_U3_CTRL(p) (IPPC_U3_CTRL_0P + ((p) * 0x08))
  42. #define IPPC_U2_CTRL(p) (IPPC_U2_CTRL_0P + ((p) * 0x08))
  43. struct mtk_xhci {
  44. struct xhci_ctrl ctrl; /* Needs to come first in this struct! */
  45. struct xhci_hccr *hcd;
  46. void __iomem *ippc;
  47. struct udevice *dev;
  48. struct udevice *vusb33_supply;
  49. struct udevice *vbus_supply;
  50. struct clk_bulk clks;
  51. struct phy_bulk phys;
  52. int num_u2ports;
  53. int num_u3ports;
  54. };
  55. static int xhci_mtk_host_enable(struct mtk_xhci *mtk)
  56. {
  57. u32 value;
  58. u32 check_val;
  59. int ret;
  60. int i;
  61. /* power on host ip */
  62. clrbits_le32(mtk->ippc + IPPC_IP_PW_CTRL1, CTRL1_IP_HOST_PDN);
  63. /* power on and enable all u3 ports */
  64. for (i = 0; i < mtk->num_u3ports; i++) {
  65. clrsetbits_le32(mtk->ippc + IPPC_U3_CTRL(i),
  66. CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS,
  67. CTRL_U3_PORT_HOST_SEL);
  68. }
  69. /* power on and enable all u2 ports */
  70. for (i = 0; i < mtk->num_u2ports; i++) {
  71. clrsetbits_le32(mtk->ippc + IPPC_U2_CTRL(i),
  72. CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS,
  73. CTRL_U2_PORT_HOST_SEL);
  74. }
  75. /*
  76. * wait for clocks to be stable, and clock domains reset to
  77. * be inactive after power on and enable ports
  78. */
  79. check_val = STS1_SYSPLL_STABLE | STS1_REF_RST |
  80. STS1_SYS125_RST | STS1_XHCI_RST;
  81. if (mtk->num_u3ports)
  82. check_val |= STS1_U3_MAC_RST;
  83. ret = readl_poll_timeout(mtk->ippc + IPPC_IP_PW_STS1, value,
  84. (check_val == (value & check_val)), 20000);
  85. if (ret)
  86. dev_err(mtk->dev, "clocks are not stable 0x%x!\n", value);
  87. return ret;
  88. }
  89. static int xhci_mtk_host_disable(struct mtk_xhci *mtk)
  90. {
  91. int i;
  92. /* power down all u3 ports */
  93. for (i = 0; i < mtk->num_u3ports; i++)
  94. setbits_le32(mtk->ippc + IPPC_U3_CTRL(i), CTRL_U3_PORT_PDN);
  95. /* power down all u2 ports */
  96. for (i = 0; i < mtk->num_u2ports; i++)
  97. setbits_le32(mtk->ippc + IPPC_U2_CTRL(i), CTRL_U2_PORT_PDN);
  98. /* power down host ip */
  99. setbits_le32(mtk->ippc + IPPC_IP_PW_CTRL1, CTRL1_IP_HOST_PDN);
  100. return 0;
  101. }
  102. static int xhci_mtk_ssusb_init(struct mtk_xhci *mtk)
  103. {
  104. u32 value;
  105. /* reset whole ip */
  106. setbits_le32(mtk->ippc + IPPC_IP_PW_CTRL0, CTRL0_IP_SW_RST);
  107. udelay(1);
  108. clrbits_le32(mtk->ippc + IPPC_IP_PW_CTRL0, CTRL0_IP_SW_RST);
  109. value = readl(mtk->ippc + IPPC_IP_XHCI_CAP);
  110. mtk->num_u3ports = CAP_U3_PORT_NUM(value);
  111. mtk->num_u2ports = CAP_U2_PORT_NUM(value);
  112. dev_info(mtk->dev, "u2p:%d, u3p:%d\n",
  113. mtk->num_u2ports, mtk->num_u3ports);
  114. return xhci_mtk_host_enable(mtk);
  115. }
  116. static int xhci_mtk_ofdata_get(struct mtk_xhci *mtk)
  117. {
  118. struct udevice *dev = mtk->dev;
  119. int ret = 0;
  120. mtk->hcd = devfdt_remap_addr_name(dev, "mac");
  121. if (!mtk->hcd) {
  122. dev_err(dev, "failed to get xHCI base address\n");
  123. return -ENXIO;
  124. }
  125. mtk->ippc = devfdt_remap_addr_name(dev, "ippc");
  126. if (!mtk->ippc) {
  127. dev_err(dev, "failed to get IPPC base address\n");
  128. return -ENXIO;
  129. }
  130. dev_info(dev, "hcd: 0x%p, ippc: 0x%p\n", mtk->hcd, mtk->ippc);
  131. ret = clk_get_bulk(dev, &mtk->clks);
  132. if (ret) {
  133. dev_err(dev, "failed to get clocks %d!\n", ret);
  134. return ret;
  135. }
  136. ret = device_get_supply_regulator(dev, "vusb33-supply",
  137. &mtk->vusb33_supply);
  138. if (ret)
  139. debug("can't get vusb33 regulator %d!\n", ret);
  140. ret = device_get_supply_regulator(dev, "vbus-supply",
  141. &mtk->vbus_supply);
  142. if (ret)
  143. debug("can't get vbus regulator %d!\n", ret);
  144. return 0;
  145. }
  146. static int xhci_mtk_ldos_enable(struct mtk_xhci *mtk)
  147. {
  148. int ret;
  149. ret = regulator_set_enable(mtk->vusb33_supply, true);
  150. if (ret < 0 && ret != -ENOSYS) {
  151. dev_err(mtk->dev, "failed to enable vusb33 %d!\n", ret);
  152. return ret;
  153. }
  154. ret = regulator_set_enable(mtk->vbus_supply, true);
  155. if (ret < 0 && ret != -ENOSYS) {
  156. dev_err(mtk->dev, "failed to enable vbus %d!\n", ret);
  157. regulator_set_enable(mtk->vusb33_supply, false);
  158. return ret;
  159. }
  160. return 0;
  161. }
  162. static void xhci_mtk_ldos_disable(struct mtk_xhci *mtk)
  163. {
  164. regulator_set_enable(mtk->vbus_supply, false);
  165. regulator_set_enable(mtk->vusb33_supply, false);
  166. }
  167. static int xhci_mtk_phy_setup(struct mtk_xhci *mtk)
  168. {
  169. struct udevice *dev = mtk->dev;
  170. struct phy_bulk *phys = &mtk->phys;
  171. int ret;
  172. ret = generic_phy_get_bulk(dev, phys);
  173. if (ret)
  174. return ret;
  175. ret = generic_phy_init_bulk(phys);
  176. if (ret)
  177. return ret;
  178. ret = generic_phy_power_on_bulk(phys);
  179. if (ret)
  180. generic_phy_exit_bulk(phys);
  181. return ret;
  182. }
  183. static void xhci_mtk_phy_shutdown(struct mtk_xhci *mtk)
  184. {
  185. generic_phy_power_off_bulk(&mtk->phys);
  186. generic_phy_exit_bulk(&mtk->phys);
  187. }
  188. static int xhci_mtk_probe(struct udevice *dev)
  189. {
  190. struct mtk_xhci *mtk = dev_get_priv(dev);
  191. struct xhci_hcor *hcor;
  192. int ret;
  193. mtk->dev = dev;
  194. ret = xhci_mtk_ofdata_get(mtk);
  195. if (ret)
  196. return ret;
  197. ret = xhci_mtk_ldos_enable(mtk);
  198. if (ret)
  199. goto ldos_err;
  200. ret = clk_enable_bulk(&mtk->clks);
  201. if (ret)
  202. goto clks_err;
  203. ret = xhci_mtk_phy_setup(mtk);
  204. if (ret)
  205. goto phys_err;
  206. ret = xhci_mtk_ssusb_init(mtk);
  207. if (ret)
  208. goto ssusb_init_err;
  209. hcor = (struct xhci_hcor *)((uintptr_t)mtk->hcd +
  210. HC_LENGTH(xhci_readl(&mtk->hcd->cr_capbase)));
  211. return xhci_register(dev, mtk->hcd, hcor);
  212. ssusb_init_err:
  213. xhci_mtk_phy_shutdown(mtk);
  214. phys_err:
  215. clk_disable_bulk(&mtk->clks);
  216. clks_err:
  217. xhci_mtk_ldos_disable(mtk);
  218. ldos_err:
  219. return ret;
  220. }
  221. static int xhci_mtk_remove(struct udevice *dev)
  222. {
  223. struct mtk_xhci *mtk = dev_get_priv(dev);
  224. xhci_deregister(dev);
  225. xhci_mtk_host_disable(mtk);
  226. xhci_mtk_ldos_disable(mtk);
  227. clk_disable_bulk(&mtk->clks);
  228. return 0;
  229. }
  230. static const struct udevice_id xhci_mtk_ids[] = {
  231. { .compatible = "mediatek,mtk-xhci" },
  232. { }
  233. };
  234. U_BOOT_DRIVER(usb_xhci) = {
  235. .name = "xhci-mtk",
  236. .id = UCLASS_USB,
  237. .of_match = xhci_mtk_ids,
  238. .probe = xhci_mtk_probe,
  239. .remove = xhci_mtk_remove,
  240. .ops = &xhci_usb_ops,
  241. .bind = dm_scan_fdt_dev,
  242. .priv_auto_alloc_size = sizeof(struct mtk_xhci),
  243. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  244. };