xhci-fsl.c 5.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2015,2016 Freescale Semiconductor, Inc.
  4. *
  5. * FSL USB HOST xHCI Controller
  6. *
  7. * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
  8. */
  9. #include <common.h>
  10. #include <usb.h>
  11. #include <linux/errno.h>
  12. #include <linux/compat.h>
  13. #include <linux/usb/xhci-fsl.h>
  14. #include <linux/usb/dwc3.h>
  15. #include <usb/xhci.h>
  16. #include <fsl_errata.h>
  17. #include <fsl_usb.h>
  18. #include <dm.h>
  19. /* Declare global data pointer */
  20. #if !CONFIG_IS_ENABLED(DM_USB)
  21. static struct fsl_xhci fsl_xhci;
  22. unsigned long ctr_addr[] = FSL_USB_XHCI_ADDR;
  23. #else
  24. struct xhci_fsl_priv {
  25. struct xhci_ctrl xhci;
  26. fdt_addr_t hcd_base;
  27. struct fsl_xhci ctx;
  28. };
  29. #endif
  30. __weak int __board_usb_init(int index, enum usb_init_type init)
  31. {
  32. return 0;
  33. }
  34. static int erratum_a008751(void)
  35. {
  36. #if defined(CONFIG_TARGET_LS2080AQDS) || defined(CONFIG_TARGET_LS2080ARDB) ||\
  37. defined(CONFIG_TARGET_LS2080AQDS)
  38. u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
  39. writel(SCFG_USB3PRM1CR_INIT, scfg + SCFG_USB3PRM1CR / 4);
  40. return 0;
  41. #endif
  42. return 1;
  43. }
  44. static void fsl_apply_xhci_errata(void)
  45. {
  46. int ret;
  47. if (has_erratum_a008751()) {
  48. ret = erratum_a008751();
  49. if (ret != 0)
  50. puts("Failed to apply erratum a008751\n");
  51. }
  52. }
  53. static void fsl_xhci_set_beat_burst_length(struct dwc3 *dwc3_reg)
  54. {
  55. clrsetbits_le32(&dwc3_reg->g_sbuscfg0, USB3_ENABLE_BEAT_BURST_MASK,
  56. USB3_ENABLE_BEAT_BURST);
  57. setbits_le32(&dwc3_reg->g_sbuscfg1, USB3_SET_BEAT_BURST_LIMIT);
  58. }
  59. static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
  60. {
  61. int ret = 0;
  62. ret = dwc3_core_init(fsl_xhci->dwc3_reg);
  63. if (ret) {
  64. debug("%s:failed to initialize core\n", __func__);
  65. return ret;
  66. }
  67. /* We are hard-coding DWC3 core to Host Mode */
  68. dwc3_set_mode(fsl_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
  69. /* Set GFLADJ_30MHZ as 20h as per XHCI spec default value */
  70. dwc3_set_fladj(fsl_xhci->dwc3_reg, GFLADJ_30MHZ_DEFAULT);
  71. /* Change beat burst and outstanding pipelined transfers requests */
  72. fsl_xhci_set_beat_burst_length(fsl_xhci->dwc3_reg);
  73. /*
  74. * A-010151: The dwc3 phy TSMC 28-nm HPM 0.9/1.8 V does not
  75. * reliably support Rx Detect in P3 mode(P3 is the default
  76. * setting). Therefore, some USB3.0 devices may not be detected
  77. * reliably in Super Speed mode. So, USB controller to configure
  78. * USB in P2 mode whenever the Receive Detect feature is required.
  79. * whenever the Receive Detect feature is required.
  80. */
  81. if (has_erratum_a010151())
  82. clrsetbits_le32(&fsl_xhci->dwc3_reg->g_usb3pipectl[0],
  83. DWC3_GUSB3PIPECTL_DISRXDETP3,
  84. DWC3_GUSB3PIPECTL_DISRXDETP3);
  85. return ret;
  86. }
  87. static int fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci)
  88. {
  89. /*
  90. * Currently fsl socs do not support PHY shutdown from
  91. * sw. But this support may be added in future socs.
  92. */
  93. return 0;
  94. }
  95. #if CONFIG_IS_ENABLED(DM_USB)
  96. static int xhci_fsl_probe(struct udevice *dev)
  97. {
  98. struct xhci_fsl_priv *priv = dev_get_priv(dev);
  99. struct xhci_hccr *hccr;
  100. struct xhci_hcor *hcor;
  101. int ret = 0;
  102. /*
  103. * Get the base address for XHCI controller from the device node
  104. */
  105. priv->hcd_base = devfdt_get_addr(dev);
  106. if (priv->hcd_base == FDT_ADDR_T_NONE) {
  107. debug("Can't get the XHCI register base address\n");
  108. return -ENXIO;
  109. }
  110. priv->ctx.hcd = (struct xhci_hccr *)priv->hcd_base;
  111. priv->ctx.dwc3_reg = (struct dwc3 *)((char *)(priv->hcd_base) +
  112. DWC3_REG_OFFSET);
  113. fsl_apply_xhci_errata();
  114. ret = fsl_xhci_core_init(&priv->ctx);
  115. if (ret < 0) {
  116. puts("Failed to initialize xhci\n");
  117. return ret;
  118. }
  119. hccr = (struct xhci_hccr *)(priv->ctx.hcd);
  120. hcor = (struct xhci_hcor *)((uintptr_t) hccr
  121. + HC_LENGTH(xhci_readl(&hccr->cr_capbase)));
  122. debug("xhci-fsl: init hccr %lx and hcor %lx hc_length %lx\n",
  123. (uintptr_t)hccr, (uintptr_t)hcor,
  124. (uintptr_t)HC_LENGTH(xhci_readl(&hccr->cr_capbase)));
  125. return xhci_register(dev, hccr, hcor);
  126. }
  127. static int xhci_fsl_remove(struct udevice *dev)
  128. {
  129. struct xhci_fsl_priv *priv = dev_get_priv(dev);
  130. fsl_xhci_core_exit(&priv->ctx);
  131. return xhci_deregister(dev);
  132. }
  133. static const struct udevice_id xhci_usb_ids[] = {
  134. { .compatible = "fsl,layerscape-dwc3", },
  135. { }
  136. };
  137. U_BOOT_DRIVER(xhci_fsl) = {
  138. .name = "xhci_fsl",
  139. .id = UCLASS_USB,
  140. .of_match = xhci_usb_ids,
  141. .probe = xhci_fsl_probe,
  142. .remove = xhci_fsl_remove,
  143. .ops = &xhci_usb_ops,
  144. .platdata_auto_alloc_size = sizeof(struct usb_platdata),
  145. .priv_auto_alloc_size = sizeof(struct xhci_fsl_priv),
  146. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  147. };
  148. #else
  149. int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
  150. {
  151. struct fsl_xhci *ctx = &fsl_xhci;
  152. int ret = 0;
  153. ctx->hcd = (struct xhci_hccr *)ctr_addr[index];
  154. ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
  155. ret = board_usb_init(index, USB_INIT_HOST);
  156. if (ret != 0) {
  157. puts("Failed to initialize board for USB\n");
  158. return ret;
  159. }
  160. fsl_apply_xhci_errata();
  161. ret = fsl_xhci_core_init(ctx);
  162. if (ret < 0) {
  163. puts("Failed to initialize xhci\n");
  164. return ret;
  165. }
  166. *hccr = (struct xhci_hccr *)ctx->hcd;
  167. *hcor = (struct xhci_hcor *)((uintptr_t) *hccr
  168. + HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
  169. debug("fsl-xhci: init hccr %lx and hcor %lx hc_length %lx\n",
  170. (uintptr_t)*hccr, (uintptr_t)*hcor,
  171. (uintptr_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
  172. return ret;
  173. }
  174. void xhci_hcd_stop(int index)
  175. {
  176. struct fsl_xhci *ctx = &fsl_xhci;
  177. fsl_xhci_core_exit(ctx);
  178. }
  179. #endif