xhci-dwc3.c 4.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2015 Freescale Semiconductor, Inc.
  4. *
  5. * DWC3 controller driver
  6. *
  7. * Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
  8. */
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <generic-phy.h>
  12. #include <usb.h>
  13. #include <dwc3-uboot.h>
  14. #include <usb/xhci.h>
  15. #include <asm/io.h>
  16. #include <linux/usb/dwc3.h>
  17. #include <linux/usb/otg.h>
  18. struct xhci_dwc3_platdata {
  19. struct phy_bulk *usb_phys;
  20. };
  21. void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
  22. {
  23. clrsetbits_le32(&dwc3_reg->g_ctl,
  24. DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
  25. DWC3_GCTL_PRTCAPDIR(mode));
  26. }
  27. static void dwc3_phy_reset(struct dwc3 *dwc3_reg)
  28. {
  29. /* Assert USB3 PHY reset */
  30. setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
  31. /* Assert USB2 PHY reset */
  32. setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
  33. mdelay(100);
  34. /* Clear USB3 PHY reset */
  35. clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
  36. /* Clear USB2 PHY reset */
  37. clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
  38. }
  39. void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
  40. {
  41. /* Before Resetting PHY, put Core in Reset */
  42. setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
  43. /* reset USB3 phy - if required */
  44. dwc3_phy_reset(dwc3_reg);
  45. mdelay(100);
  46. /* After PHYs are stable we can take Core out of reset state */
  47. clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
  48. }
  49. int dwc3_core_init(struct dwc3 *dwc3_reg)
  50. {
  51. u32 reg;
  52. u32 revision;
  53. unsigned int dwc3_hwparams1;
  54. revision = readl(&dwc3_reg->g_snpsid);
  55. /* This should read as U3 followed by revision number */
  56. if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
  57. puts("this is not a DesignWare USB3 DRD Core\n");
  58. return -1;
  59. }
  60. dwc3_core_soft_reset(dwc3_reg);
  61. dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
  62. reg = readl(&dwc3_reg->g_ctl);
  63. reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
  64. reg &= ~DWC3_GCTL_DISSCRAMBLE;
  65. switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
  66. case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
  67. reg &= ~DWC3_GCTL_DSBLCLKGTNG;
  68. break;
  69. default:
  70. debug("No power optimization available\n");
  71. }
  72. /*
  73. * WORKAROUND: DWC3 revisions <1.90a have a bug
  74. * where the device can fail to connect at SuperSpeed
  75. * and falls back to high-speed mode which causes
  76. * the device to enter a Connect/Disconnect loop
  77. */
  78. if ((revision & DWC3_REVISION_MASK) < 0x190a)
  79. reg |= DWC3_GCTL_U2RSTECN;
  80. writel(reg, &dwc3_reg->g_ctl);
  81. return 0;
  82. }
  83. void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val)
  84. {
  85. setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL |
  86. GFLADJ_30MHZ(val));
  87. }
  88. #if CONFIG_IS_ENABLED(DM_USB)
  89. static int xhci_dwc3_probe(struct udevice *dev)
  90. {
  91. struct xhci_hcor *hcor;
  92. struct xhci_hccr *hccr;
  93. struct dwc3 *dwc3_reg;
  94. enum usb_dr_mode dr_mode;
  95. struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
  96. const char *phy;
  97. u32 reg;
  98. int ret;
  99. hccr = (struct xhci_hccr *)((uintptr_t)dev_read_addr(dev));
  100. hcor = (struct xhci_hcor *)((uintptr_t)hccr +
  101. HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
  102. ret = dwc3_setup_phy(dev, plat->usb_phys);
  103. if (ret && (ret != -ENOTSUPP))
  104. return ret;
  105. dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET);
  106. dwc3_core_init(dwc3_reg);
  107. /* Set dwc3 usb2 phy config */
  108. reg = readl(&dwc3_reg->g_usb2phycfg[0]);
  109. phy = dev_read_string(dev, "phy_type");
  110. if (phy && strcmp(phy, "utmi_wide") == 0) {
  111. reg |= DWC3_GUSB2PHYCFG_PHYIF;
  112. reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
  113. reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT;
  114. }
  115. if (dev_read_bool(dev, "snps,dis_enblslpm-quirk"))
  116. reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
  117. if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk"))
  118. reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
  119. if (dev_read_bool(dev, "snps,dis_u2_susphy_quirk"))
  120. reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
  121. writel(reg, &dwc3_reg->g_usb2phycfg[0]);
  122. dr_mode = usb_get_dr_mode(dev->node);
  123. if (dr_mode == USB_DR_MODE_UNKNOWN)
  124. /* by default set dual role mode to HOST */
  125. dr_mode = USB_DR_MODE_HOST;
  126. dwc3_set_mode(dwc3_reg, dr_mode);
  127. return xhci_register(dev, hccr, hcor);
  128. }
  129. static int xhci_dwc3_remove(struct udevice *dev)
  130. {
  131. struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
  132. dwc3_shutdown_phy(dev, plat->usb_phys);
  133. return xhci_deregister(dev);
  134. }
  135. static const struct udevice_id xhci_dwc3_ids[] = {
  136. { .compatible = "snps,dwc3" },
  137. { }
  138. };
  139. U_BOOT_DRIVER(xhci_dwc3) = {
  140. .name = "xhci-dwc3",
  141. .id = UCLASS_USB,
  142. .of_match = xhci_dwc3_ids,
  143. .probe = xhci_dwc3_probe,
  144. .remove = xhci_dwc3_remove,
  145. .ops = &xhci_usb_ops,
  146. .priv_auto_alloc_size = sizeof(struct xhci_ctrl),
  147. .platdata_auto_alloc_size = sizeof(struct xhci_dwc3_platdata),
  148. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  149. };
  150. #endif