utmi-armada100.c 1.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2012
  4. * eInfochips Ltd. <www.einfochips.com>
  5. * Written-by: Ajay Bhargav <contact@8051projects.net>
  6. *
  7. * (C) Copyright 2009
  8. * Marvell Semiconductor <www.marvell.com>
  9. */
  10. #include <common.h>
  11. #include <asm/io.h>
  12. #include <usb.h>
  13. #include <asm/arch/cpu.h>
  14. #include <asm/arch/armada100.h>
  15. #include <asm/arch/utmi-armada100.h>
  16. static int utmi_phy_init(void)
  17. {
  18. struct armd1usb_phy_reg *phy_regs =
  19. (struct armd1usb_phy_reg *)UTMI_PHY_BASE;
  20. int timeout;
  21. setbits_le32(&phy_regs->utmi_ctrl, INPKT_DELAY_SOF | PLL_PWR_UP);
  22. udelay(1000);
  23. setbits_le32(&phy_regs->utmi_ctrl, PHY_PWR_UP);
  24. clrbits_le32(&phy_regs->utmi_pll, PLL_FBDIV_MASK | PLL_REFDIV_MASK);
  25. setbits_le32(&phy_regs->utmi_pll, N_DIVIDER << PLL_FBDIV | M_DIVIDER);
  26. setbits_le32(&phy_regs->utmi_tx, PHSEL_VAL << CK60_PHSEL);
  27. /* Calibrate pll */
  28. timeout = 10000;
  29. while (--timeout && ((readl(&phy_regs->utmi_pll) & PLL_READY) == 0))
  30. ;
  31. if (!timeout)
  32. return -1;
  33. udelay(200);
  34. setbits_le32(&phy_regs->utmi_pll, VCOCAL_START);
  35. udelay(400);
  36. clrbits_le32(&phy_regs->utmi_pll, VCOCAL_START);
  37. udelay(200);
  38. setbits_le32(&phy_regs->utmi_tx, RCAL_START);
  39. udelay(400);
  40. clrbits_le32(&phy_regs->utmi_tx, RCAL_START);
  41. timeout = 10000;
  42. while (--timeout && ((readl(&phy_regs->utmi_pll) & PLL_READY) == 0))
  43. ;
  44. if (!timeout)
  45. return -1;
  46. return 0;
  47. }
  48. /*
  49. * Initialize USB host controller's UTMI Physical interface
  50. */
  51. int utmi_init(void)
  52. {
  53. struct armd1mpmu_registers *mpmu_regs =
  54. (struct armd1mpmu_registers *)ARMD1_MPMU_BASE;
  55. struct armd1apmu_registers *apmu_regs =
  56. (struct armd1apmu_registers *)ARMD1_APMU_BASE;
  57. /* Turn on 26Mhz ref clock for UTMI PLL */
  58. setbits_le32(&mpmu_regs->acgr, APB2_26M_EN | AP_26M);
  59. /* USB Clock reset */
  60. writel(USB_SPH_AXICLK_EN, &apmu_regs->usbcrc);
  61. writel(USB_SPH_AXICLK_EN | USB_SPH_AXI_RST, &apmu_regs->usbcrc);
  62. /* Initialize UTMI transceiver */
  63. return utmi_phy_init();
  64. }