ohci.h 12 KB

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  1. /*
  2. * URB OHCI HCD (Host Controller Driver) for USB.
  3. *
  4. * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
  5. * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
  6. *
  7. * usb-ohci.h
  8. */
  9. /*
  10. * e.g. PCI controllers need this
  11. */
  12. #include <asm/io.h>
  13. #ifdef CONFIG_SYS_OHCI_SWAP_REG_ACCESS
  14. # define ohci_readl(a) __swap_32(in_be32((u32 *)a))
  15. # define ohci_writel(a, b) out_be32((u32 *)b, __swap_32(a))
  16. #else
  17. # define ohci_readl(a) readl(a)
  18. # define ohci_writel(v, a) writel(v, a)
  19. #endif /* CONFIG_SYS_OHCI_SWAP_REG_ACCESS */
  20. #if ARCH_DMA_MINALIGN > 16
  21. #define ED_ALIGNMENT ARCH_DMA_MINALIGN
  22. #else
  23. #define ED_ALIGNMENT 16
  24. #endif
  25. #if CONFIG_IS_ENABLED(DM_USB) && ARCH_DMA_MINALIGN > 32
  26. #define TD_ALIGNMENT ARCH_DMA_MINALIGN
  27. #else
  28. #define TD_ALIGNMENT 32
  29. #endif
  30. /* functions for doing board or CPU specific setup/cleanup */
  31. int usb_board_stop(void);
  32. int usb_cpu_init(void);
  33. int usb_cpu_stop(void);
  34. int usb_cpu_init_fail(void);
  35. /* ED States */
  36. #define ED_NEW 0x00
  37. #define ED_UNLINK 0x01
  38. #define ED_OPER 0x02
  39. #define ED_DEL 0x04
  40. #define ED_URB_DEL 0x08
  41. /* usb_ohci_ed */
  42. struct ed {
  43. __u32 hwINFO;
  44. __u32 hwTailP;
  45. __u32 hwHeadP;
  46. __u32 hwNextED;
  47. struct ed *ed_prev;
  48. __u8 int_period;
  49. __u8 int_branch;
  50. __u8 int_load;
  51. __u8 int_interval;
  52. __u8 state;
  53. __u8 type;
  54. __u16 last_iso;
  55. struct ed *ed_rm_list;
  56. struct usb_device *usb_dev;
  57. void *purb;
  58. __u32 unused[2];
  59. } __attribute__((aligned(ED_ALIGNMENT)));
  60. typedef struct ed ed_t;
  61. /* TD info field */
  62. #define TD_CC 0xf0000000
  63. #define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
  64. #define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
  65. #define TD_EC 0x0C000000
  66. #define TD_T 0x03000000
  67. #define TD_T_DATA0 0x02000000
  68. #define TD_T_DATA1 0x03000000
  69. #define TD_T_TOGGLE 0x00000000
  70. #define TD_R 0x00040000
  71. #define TD_DI 0x00E00000
  72. #define TD_DI_SET(X) (((X) & 0x07)<< 21)
  73. #define TD_DP 0x00180000
  74. #define TD_DP_SETUP 0x00000000
  75. #define TD_DP_IN 0x00100000
  76. #define TD_DP_OUT 0x00080000
  77. #define TD_ISO 0x00010000
  78. #define TD_DEL 0x00020000
  79. /* CC Codes */
  80. #define TD_CC_NOERROR 0x00
  81. #define TD_CC_CRC 0x01
  82. #define TD_CC_BITSTUFFING 0x02
  83. #define TD_CC_DATATOGGLEM 0x03
  84. #define TD_CC_STALL 0x04
  85. #define TD_DEVNOTRESP 0x05
  86. #define TD_PIDCHECKFAIL 0x06
  87. #define TD_UNEXPECTEDPID 0x07
  88. #define TD_DATAOVERRUN 0x08
  89. #define TD_DATAUNDERRUN 0x09
  90. #define TD_BUFFEROVERRUN 0x0C
  91. #define TD_BUFFERUNDERRUN 0x0D
  92. #define TD_NOTACCESSED 0x0F
  93. #define MAXPSW 1
  94. struct td {
  95. __u32 hwINFO;
  96. __u32 hwCBP; /* Current Buffer Pointer */
  97. __u32 hwNextTD; /* Next TD Pointer */
  98. __u32 hwBE; /* Memory Buffer End Pointer */
  99. __u16 hwPSW[MAXPSW];
  100. __u8 unused;
  101. __u8 index;
  102. struct ed *ed;
  103. struct td *next_dl_td;
  104. struct usb_device *usb_dev;
  105. int transfer_len;
  106. __u32 data;
  107. __u32 unused2[2];
  108. } __attribute__((aligned(TD_ALIGNMENT)));
  109. typedef struct td td_t;
  110. #define OHCI_ED_SKIP (1 << 14)
  111. /*
  112. * The HCCA (Host Controller Communications Area) is a 256 byte
  113. * structure defined in the OHCI spec. that the host controller is
  114. * told the base address of. It must be 256-byte aligned.
  115. */
  116. #define NUM_INTS 32 /* part of the OHCI standard */
  117. struct ohci_hcca {
  118. __u32 int_table[NUM_INTS]; /* Interrupt ED table */
  119. __u16 frame_no; /* current frame number */
  120. __u16 pad1; /* set to 0 on each frame_no change */
  121. __u32 done_head; /* info returned for an interrupt */
  122. u8 reserved_for_hc[116];
  123. } __attribute__((aligned(256)));
  124. /*
  125. * Maximum number of root hub ports.
  126. */
  127. #ifndef CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS
  128. # error "CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS undefined!"
  129. #endif
  130. /*
  131. * This is the structure of the OHCI controller's memory mapped I/O
  132. * region. This is Memory Mapped I/O. You must use the ohci_readl() and
  133. * ohci_writel() macros defined in this file to access these!!
  134. */
  135. struct ohci_regs {
  136. /* control and status registers */
  137. __u32 revision;
  138. __u32 control;
  139. __u32 cmdstatus;
  140. __u32 intrstatus;
  141. __u32 intrenable;
  142. __u32 intrdisable;
  143. /* memory pointers */
  144. __u32 hcca;
  145. __u32 ed_periodcurrent;
  146. __u32 ed_controlhead;
  147. __u32 ed_controlcurrent;
  148. __u32 ed_bulkhead;
  149. __u32 ed_bulkcurrent;
  150. __u32 donehead;
  151. /* frame counters */
  152. __u32 fminterval;
  153. __u32 fmremaining;
  154. __u32 fmnumber;
  155. __u32 periodicstart;
  156. __u32 lsthresh;
  157. /* Root hub ports */
  158. struct ohci_roothub_regs {
  159. __u32 a;
  160. __u32 b;
  161. __u32 status;
  162. __u32 portstatus[CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS];
  163. } roothub;
  164. } __attribute__((aligned(32)));
  165. /* Some EHCI controls */
  166. #define EHCI_USBCMD_OFF 0x20
  167. #define EHCI_USBCMD_HCRESET (1 << 1)
  168. /* OHCI CONTROL AND STATUS REGISTER MASKS */
  169. /*
  170. * HcControl (control) register masks
  171. */
  172. #define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */
  173. #define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */
  174. #define OHCI_CTRL_IE (1 << 3) /* isochronous enable */
  175. #define OHCI_CTRL_CLE (1 << 4) /* control list enable */
  176. #define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */
  177. #define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */
  178. #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
  179. #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
  180. #define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */
  181. /* pre-shifted values for HCFS */
  182. # define OHCI_USB_RESET (0 << 6)
  183. # define OHCI_USB_RESUME (1 << 6)
  184. # define OHCI_USB_OPER (2 << 6)
  185. # define OHCI_USB_SUSPEND (3 << 6)
  186. /*
  187. * HcCommandStatus (cmdstatus) register masks
  188. */
  189. #define OHCI_HCR (1 << 0) /* host controller reset */
  190. #define OHCI_CLF (1 << 1) /* control list filled */
  191. #define OHCI_BLF (1 << 2) /* bulk list filled */
  192. #define OHCI_OCR (1 << 3) /* ownership change request */
  193. #define OHCI_SOC (3 << 16) /* scheduling overrun count */
  194. /*
  195. * masks used with interrupt registers:
  196. * HcInterruptStatus (intrstatus)
  197. * HcInterruptEnable (intrenable)
  198. * HcInterruptDisable (intrdisable)
  199. */
  200. #define OHCI_INTR_SO (1 << 0) /* scheduling overrun */
  201. #define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */
  202. #define OHCI_INTR_SF (1 << 2) /* start frame */
  203. #define OHCI_INTR_RD (1 << 3) /* resume detect */
  204. #define OHCI_INTR_UE (1 << 4) /* unrecoverable error */
  205. #define OHCI_INTR_FNO (1 << 5) /* frame number overflow */
  206. #define OHCI_INTR_RHSC (1 << 6) /* root hub status change */
  207. #define OHCI_INTR_OC (1 << 30) /* ownership change */
  208. #define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
  209. /* Virtual Root HUB */
  210. struct virt_root_hub {
  211. int devnum; /* Address of Root Hub endpoint */
  212. void *dev; /* was urb */
  213. void *int_addr;
  214. int send;
  215. int interval;
  216. };
  217. /* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
  218. /* destination of request */
  219. #define RH_INTERFACE 0x01
  220. #define RH_ENDPOINT 0x02
  221. #define RH_OTHER 0x03
  222. #define RH_CLASS 0x20
  223. #define RH_VENDOR 0x40
  224. /* Requests: bRequest << 8 | bmRequestType */
  225. #define RH_GET_STATUS 0x0080
  226. #define RH_CLEAR_FEATURE 0x0100
  227. #define RH_SET_FEATURE 0x0300
  228. #define RH_SET_ADDRESS 0x0500
  229. #define RH_GET_DESCRIPTOR 0x0680
  230. #define RH_SET_DESCRIPTOR 0x0700
  231. #define RH_GET_CONFIGURATION 0x0880
  232. #define RH_SET_CONFIGURATION 0x0900
  233. #define RH_GET_STATE 0x0280
  234. #define RH_GET_INTERFACE 0x0A80
  235. #define RH_SET_INTERFACE 0x0B00
  236. #define RH_SYNC_FRAME 0x0C80
  237. /* Our Vendor Specific Request */
  238. #define RH_SET_EP 0x2000
  239. /* Hub port features */
  240. #define RH_PORT_CONNECTION 0x00
  241. #define RH_PORT_ENABLE 0x01
  242. #define RH_PORT_SUSPEND 0x02
  243. #define RH_PORT_OVER_CURRENT 0x03
  244. #define RH_PORT_RESET 0x04
  245. #define RH_PORT_POWER 0x08
  246. #define RH_PORT_LOW_SPEED 0x09
  247. #define RH_C_PORT_CONNECTION 0x10
  248. #define RH_C_PORT_ENABLE 0x11
  249. #define RH_C_PORT_SUSPEND 0x12
  250. #define RH_C_PORT_OVER_CURRENT 0x13
  251. #define RH_C_PORT_RESET 0x14
  252. /* Hub features */
  253. #define RH_C_HUB_LOCAL_POWER 0x00
  254. #define RH_C_HUB_OVER_CURRENT 0x01
  255. #define RH_DEVICE_REMOTE_WAKEUP 0x00
  256. #define RH_ENDPOINT_STALL 0x01
  257. #define RH_ACK 0x01
  258. #define RH_REQ_ERR -1
  259. #define RH_NACK 0x00
  260. /* OHCI ROOT HUB REGISTER MASKS */
  261. /* roothub.portstatus [i] bits */
  262. #define RH_PS_CCS 0x00000001 /* current connect status */
  263. #define RH_PS_PES 0x00000002 /* port enable status*/
  264. #define RH_PS_PSS 0x00000004 /* port suspend status */
  265. #define RH_PS_POCI 0x00000008 /* port over current indicator */
  266. #define RH_PS_PRS 0x00000010 /* port reset status */
  267. #define RH_PS_PPS 0x00000100 /* port power status */
  268. #define RH_PS_LSDA 0x00000200 /* low speed device attached */
  269. #define RH_PS_CSC 0x00010000 /* connect status change */
  270. #define RH_PS_PESC 0x00020000 /* port enable status change */
  271. #define RH_PS_PSSC 0x00040000 /* port suspend status change */
  272. #define RH_PS_OCIC 0x00080000 /* over current indicator change */
  273. #define RH_PS_PRSC 0x00100000 /* port reset status change */
  274. /* roothub.status bits */
  275. #define RH_HS_LPS 0x00000001 /* local power status */
  276. #define RH_HS_OCI 0x00000002 /* over current indicator */
  277. #define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
  278. #define RH_HS_LPSC 0x00010000 /* local power status change */
  279. #define RH_HS_OCIC 0x00020000 /* over current indicator change */
  280. #define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
  281. /* roothub.b masks */
  282. #define RH_B_DR 0x0000ffff /* device removable flags */
  283. #define RH_B_PPCM 0xffff0000 /* port power control mask */
  284. /* roothub.a masks */
  285. #define RH_A_NDP (0xff << 0) /* number of downstream ports */
  286. #define RH_A_PSM (1 << 8) /* power switching mode */
  287. #define RH_A_NPS (1 << 9) /* no power switching */
  288. #define RH_A_DT (1 << 10) /* device type (mbz) */
  289. #define RH_A_OCPM (1 << 11) /* over current protection mode */
  290. #define RH_A_NOCP (1 << 12) /* no over current protection */
  291. #define RH_A_POTPGT (0xff << 24) /* power on to power good time */
  292. /* urb */
  293. #define N_URB_TD 48
  294. typedef struct
  295. {
  296. ed_t *ed;
  297. __u16 length; /* number of tds associated with this request */
  298. __u16 td_cnt; /* number of tds already serviced */
  299. struct usb_device *dev;
  300. int state;
  301. unsigned long pipe;
  302. void *transfer_buffer;
  303. int transfer_buffer_length;
  304. int interval;
  305. int actual_length;
  306. int finished;
  307. td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */
  308. } urb_priv_t;
  309. #define URB_DEL 1
  310. #define NUM_EDS 32 /* num of preallocated endpoint descriptors */
  311. #define NUM_TD 64 /* we need more TDs than EDs */
  312. #define NUM_INT_DEVS 8 /* num of ohci_dev structs for int endpoints */
  313. typedef struct ohci_device {
  314. ed_t ed[NUM_EDS] __aligned(ED_ALIGNMENT);
  315. td_t tds[NUM_TD] __aligned(TD_ALIGNMENT);
  316. int ed_cnt;
  317. int devnum;
  318. } ohci_dev_t;
  319. /*
  320. * This is the full ohci controller description
  321. *
  322. * Note how the "proper" USB information is just
  323. * a subset of what the full implementation needs. (Linus)
  324. */
  325. typedef struct ohci {
  326. /* this allocates EDs for all possible endpoints */
  327. struct ohci_device ohci_dev __aligned(TD_ALIGNMENT);
  328. struct ohci_device int_dev[NUM_INT_DEVS] __aligned(TD_ALIGNMENT);
  329. struct ohci_hcca *hcca; /* hcca */
  330. /*dma_addr_t hcca_dma;*/
  331. int irq;
  332. int disabled; /* e.g. got a UE, we're hung */
  333. int sleeping;
  334. unsigned long flags; /* for HC bugs */
  335. struct ohci_regs *regs; /* OHCI controller's memory */
  336. int ohci_int_load[32]; /* load of the 32 Interrupt Chains (for load balancing)*/
  337. ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */
  338. ed_t *ed_bulktail; /* last endpoint of bulk list */
  339. ed_t *ed_controltail; /* last endpoint of control list */
  340. int intrstatus;
  341. __u32 hc_control; /* copy of the hc control reg */
  342. struct usb_device *dev[32];
  343. struct virt_root_hub rh;
  344. const char *slot_name;
  345. } ohci_t;
  346. #if CONFIG_IS_ENABLED(DM_USB)
  347. extern struct dm_usb_ops ohci_usb_ops;
  348. int ohci_register(struct udevice *dev, struct ohci_regs *regs);
  349. int ohci_deregister(struct udevice *dev);
  350. #endif