ohci-hcd.c 58 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200 and PCI bus.
  4. *
  5. * Interrupt support is added. Now, it has been tested
  6. * on ULI1575 chip and works well with USB keyboard.
  7. *
  8. * (C) Copyright 2007
  9. * Zhang Wei, Freescale Semiconductor, Inc. <wei.zhang@freescale.com>
  10. *
  11. * (C) Copyright 2003
  12. * Gary Jennejohn, DENX Software Engineering <garyj@denx.de>
  13. *
  14. * Note: Much of this code has been derived from Linux 2.4
  15. * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
  16. * (C) Copyright 2000-2002 David Brownell
  17. *
  18. * Modified for the MP2USB by (C) Copyright 2005 Eric Benard
  19. * ebenard@eukrea.com - based on s3c24x0's driver
  20. */
  21. /*
  22. * IMPORTANT NOTES
  23. * 1 - Read doc/README.generic_usb_ohci
  24. * 2 - this driver is intended for use with USB Mass Storage Devices
  25. * (BBB) and USB keyboard. There is NO support for Isochronous pipes!
  26. * 2 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG
  27. * to activate workaround for bug #41 or this driver will NOT work!
  28. */
  29. #include <common.h>
  30. #include <cpu_func.h>
  31. #include <asm/byteorder.h>
  32. #include <dm.h>
  33. #include <errno.h>
  34. #if defined(CONFIG_PCI_OHCI)
  35. # include <pci.h>
  36. #if !defined(CONFIG_PCI_OHCI_DEVNO)
  37. #define CONFIG_PCI_OHCI_DEVNO 0
  38. #endif
  39. #endif
  40. #include <malloc.h>
  41. #include <memalign.h>
  42. #include <usb.h>
  43. #include "ohci.h"
  44. #ifdef CONFIG_AT91RM9200
  45. #include <asm/arch/hardware.h> /* needed for AT91_USB_HOST_BASE */
  46. #endif
  47. #if defined(CONFIG_CPU_ARM920T) || \
  48. defined(CONFIG_PCI_OHCI) || \
  49. defined(CONFIG_DM_PCI) || \
  50. defined(CONFIG_SYS_OHCI_USE_NPS)
  51. # define OHCI_USE_NPS /* force NoPowerSwitching mode */
  52. #endif
  53. #undef OHCI_VERBOSE_DEBUG /* not always helpful */
  54. #undef DEBUG
  55. #undef SHOW_INFO
  56. #undef OHCI_FILL_TRACE
  57. /* For initializing controller (mask in an HCFS mode too) */
  58. #define OHCI_CONTROL_INIT \
  59. (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
  60. #if !CONFIG_IS_ENABLED(DM_USB)
  61. #ifdef CONFIG_PCI_OHCI
  62. static struct pci_device_id ohci_pci_ids[] = {
  63. {0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */
  64. {0x1033, 0x0035}, /* NEC PCI OHCI module ids */
  65. {0x1131, 0x1561}, /* Philips 1561 PCI OHCI module ids */
  66. /* Please add supported PCI OHCI controller ids here */
  67. {0, 0}
  68. };
  69. #endif
  70. #endif
  71. #ifdef CONFIG_PCI_EHCI_DEVNO
  72. static struct pci_device_id ehci_pci_ids[] = {
  73. {0x1131, 0x1562}, /* Philips 1562 PCI EHCI module ids */
  74. /* Please add supported PCI EHCI controller ids here */
  75. {0, 0}
  76. };
  77. #endif
  78. #ifdef DEBUG
  79. #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
  80. #else
  81. #define dbg(format, arg...) do {} while (0)
  82. #endif /* DEBUG */
  83. #define err(format, arg...) printf("ERROR: " format "\n", ## arg)
  84. #ifdef SHOW_INFO
  85. #define info(format, arg...) printf("INFO: " format "\n", ## arg)
  86. #else
  87. #define info(format, arg...) do {} while (0)
  88. #endif
  89. #ifdef CONFIG_SYS_OHCI_BE_CONTROLLER
  90. # define m16_swap(x) cpu_to_be16(x)
  91. # define m32_swap(x) cpu_to_be32(x)
  92. #else
  93. # define m16_swap(x) cpu_to_le16(x)
  94. # define m32_swap(x) cpu_to_le32(x)
  95. #endif /* CONFIG_SYS_OHCI_BE_CONTROLLER */
  96. /* We really should do proper cache flushing everywhere */
  97. #define flush_dcache_buffer(addr, size) \
  98. flush_dcache_range((unsigned long)(addr), \
  99. ALIGN((unsigned long)(addr) + size, ARCH_DMA_MINALIGN))
  100. #define invalidate_dcache_buffer(addr, size) \
  101. invalidate_dcache_range((unsigned long)(addr), \
  102. ALIGN((unsigned long)(addr) + size, ARCH_DMA_MINALIGN))
  103. /* Do not use sizeof(ed / td) as our ed / td structs contain extra members */
  104. #define flush_dcache_ed(addr) flush_dcache_buffer(addr, 16)
  105. #define flush_dcache_td(addr) flush_dcache_buffer(addr, 16)
  106. #define flush_dcache_iso_td(addr) flush_dcache_buffer(addr, 32)
  107. #define flush_dcache_hcca(addr) flush_dcache_buffer(addr, 256)
  108. #define invalidate_dcache_ed(addr) invalidate_dcache_buffer(addr, 16)
  109. #define invalidate_dcache_td(addr) invalidate_dcache_buffer(addr, 16)
  110. #define invalidate_dcache_iso_td(addr) invalidate_dcache_buffer(addr, 32)
  111. #define invalidate_dcache_hcca(addr) invalidate_dcache_buffer(addr, 256)
  112. #if CONFIG_IS_ENABLED(DM_USB)
  113. /*
  114. * The various ohci_mdelay(1) calls in the code seem unnecessary. We keep
  115. * them around when building for older boards not yet converted to the dm
  116. * just in case (to avoid regressions), for dm this turns them into nops.
  117. */
  118. #define ohci_mdelay(x)
  119. #else
  120. #define ohci_mdelay(x) mdelay(x)
  121. #endif
  122. #if !CONFIG_IS_ENABLED(DM_USB)
  123. /* global ohci_t */
  124. static ohci_t gohci;
  125. /* this must be aligned to a 256 byte boundary */
  126. struct ohci_hcca ghcca[1];
  127. #endif
  128. /* mapping of the OHCI CC status to error codes */
  129. static int cc_to_error[16] = {
  130. /* No Error */ 0,
  131. /* CRC Error */ USB_ST_CRC_ERR,
  132. /* Bit Stuff */ USB_ST_BIT_ERR,
  133. /* Data Togg */ USB_ST_CRC_ERR,
  134. /* Stall */ USB_ST_STALLED,
  135. /* DevNotResp */ -1,
  136. /* PIDCheck */ USB_ST_BIT_ERR,
  137. /* UnExpPID */ USB_ST_BIT_ERR,
  138. /* DataOver */ USB_ST_BUF_ERR,
  139. /* DataUnder */ USB_ST_BUF_ERR,
  140. /* reservd */ -1,
  141. /* reservd */ -1,
  142. /* BufferOver */ USB_ST_BUF_ERR,
  143. /* BuffUnder */ USB_ST_BUF_ERR,
  144. /* Not Access */ -1,
  145. /* Not Access */ -1
  146. };
  147. static const char *cc_to_string[16] = {
  148. "No Error",
  149. "CRC: Last data packet from endpoint contained a CRC error.",
  150. "BITSTUFFING: Last data packet from endpoint contained a bit " \
  151. "stuffing violation",
  152. "DATATOGGLEMISMATCH: Last packet from endpoint had data toggle PID\n" \
  153. "that did not match the expected value.",
  154. "STALL: TD was moved to the Done Queue because the endpoint returned" \
  155. " a STALL PID",
  156. "DEVICENOTRESPONDING: Device did not respond to token (IN) or did\n" \
  157. "not provide a handshake (OUT)",
  158. "PIDCHECKFAILURE: Check bits on PID from endpoint failed on data PID\n"\
  159. "(IN) or handshake (OUT)",
  160. "UNEXPECTEDPID: Receive PID was not valid when encountered or PID\n" \
  161. "value is not defined.",
  162. "DATAOVERRUN: The amount of data returned by the endpoint exceeded\n" \
  163. "either the size of the maximum data packet allowed\n" \
  164. "from the endpoint (found in MaximumPacketSize field\n" \
  165. "of ED) or the remaining buffer size.",
  166. "DATAUNDERRUN: The endpoint returned less than MaximumPacketSize\n" \
  167. "and that amount was not sufficient to fill the\n" \
  168. "specified buffer",
  169. "reserved1",
  170. "reserved2",
  171. "BUFFEROVERRUN: During an IN, HC received data from endpoint faster\n" \
  172. "than it could be written to system memory",
  173. "BUFFERUNDERRUN: During an OUT, HC could not retrieve data from\n" \
  174. "system memory fast enough to keep up with data USB " \
  175. "data rate.",
  176. "NOT ACCESSED: This code is set by software before the TD is placed" \
  177. "on a list to be processed by the HC.(1)",
  178. "NOT ACCESSED: This code is set by software before the TD is placed" \
  179. "on a list to be processed by the HC.(2)",
  180. };
  181. static inline u32 roothub_a(struct ohci *hc)
  182. { return ohci_readl(&hc->regs->roothub.a); }
  183. static inline u32 roothub_b(struct ohci *hc)
  184. { return ohci_readl(&hc->regs->roothub.b); }
  185. static inline u32 roothub_status(struct ohci *hc)
  186. { return ohci_readl(&hc->regs->roothub.status); }
  187. static inline u32 roothub_portstatus(struct ohci *hc, int i)
  188. { return ohci_readl(&hc->regs->roothub.portstatus[i]); }
  189. /* forward declaration */
  190. static int hc_interrupt(ohci_t *ohci);
  191. static void td_submit_job(ohci_t *ohci, struct usb_device *dev,
  192. unsigned long pipe, void *buffer, int transfer_len,
  193. struct devrequest *setup, urb_priv_t *urb,
  194. int interval);
  195. static int ep_link(ohci_t * ohci, ed_t * ed);
  196. static int ep_unlink(ohci_t * ohci, ed_t * ed);
  197. static ed_t *ep_add_ed(ohci_dev_t *ohci_dev, struct usb_device *usb_dev,
  198. unsigned long pipe, int interval, int load);
  199. /*-------------------------------------------------------------------------*/
  200. /* TDs ... */
  201. static struct td *td_alloc(ohci_dev_t *ohci_dev, struct usb_device *usb_dev)
  202. {
  203. int i;
  204. struct td *td;
  205. td = NULL;
  206. for (i = 0; i < NUM_TD; i++)
  207. {
  208. if (ohci_dev->tds[i].usb_dev == NULL)
  209. {
  210. td = &ohci_dev->tds[i];
  211. td->usb_dev = usb_dev;
  212. break;
  213. }
  214. }
  215. return td;
  216. }
  217. static inline void ed_free(struct ed *ed)
  218. {
  219. ed->usb_dev = NULL;
  220. }
  221. /*-------------------------------------------------------------------------*
  222. * URB support functions
  223. *-------------------------------------------------------------------------*/
  224. /* free HCD-private data associated with this URB */
  225. static void urb_free_priv(urb_priv_t *urb)
  226. {
  227. int i;
  228. int last;
  229. struct td *td;
  230. last = urb->length - 1;
  231. if (last >= 0) {
  232. for (i = 0; i <= last; i++) {
  233. td = urb->td[i];
  234. if (td) {
  235. td->usb_dev = NULL;
  236. urb->td[i] = NULL;
  237. }
  238. }
  239. }
  240. free(urb);
  241. }
  242. /*-------------------------------------------------------------------------*/
  243. #ifdef DEBUG
  244. static int sohci_get_current_frame_number(ohci_t *ohci);
  245. /* debug| print the main components of an URB
  246. * small: 0) header + data packets 1) just header */
  247. static void pkt_print(ohci_t *ohci, urb_priv_t *purb, struct usb_device *dev,
  248. unsigned long pipe, void *buffer, int transfer_len,
  249. struct devrequest *setup, char *str, int small)
  250. {
  251. dbg("%s URB:[%4x] dev:%2lu,ep:%2lu-%c,type:%s,len:%d/%d stat:%#lx",
  252. str,
  253. sohci_get_current_frame_number(ohci),
  254. usb_pipedevice(pipe),
  255. usb_pipeendpoint(pipe),
  256. usb_pipeout(pipe)? 'O': 'I',
  257. usb_pipetype(pipe) < 2 ? \
  258. (usb_pipeint(pipe)? "INTR": "ISOC"): \
  259. (usb_pipecontrol(pipe)? "CTRL": "BULK"),
  260. (purb ? purb->actual_length : 0),
  261. transfer_len, dev->status);
  262. #ifdef OHCI_VERBOSE_DEBUG
  263. if (!small) {
  264. int i, len;
  265. if (usb_pipecontrol(pipe)) {
  266. printf(__FILE__ ": cmd(8):");
  267. for (i = 0; i < 8 ; i++)
  268. printf(" %02x", ((__u8 *) setup) [i]);
  269. printf("\n");
  270. }
  271. if (transfer_len > 0 && buffer) {
  272. printf(__FILE__ ": data(%d/%d):",
  273. (purb ? purb->actual_length : 0),
  274. transfer_len);
  275. len = usb_pipeout(pipe)? transfer_len:
  276. (purb ? purb->actual_length : 0);
  277. for (i = 0; i < 16 && i < len; i++)
  278. printf(" %02x", ((__u8 *) buffer) [i]);
  279. printf("%s\n", i < len? "...": "");
  280. }
  281. }
  282. #endif
  283. }
  284. /* just for debugging; prints non-empty branches of the int ed tree
  285. * inclusive iso eds */
  286. void ep_print_int_eds(ohci_t *ohci, char *str)
  287. {
  288. int i, j;
  289. __u32 *ed_p;
  290. for (i = 0; i < 32; i++) {
  291. j = 5;
  292. ed_p = &(ohci->hcca->int_table [i]);
  293. if (*ed_p == 0)
  294. continue;
  295. invalidate_dcache_ed(ed_p);
  296. printf(__FILE__ ": %s branch int %2d(%2x):", str, i, i);
  297. while (*ed_p != 0 && j--) {
  298. ed_t *ed = (ed_t *)m32_swap(ed_p);
  299. invalidate_dcache_ed(ed);
  300. printf(" ed: %4x;", ed->hwINFO);
  301. ed_p = &ed->hwNextED;
  302. }
  303. printf("\n");
  304. }
  305. }
  306. static void ohci_dump_intr_mask(char *label, __u32 mask)
  307. {
  308. dbg("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
  309. label,
  310. mask,
  311. (mask & OHCI_INTR_MIE) ? " MIE" : "",
  312. (mask & OHCI_INTR_OC) ? " OC" : "",
  313. (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
  314. (mask & OHCI_INTR_FNO) ? " FNO" : "",
  315. (mask & OHCI_INTR_UE) ? " UE" : "",
  316. (mask & OHCI_INTR_RD) ? " RD" : "",
  317. (mask & OHCI_INTR_SF) ? " SF" : "",
  318. (mask & OHCI_INTR_WDH) ? " WDH" : "",
  319. (mask & OHCI_INTR_SO) ? " SO" : ""
  320. );
  321. }
  322. static void maybe_print_eds(char *label, __u32 value)
  323. {
  324. ed_t *edp = (ed_t *)value;
  325. if (value) {
  326. dbg("%s %08x", label, value);
  327. invalidate_dcache_ed(edp);
  328. dbg("%08x", edp->hwINFO);
  329. dbg("%08x", edp->hwTailP);
  330. dbg("%08x", edp->hwHeadP);
  331. dbg("%08x", edp->hwNextED);
  332. }
  333. }
  334. static char *hcfs2string(int state)
  335. {
  336. switch (state) {
  337. case OHCI_USB_RESET: return "reset";
  338. case OHCI_USB_RESUME: return "resume";
  339. case OHCI_USB_OPER: return "operational";
  340. case OHCI_USB_SUSPEND: return "suspend";
  341. }
  342. return "?";
  343. }
  344. /* dump control and status registers */
  345. static void ohci_dump_status(ohci_t *controller)
  346. {
  347. struct ohci_regs *regs = controller->regs;
  348. __u32 temp;
  349. temp = ohci_readl(&regs->revision) & 0xff;
  350. if (temp != 0x10)
  351. dbg("spec %d.%d", (temp >> 4), (temp & 0x0f));
  352. temp = ohci_readl(&regs->control);
  353. dbg("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
  354. (temp & OHCI_CTRL_RWE) ? " RWE" : "",
  355. (temp & OHCI_CTRL_RWC) ? " RWC" : "",
  356. (temp & OHCI_CTRL_IR) ? " IR" : "",
  357. hcfs2string(temp & OHCI_CTRL_HCFS),
  358. (temp & OHCI_CTRL_BLE) ? " BLE" : "",
  359. (temp & OHCI_CTRL_CLE) ? " CLE" : "",
  360. (temp & OHCI_CTRL_IE) ? " IE" : "",
  361. (temp & OHCI_CTRL_PLE) ? " PLE" : "",
  362. temp & OHCI_CTRL_CBSR
  363. );
  364. temp = ohci_readl(&regs->cmdstatus);
  365. dbg("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
  366. (temp & OHCI_SOC) >> 16,
  367. (temp & OHCI_OCR) ? " OCR" : "",
  368. (temp & OHCI_BLF) ? " BLF" : "",
  369. (temp & OHCI_CLF) ? " CLF" : "",
  370. (temp & OHCI_HCR) ? " HCR" : ""
  371. );
  372. ohci_dump_intr_mask("intrstatus", ohci_readl(&regs->intrstatus));
  373. ohci_dump_intr_mask("intrenable", ohci_readl(&regs->intrenable));
  374. maybe_print_eds("ed_periodcurrent",
  375. ohci_readl(&regs->ed_periodcurrent));
  376. maybe_print_eds("ed_controlhead", ohci_readl(&regs->ed_controlhead));
  377. maybe_print_eds("ed_controlcurrent",
  378. ohci_readl(&regs->ed_controlcurrent));
  379. maybe_print_eds("ed_bulkhead", ohci_readl(&regs->ed_bulkhead));
  380. maybe_print_eds("ed_bulkcurrent", ohci_readl(&regs->ed_bulkcurrent));
  381. maybe_print_eds("donehead", ohci_readl(&regs->donehead));
  382. }
  383. static void ohci_dump_roothub(ohci_t *controller, int verbose)
  384. {
  385. __u32 temp, ndp, i;
  386. temp = roothub_a(controller);
  387. ndp = (temp & RH_A_NDP);
  388. #ifdef CONFIG_AT91C_PQFP_UHPBUG
  389. ndp = (ndp == 2) ? 1:0;
  390. #endif
  391. if (verbose) {
  392. dbg("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
  393. ((temp & RH_A_POTPGT) >> 24) & 0xff,
  394. (temp & RH_A_NOCP) ? " NOCP" : "",
  395. (temp & RH_A_OCPM) ? " OCPM" : "",
  396. (temp & RH_A_DT) ? " DT" : "",
  397. (temp & RH_A_NPS) ? " NPS" : "",
  398. (temp & RH_A_PSM) ? " PSM" : "",
  399. ndp
  400. );
  401. temp = roothub_b(controller);
  402. dbg("roothub.b: %08x PPCM=%04x DR=%04x",
  403. temp,
  404. (temp & RH_B_PPCM) >> 16,
  405. (temp & RH_B_DR)
  406. );
  407. temp = roothub_status(controller);
  408. dbg("roothub.status: %08x%s%s%s%s%s%s",
  409. temp,
  410. (temp & RH_HS_CRWE) ? " CRWE" : "",
  411. (temp & RH_HS_OCIC) ? " OCIC" : "",
  412. (temp & RH_HS_LPSC) ? " LPSC" : "",
  413. (temp & RH_HS_DRWE) ? " DRWE" : "",
  414. (temp & RH_HS_OCI) ? " OCI" : "",
  415. (temp & RH_HS_LPS) ? " LPS" : ""
  416. );
  417. }
  418. for (i = 0; i < ndp; i++) {
  419. temp = roothub_portstatus(controller, i);
  420. dbg("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
  421. i,
  422. temp,
  423. (temp & RH_PS_PRSC) ? " PRSC" : "",
  424. (temp & RH_PS_OCIC) ? " OCIC" : "",
  425. (temp & RH_PS_PSSC) ? " PSSC" : "",
  426. (temp & RH_PS_PESC) ? " PESC" : "",
  427. (temp & RH_PS_CSC) ? " CSC" : "",
  428. (temp & RH_PS_LSDA) ? " LSDA" : "",
  429. (temp & RH_PS_PPS) ? " PPS" : "",
  430. (temp & RH_PS_PRS) ? " PRS" : "",
  431. (temp & RH_PS_POCI) ? " POCI" : "",
  432. (temp & RH_PS_PSS) ? " PSS" : "",
  433. (temp & RH_PS_PES) ? " PES" : "",
  434. (temp & RH_PS_CCS) ? " CCS" : ""
  435. );
  436. }
  437. }
  438. static void ohci_dump(ohci_t *controller, int verbose)
  439. {
  440. dbg("OHCI controller usb-%s state", controller->slot_name);
  441. /* dumps some of the state we know about */
  442. ohci_dump_status(controller);
  443. if (verbose)
  444. ep_print_int_eds(controller, "hcca");
  445. invalidate_dcache_hcca(controller->hcca);
  446. dbg("hcca frame #%04x", controller->hcca->frame_no);
  447. ohci_dump_roothub(controller, 1);
  448. }
  449. #endif /* DEBUG */
  450. /*-------------------------------------------------------------------------*
  451. * Interface functions (URB)
  452. *-------------------------------------------------------------------------*/
  453. /* get a transfer request */
  454. int sohci_submit_job(ohci_t *ohci, ohci_dev_t *ohci_dev, urb_priv_t *urb,
  455. struct devrequest *setup)
  456. {
  457. ed_t *ed;
  458. urb_priv_t *purb_priv = urb;
  459. int i, size = 0;
  460. struct usb_device *dev = urb->dev;
  461. unsigned long pipe = urb->pipe;
  462. void *buffer = urb->transfer_buffer;
  463. int transfer_len = urb->transfer_buffer_length;
  464. int interval = urb->interval;
  465. /* when controller's hung, permit only roothub cleanup attempts
  466. * such as powering down ports */
  467. if (ohci->disabled) {
  468. err("sohci_submit_job: EPIPE");
  469. return -1;
  470. }
  471. /* we're about to begin a new transaction here so mark the
  472. * URB unfinished */
  473. urb->finished = 0;
  474. /* every endpoint has a ed, locate and fill it */
  475. ed = ep_add_ed(ohci_dev, dev, pipe, interval, 1);
  476. if (!ed) {
  477. err("sohci_submit_job: ENOMEM");
  478. return -1;
  479. }
  480. /* for the private part of the URB we need the number of TDs (size) */
  481. switch (usb_pipetype(pipe)) {
  482. case PIPE_BULK: /* one TD for every 4096 Byte */
  483. size = (transfer_len - 1) / 4096 + 1;
  484. break;
  485. case PIPE_CONTROL:/* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
  486. size = (transfer_len == 0)? 2:
  487. (transfer_len - 1) / 4096 + 3;
  488. break;
  489. case PIPE_INTERRUPT: /* 1 TD */
  490. size = 1;
  491. break;
  492. }
  493. ed->purb = urb;
  494. if (size >= (N_URB_TD - 1)) {
  495. err("need %d TDs, only have %d", size, N_URB_TD);
  496. return -1;
  497. }
  498. purb_priv->pipe = pipe;
  499. /* fill the private part of the URB */
  500. purb_priv->length = size;
  501. purb_priv->ed = ed;
  502. purb_priv->actual_length = 0;
  503. /* allocate the TDs */
  504. /* note that td[0] was allocated in ep_add_ed */
  505. for (i = 0; i < size; i++) {
  506. purb_priv->td[i] = td_alloc(ohci_dev, dev);
  507. if (!purb_priv->td[i]) {
  508. purb_priv->length = i;
  509. urb_free_priv(purb_priv);
  510. err("sohci_submit_job: ENOMEM");
  511. return -1;
  512. }
  513. }
  514. if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
  515. urb_free_priv(purb_priv);
  516. err("sohci_submit_job: EINVAL");
  517. return -1;
  518. }
  519. /* link the ed into a chain if is not already */
  520. if (ed->state != ED_OPER)
  521. ep_link(ohci, ed);
  522. /* fill the TDs and link it to the ed */
  523. td_submit_job(ohci, dev, pipe, buffer, transfer_len,
  524. setup, purb_priv, interval);
  525. return 0;
  526. }
  527. /*-------------------------------------------------------------------------*/
  528. #ifdef DEBUG
  529. /* tell us the current USB frame number */
  530. static int sohci_get_current_frame_number(ohci_t *ohci)
  531. {
  532. invalidate_dcache_hcca(ohci->hcca);
  533. return m16_swap(ohci->hcca->frame_no);
  534. }
  535. #endif
  536. /*-------------------------------------------------------------------------*
  537. * ED handling functions
  538. *-------------------------------------------------------------------------*/
  539. /* search for the right branch to insert an interrupt ed into the int tree
  540. * do some load ballancing;
  541. * returns the branch and
  542. * sets the interval to interval = 2^integer (ld (interval)) */
  543. static int ep_int_ballance(ohci_t *ohci, int interval, int load)
  544. {
  545. int i, branch = 0;
  546. /* search for the least loaded interrupt endpoint
  547. * branch of all 32 branches
  548. */
  549. for (i = 0; i < 32; i++)
  550. if (ohci->ohci_int_load [branch] > ohci->ohci_int_load [i])
  551. branch = i;
  552. branch = branch % interval;
  553. for (i = branch; i < 32; i += interval)
  554. ohci->ohci_int_load [i] += load;
  555. return branch;
  556. }
  557. /*-------------------------------------------------------------------------*/
  558. /* 2^int( ld (inter)) */
  559. static int ep_2_n_interval(int inter)
  560. {
  561. int i;
  562. for (i = 0; ((inter >> i) > 1) && (i < 5); i++);
  563. return 1 << i;
  564. }
  565. /*-------------------------------------------------------------------------*/
  566. /* the int tree is a binary tree
  567. * in order to process it sequentially the indexes of the branches have to
  568. * be mapped the mapping reverses the bits of a word of num_bits length */
  569. static int ep_rev(int num_bits, int word)
  570. {
  571. int i, wout = 0;
  572. for (i = 0; i < num_bits; i++)
  573. wout |= (((word >> i) & 1) << (num_bits - i - 1));
  574. return wout;
  575. }
  576. /*-------------------------------------------------------------------------*
  577. * ED handling functions
  578. *-------------------------------------------------------------------------*/
  579. /* link an ed into one of the HC chains */
  580. static int ep_link(ohci_t *ohci, ed_t *edi)
  581. {
  582. volatile ed_t *ed = edi;
  583. int int_branch;
  584. int i;
  585. int inter;
  586. int interval;
  587. int load;
  588. __u32 *ed_p;
  589. ed->state = ED_OPER;
  590. ed->int_interval = 0;
  591. switch (ed->type) {
  592. case PIPE_CONTROL:
  593. ed->hwNextED = 0;
  594. flush_dcache_ed(ed);
  595. if (ohci->ed_controltail == NULL)
  596. ohci_writel((uintptr_t)ed, &ohci->regs->ed_controlhead);
  597. else
  598. ohci->ed_controltail->hwNextED =
  599. m32_swap((unsigned long)ed);
  600. ed->ed_prev = ohci->ed_controltail;
  601. if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
  602. !ohci->ed_rm_list[1] && !ohci->sleeping) {
  603. ohci->hc_control |= OHCI_CTRL_CLE;
  604. ohci_writel(ohci->hc_control, &ohci->regs->control);
  605. }
  606. ohci->ed_controltail = edi;
  607. break;
  608. case PIPE_BULK:
  609. ed->hwNextED = 0;
  610. flush_dcache_ed(ed);
  611. if (ohci->ed_bulktail == NULL)
  612. ohci_writel((uintptr_t)ed, &ohci->regs->ed_bulkhead);
  613. else
  614. ohci->ed_bulktail->hwNextED =
  615. m32_swap((unsigned long)ed);
  616. ed->ed_prev = ohci->ed_bulktail;
  617. if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
  618. !ohci->ed_rm_list[1] && !ohci->sleeping) {
  619. ohci->hc_control |= OHCI_CTRL_BLE;
  620. ohci_writel(ohci->hc_control, &ohci->regs->control);
  621. }
  622. ohci->ed_bulktail = edi;
  623. break;
  624. case PIPE_INTERRUPT:
  625. load = ed->int_load;
  626. interval = ep_2_n_interval(ed->int_period);
  627. ed->int_interval = interval;
  628. int_branch = ep_int_ballance(ohci, interval, load);
  629. ed->int_branch = int_branch;
  630. for (i = 0; i < ep_rev(6, interval); i += inter) {
  631. inter = 1;
  632. for (ed_p = &(ohci->hcca->int_table[\
  633. ep_rev(5, i) + int_branch]);
  634. (*ed_p != 0) &&
  635. (((ed_t *)ed_p)->int_interval >= interval);
  636. ed_p = &(((ed_t *)ed_p)->hwNextED))
  637. inter = ep_rev(6,
  638. ((ed_t *)ed_p)->int_interval);
  639. ed->hwNextED = *ed_p;
  640. flush_dcache_ed(ed);
  641. *ed_p = m32_swap((unsigned long)ed);
  642. flush_dcache_hcca(ohci->hcca);
  643. }
  644. break;
  645. }
  646. return 0;
  647. }
  648. /*-------------------------------------------------------------------------*/
  649. /* scan the periodic table to find and unlink this ED */
  650. static void periodic_unlink(struct ohci *ohci, volatile struct ed *ed,
  651. unsigned index, unsigned period)
  652. {
  653. __maybe_unused unsigned long aligned_ed_p;
  654. for (; index < NUM_INTS; index += period) {
  655. __u32 *ed_p = &ohci->hcca->int_table [index];
  656. /* ED might have been unlinked through another path */
  657. while (*ed_p != 0) {
  658. if (((struct ed *)(uintptr_t)
  659. m32_swap((unsigned long)ed_p)) == ed) {
  660. *ed_p = ed->hwNextED;
  661. aligned_ed_p = (unsigned long)ed_p;
  662. aligned_ed_p &= ~(ARCH_DMA_MINALIGN - 1);
  663. flush_dcache_range(aligned_ed_p,
  664. aligned_ed_p + ARCH_DMA_MINALIGN);
  665. break;
  666. }
  667. ed_p = &(((struct ed *)(uintptr_t)
  668. m32_swap((unsigned long)ed_p))->hwNextED);
  669. }
  670. }
  671. }
  672. /* unlink an ed from one of the HC chains.
  673. * just the link to the ed is unlinked.
  674. * the link from the ed still points to another operational ed or 0
  675. * so the HC can eventually finish the processing of the unlinked ed */
  676. static int ep_unlink(ohci_t *ohci, ed_t *edi)
  677. {
  678. volatile ed_t *ed = edi;
  679. int i;
  680. ed->hwINFO |= m32_swap(OHCI_ED_SKIP);
  681. flush_dcache_ed(ed);
  682. switch (ed->type) {
  683. case PIPE_CONTROL:
  684. if (ed->ed_prev == NULL) {
  685. if (!ed->hwNextED) {
  686. ohci->hc_control &= ~OHCI_CTRL_CLE;
  687. ohci_writel(ohci->hc_control,
  688. &ohci->regs->control);
  689. }
  690. ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)),
  691. &ohci->regs->ed_controlhead);
  692. } else {
  693. ed->ed_prev->hwNextED = ed->hwNextED;
  694. flush_dcache_ed(ed->ed_prev);
  695. }
  696. if (ohci->ed_controltail == ed) {
  697. ohci->ed_controltail = ed->ed_prev;
  698. } else {
  699. ((ed_t *)(uintptr_t)m32_swap(
  700. *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
  701. }
  702. break;
  703. case PIPE_BULK:
  704. if (ed->ed_prev == NULL) {
  705. if (!ed->hwNextED) {
  706. ohci->hc_control &= ~OHCI_CTRL_BLE;
  707. ohci_writel(ohci->hc_control,
  708. &ohci->regs->control);
  709. }
  710. ohci_writel(m32_swap(*((__u32 *)&ed->hwNextED)),
  711. &ohci->regs->ed_bulkhead);
  712. } else {
  713. ed->ed_prev->hwNextED = ed->hwNextED;
  714. flush_dcache_ed(ed->ed_prev);
  715. }
  716. if (ohci->ed_bulktail == ed) {
  717. ohci->ed_bulktail = ed->ed_prev;
  718. } else {
  719. ((ed_t *)(uintptr_t)m32_swap(
  720. *((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
  721. }
  722. break;
  723. case PIPE_INTERRUPT:
  724. periodic_unlink(ohci, ed, 0, 1);
  725. for (i = ed->int_branch; i < 32; i += ed->int_interval)
  726. ohci->ohci_int_load[i] -= ed->int_load;
  727. break;
  728. }
  729. ed->state = ED_UNLINK;
  730. return 0;
  731. }
  732. /*-------------------------------------------------------------------------*/
  733. /* add/reinit an endpoint; this should be done once at the
  734. * usb_set_configuration command, but the USB stack is a little bit
  735. * stateless so we do it at every transaction if the state of the ed
  736. * is ED_NEW then a dummy td is added and the state is changed to
  737. * ED_UNLINK in all other cases the state is left unchanged the ed
  738. * info fields are setted anyway even though most of them should not
  739. * change
  740. */
  741. static ed_t *ep_add_ed(ohci_dev_t *ohci_dev, struct usb_device *usb_dev,
  742. unsigned long pipe, int interval, int load)
  743. {
  744. td_t *td;
  745. ed_t *ed_ret;
  746. volatile ed_t *ed;
  747. ed = ed_ret = &ohci_dev->ed[(usb_pipeendpoint(pipe) << 1) |
  748. (usb_pipecontrol(pipe)? 0: usb_pipeout(pipe))];
  749. if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
  750. err("ep_add_ed: pending delete");
  751. /* pending delete request */
  752. return NULL;
  753. }
  754. if (ed->state == ED_NEW) {
  755. /* dummy td; end of td list for ed */
  756. td = td_alloc(ohci_dev, usb_dev);
  757. ed->hwTailP = m32_swap((unsigned long)td);
  758. ed->hwHeadP = ed->hwTailP;
  759. ed->state = ED_UNLINK;
  760. ed->type = usb_pipetype(pipe);
  761. ohci_dev->ed_cnt++;
  762. }
  763. ed->hwINFO = m32_swap(usb_pipedevice(pipe)
  764. | usb_pipeendpoint(pipe) << 7
  765. | (usb_pipeisoc(pipe)? 0x8000: 0)
  766. | (usb_pipecontrol(pipe)? 0: \
  767. (usb_pipeout(pipe)? 0x800: 0x1000))
  768. | (usb_dev->speed == USB_SPEED_LOW) << 13
  769. | usb_maxpacket(usb_dev, pipe) << 16);
  770. if (ed->type == PIPE_INTERRUPT && ed->state == ED_UNLINK) {
  771. ed->int_period = interval;
  772. ed->int_load = load;
  773. }
  774. flush_dcache_ed(ed);
  775. return ed_ret;
  776. }
  777. /*-------------------------------------------------------------------------*
  778. * TD handling functions
  779. *-------------------------------------------------------------------------*/
  780. /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
  781. static void td_fill(ohci_t *ohci, unsigned int info,
  782. void *data, int len,
  783. struct usb_device *dev, int index, urb_priv_t *urb_priv)
  784. {
  785. volatile td_t *td, *td_pt;
  786. #ifdef OHCI_FILL_TRACE
  787. int i;
  788. #endif
  789. if (index > urb_priv->length) {
  790. err("index > length");
  791. return;
  792. }
  793. /* use this td as the next dummy */
  794. td_pt = urb_priv->td [index];
  795. td_pt->hwNextTD = 0;
  796. flush_dcache_td(td_pt);
  797. /* fill the old dummy TD */
  798. td = urb_priv->td [index] =
  799. (td_t *)(uintptr_t)
  800. (m32_swap(urb_priv->ed->hwTailP) & ~0xf);
  801. td->ed = urb_priv->ed;
  802. td->next_dl_td = NULL;
  803. td->index = index;
  804. td->data = (uintptr_t)data;
  805. #ifdef OHCI_FILL_TRACE
  806. if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) {
  807. for (i = 0; i < len; i++)
  808. printf("td->data[%d] %#2x ", i, ((unsigned char *)td->data)[i]);
  809. printf("\n");
  810. }
  811. #endif
  812. if (!len)
  813. data = 0;
  814. td->hwINFO = m32_swap(info);
  815. td->hwCBP = m32_swap((unsigned long)data);
  816. if (data)
  817. td->hwBE = m32_swap((unsigned long)(data + len - 1));
  818. else
  819. td->hwBE = 0;
  820. td->hwNextTD = m32_swap((unsigned long)td_pt);
  821. flush_dcache_td(td);
  822. /* append to queue */
  823. td->ed->hwTailP = td->hwNextTD;
  824. flush_dcache_ed(td->ed);
  825. }
  826. /*-------------------------------------------------------------------------*/
  827. /* prepare all TDs of a transfer */
  828. static void td_submit_job(ohci_t *ohci, struct usb_device *dev,
  829. unsigned long pipe, void *buffer, int transfer_len,
  830. struct devrequest *setup, urb_priv_t *urb,
  831. int interval)
  832. {
  833. int data_len = transfer_len;
  834. void *data;
  835. int cnt = 0;
  836. __u32 info = 0;
  837. unsigned int toggle = 0;
  838. flush_dcache_buffer(buffer, data_len);
  839. /* OHCI handles the DATA-toggles itself, we just use the USB-toggle
  840. * bits for resetting */
  841. if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
  842. toggle = TD_T_TOGGLE;
  843. } else {
  844. toggle = TD_T_DATA0;
  845. usb_settoggle(dev, usb_pipeendpoint(pipe),
  846. usb_pipeout(pipe), 1);
  847. }
  848. urb->td_cnt = 0;
  849. if (data_len)
  850. data = buffer;
  851. else
  852. data = 0;
  853. switch (usb_pipetype(pipe)) {
  854. case PIPE_BULK:
  855. info = usb_pipeout(pipe)?
  856. TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
  857. while (data_len > 4096) {
  858. td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle),
  859. data, 4096, dev, cnt, urb);
  860. data += 4096; data_len -= 4096; cnt++;
  861. }
  862. info = usb_pipeout(pipe)?
  863. TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
  864. td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle), data,
  865. data_len, dev, cnt, urb);
  866. cnt++;
  867. if (!ohci->sleeping) {
  868. /* start bulk list */
  869. ohci_writel(OHCI_BLF, &ohci->regs->cmdstatus);
  870. }
  871. break;
  872. case PIPE_CONTROL:
  873. /* Setup phase */
  874. info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
  875. flush_dcache_buffer(setup, 8);
  876. td_fill(ohci, info, setup, 8, dev, cnt++, urb);
  877. /* Optional Data phase */
  878. if (data_len > 0) {
  879. info = usb_pipeout(pipe)?
  880. TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 :
  881. TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
  882. /* NOTE: mishandles transfers >8K, some >4K */
  883. td_fill(ohci, info, data, data_len, dev, cnt++, urb);
  884. }
  885. /* Status phase */
  886. info = (usb_pipeout(pipe) || data_len == 0) ?
  887. TD_CC | TD_DP_IN | TD_T_DATA1:
  888. TD_CC | TD_DP_OUT | TD_T_DATA1;
  889. td_fill(ohci, info, data, 0, dev, cnt++, urb);
  890. if (!ohci->sleeping) {
  891. /* start Control list */
  892. ohci_writel(OHCI_CLF, &ohci->regs->cmdstatus);
  893. }
  894. break;
  895. case PIPE_INTERRUPT:
  896. info = usb_pipeout(urb->pipe)?
  897. TD_CC | TD_DP_OUT | toggle:
  898. TD_CC | TD_R | TD_DP_IN | toggle;
  899. td_fill(ohci, info, data, data_len, dev, cnt++, urb);
  900. break;
  901. }
  902. if (urb->length != cnt)
  903. dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
  904. }
  905. /*-------------------------------------------------------------------------*
  906. * Done List handling functions
  907. *-------------------------------------------------------------------------*/
  908. /* calculate the transfer length and update the urb */
  909. static void dl_transfer_length(td_t *td)
  910. {
  911. __u32 tdBE, tdCBP;
  912. urb_priv_t *lurb_priv = td->ed->purb;
  913. tdBE = m32_swap(td->hwBE);
  914. tdCBP = m32_swap(td->hwCBP);
  915. if (!(usb_pipecontrol(lurb_priv->pipe) &&
  916. ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
  917. if (tdBE != 0) {
  918. if (td->hwCBP == 0)
  919. lurb_priv->actual_length += tdBE - td->data + 1;
  920. else
  921. lurb_priv->actual_length += tdCBP - td->data;
  922. }
  923. }
  924. }
  925. /*-------------------------------------------------------------------------*/
  926. static void check_status(td_t *td_list)
  927. {
  928. urb_priv_t *lurb_priv = td_list->ed->purb;
  929. int urb_len = lurb_priv->length;
  930. __u32 *phwHeadP = &td_list->ed->hwHeadP;
  931. int cc;
  932. cc = TD_CC_GET(m32_swap(td_list->hwINFO));
  933. if (cc) {
  934. err(" USB-error: %s (%x)", cc_to_string[cc], cc);
  935. invalidate_dcache_ed(td_list->ed);
  936. if (*phwHeadP & m32_swap(0x1)) {
  937. if (lurb_priv &&
  938. ((td_list->index + 1) < urb_len)) {
  939. *phwHeadP =
  940. (lurb_priv->td[urb_len - 1]->hwNextTD &\
  941. m32_swap(0xfffffff0)) |
  942. (*phwHeadP & m32_swap(0x2));
  943. lurb_priv->td_cnt += urb_len -
  944. td_list->index - 1;
  945. } else
  946. *phwHeadP &= m32_swap(0xfffffff2);
  947. flush_dcache_ed(td_list->ed);
  948. }
  949. }
  950. }
  951. /* replies to the request have to be on a FIFO basis so
  952. * we reverse the reversed done-list */
  953. static td_t *dl_reverse_done_list(ohci_t *ohci)
  954. {
  955. uintptr_t td_list_hc;
  956. td_t *td_rev = NULL;
  957. td_t *td_list = NULL;
  958. invalidate_dcache_hcca(ohci->hcca);
  959. td_list_hc = m32_swap(ohci->hcca->done_head) & 0xfffffff0;
  960. ohci->hcca->done_head = 0;
  961. flush_dcache_hcca(ohci->hcca);
  962. while (td_list_hc) {
  963. td_list = (td_t *)td_list_hc;
  964. invalidate_dcache_td(td_list);
  965. check_status(td_list);
  966. td_list->next_dl_td = td_rev;
  967. td_rev = td_list;
  968. td_list_hc = m32_swap(td_list->hwNextTD) & 0xfffffff0;
  969. }
  970. return td_list;
  971. }
  972. /*-------------------------------------------------------------------------*/
  973. /*-------------------------------------------------------------------------*/
  974. static void finish_urb(ohci_t *ohci, urb_priv_t *urb, int status)
  975. {
  976. if ((status & (ED_OPER | ED_UNLINK)) && (urb->state != URB_DEL))
  977. urb->finished = 1;
  978. else
  979. dbg("finish_urb: strange.., ED state %x, \n", status);
  980. }
  981. /*
  982. * Used to take back a TD from the host controller. This would normally be
  983. * called from within dl_done_list, however it may be called directly if the
  984. * HC no longer sees the TD and it has not appeared on the donelist (after
  985. * two frames). This bug has been observed on ZF Micro systems.
  986. */
  987. static int takeback_td(ohci_t *ohci, td_t *td_list)
  988. {
  989. ed_t *ed;
  990. int cc;
  991. int stat = 0;
  992. /* urb_t *urb; */
  993. urb_priv_t *lurb_priv;
  994. __u32 tdINFO, edHeadP, edTailP;
  995. invalidate_dcache_td(td_list);
  996. tdINFO = m32_swap(td_list->hwINFO);
  997. ed = td_list->ed;
  998. lurb_priv = ed->purb;
  999. dl_transfer_length(td_list);
  1000. lurb_priv->td_cnt++;
  1001. /* error code of transfer */
  1002. cc = TD_CC_GET(tdINFO);
  1003. if (cc) {
  1004. err("USB-error: %s (%x)", cc_to_string[cc], cc);
  1005. stat = cc_to_error[cc];
  1006. }
  1007. /* see if this done list makes for all TD's of current URB,
  1008. * and mark the URB finished if so */
  1009. if (lurb_priv->td_cnt == lurb_priv->length)
  1010. finish_urb(ohci, lurb_priv, ed->state);
  1011. dbg("dl_done_list: processing TD %x, len %x\n",
  1012. lurb_priv->td_cnt, lurb_priv->length);
  1013. if (ed->state != ED_NEW && (!usb_pipeint(lurb_priv->pipe))) {
  1014. invalidate_dcache_ed(ed);
  1015. edHeadP = m32_swap(ed->hwHeadP) & 0xfffffff0;
  1016. edTailP = m32_swap(ed->hwTailP);
  1017. /* unlink eds if they are not busy */
  1018. if ((edHeadP == edTailP) && (ed->state == ED_OPER))
  1019. ep_unlink(ohci, ed);
  1020. }
  1021. return stat;
  1022. }
  1023. static int dl_done_list(ohci_t *ohci)
  1024. {
  1025. int stat = 0;
  1026. td_t *td_list = dl_reverse_done_list(ohci);
  1027. while (td_list) {
  1028. td_t *td_next = td_list->next_dl_td;
  1029. stat = takeback_td(ohci, td_list);
  1030. td_list = td_next;
  1031. }
  1032. return stat;
  1033. }
  1034. /*-------------------------------------------------------------------------*
  1035. * Virtual Root Hub
  1036. *-------------------------------------------------------------------------*/
  1037. #include <usbroothubdes.h>
  1038. /* Hub class-specific descriptor is constructed dynamically */
  1039. /*-------------------------------------------------------------------------*/
  1040. #define OK(x) len = (x); break
  1041. #ifdef DEBUG
  1042. #define WR_RH_STAT(x) {info("WR:status %#8x", (x)); ohci_writel((x), \
  1043. &ohci->regs->roothub.status); }
  1044. #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, \
  1045. (x)); ohci_writel((x), &ohci->regs->roothub.portstatus[wIndex-1]); }
  1046. #else
  1047. #define WR_RH_STAT(x) ohci_writel((x), &ohci->regs->roothub.status)
  1048. #define WR_RH_PORTSTAT(x) ohci_writel((x), \
  1049. &ohci->regs->roothub.portstatus[wIndex-1])
  1050. #endif
  1051. #define RD_RH_STAT roothub_status(ohci)
  1052. #define RD_RH_PORTSTAT roothub_portstatus(ohci, wIndex-1)
  1053. /* request to virtual root hub */
  1054. int rh_check_port_status(ohci_t *controller)
  1055. {
  1056. __u32 temp, ndp, i;
  1057. int res;
  1058. res = -1;
  1059. temp = roothub_a(controller);
  1060. ndp = (temp & RH_A_NDP);
  1061. #ifdef CONFIG_AT91C_PQFP_UHPBUG
  1062. ndp = (ndp == 2) ? 1:0;
  1063. #endif
  1064. for (i = 0; i < ndp; i++) {
  1065. temp = roothub_portstatus(controller, i);
  1066. /* check for a device disconnect */
  1067. if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
  1068. (RH_PS_PESC | RH_PS_CSC)) &&
  1069. ((temp & RH_PS_CCS) == 0)) {
  1070. res = i;
  1071. break;
  1072. }
  1073. }
  1074. return res;
  1075. }
  1076. static int ohci_submit_rh_msg(ohci_t *ohci, struct usb_device *dev,
  1077. unsigned long pipe, void *buffer, int transfer_len,
  1078. struct devrequest *cmd)
  1079. {
  1080. void *data = buffer;
  1081. int leni = transfer_len;
  1082. int len = 0;
  1083. int stat = 0;
  1084. __u16 bmRType_bReq;
  1085. __u16 wValue;
  1086. __u16 wIndex;
  1087. __u16 wLength;
  1088. ALLOC_ALIGN_BUFFER(__u8, databuf, 16, sizeof(u32));
  1089. #ifdef DEBUG
  1090. pkt_print(ohci, NULL, dev, pipe, buffer, transfer_len,
  1091. cmd, "SUB(rh)", usb_pipein(pipe));
  1092. #else
  1093. ohci_mdelay(1);
  1094. #endif
  1095. if (usb_pipeint(pipe)) {
  1096. info("Root-Hub submit IRQ: NOT implemented");
  1097. return 0;
  1098. }
  1099. bmRType_bReq = cmd->requesttype | (cmd->request << 8);
  1100. wValue = le16_to_cpu(cmd->value);
  1101. wIndex = le16_to_cpu(cmd->index);
  1102. wLength = le16_to_cpu(cmd->length);
  1103. info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
  1104. dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
  1105. switch (bmRType_bReq) {
  1106. /* Request Destination:
  1107. without flags: Device,
  1108. RH_INTERFACE: interface,
  1109. RH_ENDPOINT: endpoint,
  1110. RH_CLASS means HUB here,
  1111. RH_OTHER | RH_CLASS almost ever means HUB_PORT here
  1112. */
  1113. case RH_GET_STATUS:
  1114. *(u16 *)databuf = cpu_to_le16(1);
  1115. OK(2);
  1116. case RH_GET_STATUS | RH_INTERFACE:
  1117. *(u16 *)databuf = cpu_to_le16(0);
  1118. OK(2);
  1119. case RH_GET_STATUS | RH_ENDPOINT:
  1120. *(u16 *)databuf = cpu_to_le16(0);
  1121. OK(2);
  1122. case RH_GET_STATUS | RH_CLASS:
  1123. *(u32 *)databuf = cpu_to_le32(
  1124. RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
  1125. OK(4);
  1126. case RH_GET_STATUS | RH_OTHER | RH_CLASS:
  1127. *(u32 *)databuf = cpu_to_le32(RD_RH_PORTSTAT);
  1128. OK(4);
  1129. case RH_CLEAR_FEATURE | RH_ENDPOINT:
  1130. switch (wValue) {
  1131. case (RH_ENDPOINT_STALL):
  1132. OK(0);
  1133. }
  1134. break;
  1135. case RH_CLEAR_FEATURE | RH_CLASS:
  1136. switch (wValue) {
  1137. case RH_C_HUB_LOCAL_POWER:
  1138. OK(0);
  1139. case (RH_C_HUB_OVER_CURRENT):
  1140. WR_RH_STAT(RH_HS_OCIC);
  1141. OK(0);
  1142. }
  1143. break;
  1144. case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
  1145. switch (wValue) {
  1146. case (RH_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_CCS); OK(0);
  1147. case (RH_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_POCI); OK(0);
  1148. case (RH_PORT_POWER): WR_RH_PORTSTAT(RH_PS_LSDA); OK(0);
  1149. case (RH_C_PORT_CONNECTION): WR_RH_PORTSTAT(RH_PS_CSC); OK(0);
  1150. case (RH_C_PORT_ENABLE): WR_RH_PORTSTAT(RH_PS_PESC); OK(0);
  1151. case (RH_C_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_PSSC); OK(0);
  1152. case (RH_C_PORT_OVER_CURRENT):WR_RH_PORTSTAT(RH_PS_OCIC); OK(0);
  1153. case (RH_C_PORT_RESET): WR_RH_PORTSTAT(RH_PS_PRSC); OK(0);
  1154. }
  1155. break;
  1156. case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
  1157. switch (wValue) {
  1158. case (RH_PORT_SUSPEND):
  1159. WR_RH_PORTSTAT(RH_PS_PSS); OK(0);
  1160. case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
  1161. if (RD_RH_PORTSTAT & RH_PS_CCS)
  1162. WR_RH_PORTSTAT(RH_PS_PRS);
  1163. OK(0);
  1164. case (RH_PORT_POWER):
  1165. WR_RH_PORTSTAT(RH_PS_PPS);
  1166. OK(0);
  1167. case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
  1168. if (RD_RH_PORTSTAT & RH_PS_CCS)
  1169. WR_RH_PORTSTAT(RH_PS_PES);
  1170. OK(0);
  1171. }
  1172. break;
  1173. case RH_SET_ADDRESS:
  1174. ohci->rh.devnum = wValue;
  1175. OK(0);
  1176. case RH_GET_DESCRIPTOR:
  1177. switch ((wValue & 0xff00) >> 8) {
  1178. case (0x01): /* device descriptor */
  1179. len = min_t(unsigned int,
  1180. leni,
  1181. min_t(unsigned int,
  1182. sizeof(root_hub_dev_des),
  1183. wLength));
  1184. databuf = root_hub_dev_des; OK(len);
  1185. case (0x02): /* configuration descriptor */
  1186. len = min_t(unsigned int,
  1187. leni,
  1188. min_t(unsigned int,
  1189. sizeof(root_hub_config_des),
  1190. wLength));
  1191. databuf = root_hub_config_des; OK(len);
  1192. case (0x03): /* string descriptors */
  1193. if (wValue == 0x0300) {
  1194. len = min_t(unsigned int,
  1195. leni,
  1196. min_t(unsigned int,
  1197. sizeof(root_hub_str_index0),
  1198. wLength));
  1199. databuf = root_hub_str_index0;
  1200. OK(len);
  1201. }
  1202. if (wValue == 0x0301) {
  1203. len = min_t(unsigned int,
  1204. leni,
  1205. min_t(unsigned int,
  1206. sizeof(root_hub_str_index1),
  1207. wLength));
  1208. databuf = root_hub_str_index1;
  1209. OK(len);
  1210. }
  1211. default:
  1212. stat = USB_ST_STALLED;
  1213. }
  1214. break;
  1215. case RH_GET_DESCRIPTOR | RH_CLASS:
  1216. {
  1217. __u32 temp = roothub_a(ohci);
  1218. databuf[0] = 9; /* min length; */
  1219. databuf[1] = 0x29;
  1220. databuf[2] = temp & RH_A_NDP;
  1221. #ifdef CONFIG_AT91C_PQFP_UHPBUG
  1222. databuf[2] = (databuf[2] == 2) ? 1 : 0;
  1223. #endif
  1224. databuf[3] = 0;
  1225. if (temp & RH_A_PSM) /* per-port power switching? */
  1226. databuf[3] |= 0x1;
  1227. if (temp & RH_A_NOCP) /* no overcurrent reporting? */
  1228. databuf[3] |= 0x10;
  1229. else if (temp & RH_A_OCPM)/* per-port overcurrent reporting? */
  1230. databuf[3] |= 0x8;
  1231. databuf[4] = 0;
  1232. databuf[5] = (temp & RH_A_POTPGT) >> 24;
  1233. databuf[6] = 0;
  1234. temp = roothub_b(ohci);
  1235. databuf[7] = temp & RH_B_DR;
  1236. if (databuf[2] < 7) {
  1237. databuf[8] = 0xff;
  1238. } else {
  1239. databuf[0] += 2;
  1240. databuf[8] = (temp & RH_B_DR) >> 8;
  1241. databuf[10] = databuf[9] = 0xff;
  1242. }
  1243. len = min_t(unsigned int, leni,
  1244. min_t(unsigned int, databuf[0], wLength));
  1245. OK(len);
  1246. }
  1247. case RH_GET_CONFIGURATION:
  1248. databuf[0] = 0x01;
  1249. OK(1);
  1250. case RH_SET_CONFIGURATION:
  1251. WR_RH_STAT(0x10000);
  1252. OK(0);
  1253. default:
  1254. dbg("unsupported root hub command");
  1255. stat = USB_ST_STALLED;
  1256. }
  1257. #ifdef DEBUG
  1258. ohci_dump_roothub(ohci, 1);
  1259. #else
  1260. ohci_mdelay(1);
  1261. #endif
  1262. len = min_t(int, len, leni);
  1263. if (data != databuf)
  1264. memcpy(data, databuf, len);
  1265. dev->act_len = len;
  1266. dev->status = stat;
  1267. #ifdef DEBUG
  1268. pkt_print(ohci, NULL, dev, pipe, buffer,
  1269. transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
  1270. #else
  1271. ohci_mdelay(1);
  1272. #endif
  1273. return stat;
  1274. }
  1275. /*-------------------------------------------------------------------------*/
  1276. static ohci_dev_t *ohci_get_ohci_dev(ohci_t *ohci, int devnum, int intr)
  1277. {
  1278. int i;
  1279. if (!intr)
  1280. return &ohci->ohci_dev;
  1281. /* First see if we already have an ohci_dev for this dev. */
  1282. for (i = 0; i < NUM_INT_DEVS; i++) {
  1283. if (ohci->int_dev[i].devnum == devnum)
  1284. return &ohci->int_dev[i];
  1285. }
  1286. /* If not then find a free one. */
  1287. for (i = 0; i < NUM_INT_DEVS; i++) {
  1288. if (ohci->int_dev[i].devnum == -1) {
  1289. ohci->int_dev[i].devnum = devnum;
  1290. return &ohci->int_dev[i];
  1291. }
  1292. }
  1293. printf("ohci: Error out of ohci_devs for interrupt endpoints\n");
  1294. return NULL;
  1295. }
  1296. /* common code for handling submit messages - used for all but root hub */
  1297. /* accesses. */
  1298. static urb_priv_t *ohci_alloc_urb(struct usb_device *dev, unsigned long pipe,
  1299. void *buffer, int transfer_len, int interval)
  1300. {
  1301. urb_priv_t *urb;
  1302. urb = calloc(1, sizeof(urb_priv_t));
  1303. if (!urb) {
  1304. printf("ohci: Error out of memory allocating urb\n");
  1305. return NULL;
  1306. }
  1307. urb->dev = dev;
  1308. urb->pipe = pipe;
  1309. urb->transfer_buffer = buffer;
  1310. urb->transfer_buffer_length = transfer_len;
  1311. urb->interval = interval;
  1312. return urb;
  1313. }
  1314. static int submit_common_msg(ohci_t *ohci, struct usb_device *dev,
  1315. unsigned long pipe, void *buffer, int transfer_len,
  1316. struct devrequest *setup, int interval)
  1317. {
  1318. int stat = 0;
  1319. int maxsize = usb_maxpacket(dev, pipe);
  1320. int timeout;
  1321. urb_priv_t *urb;
  1322. ohci_dev_t *ohci_dev;
  1323. urb = ohci_alloc_urb(dev, pipe, buffer, transfer_len, interval);
  1324. if (!urb)
  1325. return -ENOMEM;
  1326. #ifdef DEBUG
  1327. urb->actual_length = 0;
  1328. pkt_print(ohci, urb, dev, pipe, buffer, transfer_len,
  1329. setup, "SUB", usb_pipein(pipe));
  1330. #else
  1331. ohci_mdelay(1);
  1332. #endif
  1333. if (!maxsize) {
  1334. err("submit_common_message: pipesize for pipe %lx is zero",
  1335. pipe);
  1336. return -1;
  1337. }
  1338. ohci_dev = ohci_get_ohci_dev(ohci, dev->devnum, usb_pipeint(pipe));
  1339. if (!ohci_dev)
  1340. return -ENOMEM;
  1341. if (sohci_submit_job(ohci, ohci_dev, urb, setup) < 0) {
  1342. err("sohci_submit_job failed");
  1343. return -1;
  1344. }
  1345. mdelay(10);
  1346. /* ohci_dump_status(ohci); */
  1347. timeout = USB_TIMEOUT_MS(pipe);
  1348. /* wait for it to complete */
  1349. for (;;) {
  1350. /* check whether the controller is done */
  1351. stat = hc_interrupt(ohci);
  1352. if (stat < 0) {
  1353. stat = USB_ST_CRC_ERR;
  1354. break;
  1355. }
  1356. /* NOTE: since we are not interrupt driven in U-Boot and always
  1357. * handle only one URB at a time, we cannot assume the
  1358. * transaction finished on the first successful return from
  1359. * hc_interrupt().. unless the flag for current URB is set,
  1360. * meaning that all TD's to/from device got actually
  1361. * transferred and processed. If the current URB is not
  1362. * finished we need to re-iterate this loop so as
  1363. * hc_interrupt() gets called again as there needs to be some
  1364. * more TD's to process still */
  1365. if ((stat >= 0) && (stat != 0xff) && (urb->finished)) {
  1366. /* 0xff is returned for an SF-interrupt */
  1367. break;
  1368. }
  1369. if (--timeout) {
  1370. mdelay(1);
  1371. if (!urb->finished)
  1372. dbg("*");
  1373. } else {
  1374. if (!usb_pipeint(pipe))
  1375. err("CTL:TIMEOUT ");
  1376. dbg("submit_common_msg: TO status %x\n", stat);
  1377. urb->finished = 1;
  1378. stat = USB_ST_CRC_ERR;
  1379. break;
  1380. }
  1381. }
  1382. dev->status = stat;
  1383. dev->act_len = urb->actual_length;
  1384. if (usb_pipein(pipe) && dev->status == 0 && dev->act_len)
  1385. invalidate_dcache_buffer(buffer, dev->act_len);
  1386. #ifdef DEBUG
  1387. pkt_print(ohci, urb, dev, pipe, buffer, transfer_len,
  1388. setup, "RET(ctlr)", usb_pipein(pipe));
  1389. #else
  1390. ohci_mdelay(1);
  1391. #endif
  1392. urb_free_priv(urb);
  1393. return 0;
  1394. }
  1395. #define MAX_INT_QUEUESIZE 8
  1396. struct int_queue {
  1397. int queuesize;
  1398. int curr_urb;
  1399. urb_priv_t *urb[MAX_INT_QUEUESIZE];
  1400. };
  1401. static struct int_queue *_ohci_create_int_queue(ohci_t *ohci,
  1402. struct usb_device *udev, unsigned long pipe, int queuesize,
  1403. int elementsize, void *buffer, int interval)
  1404. {
  1405. struct int_queue *queue;
  1406. ohci_dev_t *ohci_dev;
  1407. int i;
  1408. if (queuesize > MAX_INT_QUEUESIZE)
  1409. return NULL;
  1410. ohci_dev = ohci_get_ohci_dev(ohci, udev->devnum, 1);
  1411. if (!ohci_dev)
  1412. return NULL;
  1413. queue = malloc(sizeof(*queue));
  1414. if (!queue) {
  1415. printf("ohci: Error out of memory allocating int queue\n");
  1416. return NULL;
  1417. }
  1418. for (i = 0; i < queuesize; i++) {
  1419. queue->urb[i] = ohci_alloc_urb(udev, pipe,
  1420. buffer + i * elementsize,
  1421. elementsize, interval);
  1422. if (!queue->urb[i])
  1423. break;
  1424. if (sohci_submit_job(ohci, ohci_dev, queue->urb[i], NULL)) {
  1425. printf("ohci: Error submitting int queue job\n");
  1426. urb_free_priv(queue->urb[i]);
  1427. break;
  1428. }
  1429. }
  1430. if (i == 0) {
  1431. /* We did not succeed in submitting even 1 urb */
  1432. free(queue);
  1433. return NULL;
  1434. }
  1435. queue->queuesize = i;
  1436. queue->curr_urb = 0;
  1437. return queue;
  1438. }
  1439. static void *_ohci_poll_int_queue(ohci_t *ohci, struct usb_device *udev,
  1440. struct int_queue *queue)
  1441. {
  1442. if (queue->curr_urb == queue->queuesize)
  1443. return NULL; /* Queue depleted */
  1444. if (hc_interrupt(ohci) < 0)
  1445. return NULL;
  1446. if (queue->urb[queue->curr_urb]->finished) {
  1447. void *ret = queue->urb[queue->curr_urb]->transfer_buffer;
  1448. queue->curr_urb++;
  1449. return ret;
  1450. }
  1451. return NULL;
  1452. }
  1453. static int _ohci_destroy_int_queue(ohci_t *ohci, struct usb_device *dev,
  1454. struct int_queue *queue)
  1455. {
  1456. int i;
  1457. for (i = 0; i < queue->queuesize; i++)
  1458. urb_free_priv(queue->urb[i]);
  1459. free(queue);
  1460. return 0;
  1461. }
  1462. #if !CONFIG_IS_ENABLED(DM_USB)
  1463. /* submit routines called from usb.c */
  1464. int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1465. int transfer_len)
  1466. {
  1467. info("submit_bulk_msg");
  1468. return submit_common_msg(&gohci, dev, pipe, buffer, transfer_len,
  1469. NULL, 0);
  1470. }
  1471. int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1472. int transfer_len, int interval, bool nonblock)
  1473. {
  1474. info("submit_int_msg");
  1475. return submit_common_msg(&gohci, dev, pipe, buffer, transfer_len, NULL,
  1476. interval);
  1477. }
  1478. struct int_queue *create_int_queue(struct usb_device *dev,
  1479. unsigned long pipe, int queuesize, int elementsize,
  1480. void *buffer, int interval)
  1481. {
  1482. return _ohci_create_int_queue(&gohci, dev, pipe, queuesize,
  1483. elementsize, buffer, interval);
  1484. }
  1485. void *poll_int_queue(struct usb_device *dev, struct int_queue *queue)
  1486. {
  1487. return _ohci_poll_int_queue(&gohci, dev, queue);
  1488. }
  1489. int destroy_int_queue(struct usb_device *dev, struct int_queue *queue)
  1490. {
  1491. return _ohci_destroy_int_queue(&gohci, dev, queue);
  1492. }
  1493. #endif
  1494. static int _ohci_submit_control_msg(ohci_t *ohci, struct usb_device *dev,
  1495. unsigned long pipe, void *buffer, int transfer_len,
  1496. struct devrequest *setup)
  1497. {
  1498. int maxsize = usb_maxpacket(dev, pipe);
  1499. info("submit_control_msg");
  1500. #ifdef DEBUG
  1501. pkt_print(ohci, NULL, dev, pipe, buffer, transfer_len,
  1502. setup, "SUB", usb_pipein(pipe));
  1503. #else
  1504. ohci_mdelay(1);
  1505. #endif
  1506. if (!maxsize) {
  1507. err("submit_control_message: pipesize for pipe %lx is zero",
  1508. pipe);
  1509. return -1;
  1510. }
  1511. if (((pipe >> 8) & 0x7f) == ohci->rh.devnum) {
  1512. ohci->rh.dev = dev;
  1513. /* root hub - redirect */
  1514. return ohci_submit_rh_msg(ohci, dev, pipe, buffer,
  1515. transfer_len, setup);
  1516. }
  1517. return submit_common_msg(ohci, dev, pipe, buffer, transfer_len,
  1518. setup, 0);
  1519. }
  1520. /*-------------------------------------------------------------------------*
  1521. * HC functions
  1522. *-------------------------------------------------------------------------*/
  1523. /* reset the HC and BUS */
  1524. static int hc_reset(ohci_t *ohci)
  1525. {
  1526. #ifdef CONFIG_PCI_EHCI_DEVNO
  1527. pci_dev_t pdev;
  1528. #endif
  1529. int timeout = 30;
  1530. int smm_timeout = 50; /* 0,5 sec */
  1531. dbg("%s\n", __FUNCTION__);
  1532. #ifdef CONFIG_PCI_EHCI_DEVNO
  1533. /*
  1534. * Some multi-function controllers (e.g. ISP1562) allow root hub
  1535. * resetting via EHCI registers only.
  1536. */
  1537. pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVNO);
  1538. if (pdev != -1) {
  1539. u32 base;
  1540. int timeout = 1000;
  1541. pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base);
  1542. base += EHCI_USBCMD_OFF;
  1543. ohci_writel(ohci_readl(base) | EHCI_USBCMD_HCRESET, base);
  1544. while (ohci_readl(base) & EHCI_USBCMD_HCRESET) {
  1545. if (timeout-- <= 0) {
  1546. printf("USB RootHub reset timed out!");
  1547. break;
  1548. }
  1549. udelay(1);
  1550. }
  1551. } else
  1552. printf("No EHCI func at %d index!\n", CONFIG_PCI_EHCI_DEVNO);
  1553. #endif
  1554. if (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) {
  1555. /* SMM owns the HC, request ownership */
  1556. ohci_writel(OHCI_OCR, &ohci->regs->cmdstatus);
  1557. info("USB HC TakeOver from SMM");
  1558. while (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) {
  1559. mdelay(10);
  1560. if (--smm_timeout == 0) {
  1561. err("USB HC TakeOver failed!");
  1562. return -1;
  1563. }
  1564. }
  1565. }
  1566. /* Disable HC interrupts */
  1567. ohci_writel(OHCI_INTR_MIE, &ohci->regs->intrdisable);
  1568. dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n",
  1569. ohci->slot_name,
  1570. ohci_readl(&ohci->regs->control));
  1571. /* Reset USB (needed by some controllers) */
  1572. ohci->hc_control = 0;
  1573. ohci_writel(ohci->hc_control, &ohci->regs->control);
  1574. /* HC Reset requires max 10 us delay */
  1575. ohci_writel(OHCI_HCR, &ohci->regs->cmdstatus);
  1576. while ((ohci_readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
  1577. if (--timeout == 0) {
  1578. err("USB HC reset timed out!");
  1579. return -1;
  1580. }
  1581. udelay(1);
  1582. }
  1583. return 0;
  1584. }
  1585. /*-------------------------------------------------------------------------*/
  1586. /* Start an OHCI controller, set the BUS operational
  1587. * enable interrupts
  1588. * connect the virtual root hub */
  1589. static int hc_start(ohci_t *ohci)
  1590. {
  1591. __u32 mask;
  1592. unsigned int fminterval;
  1593. int i;
  1594. ohci->disabled = 1;
  1595. for (i = 0; i < NUM_INT_DEVS; i++)
  1596. ohci->int_dev[i].devnum = -1;
  1597. /* Tell the controller where the control and bulk lists are
  1598. * The lists are empty now. */
  1599. ohci_writel(0, &ohci->regs->ed_controlhead);
  1600. ohci_writel(0, &ohci->regs->ed_bulkhead);
  1601. ohci_writel((uintptr_t)ohci->hcca,
  1602. &ohci->regs->hcca); /* reset clears this */
  1603. fminterval = 0x2edf;
  1604. ohci_writel((fminterval * 9) / 10, &ohci->regs->periodicstart);
  1605. fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
  1606. ohci_writel(fminterval, &ohci->regs->fminterval);
  1607. ohci_writel(0x628, &ohci->regs->lsthresh);
  1608. /* start controller operations */
  1609. ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
  1610. ohci->disabled = 0;
  1611. ohci_writel(ohci->hc_control, &ohci->regs->control);
  1612. /* disable all interrupts */
  1613. mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
  1614. OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
  1615. OHCI_INTR_OC | OHCI_INTR_MIE);
  1616. ohci_writel(mask, &ohci->regs->intrdisable);
  1617. /* clear all interrupts */
  1618. mask &= ~OHCI_INTR_MIE;
  1619. ohci_writel(mask, &ohci->regs->intrstatus);
  1620. /* Choose the interrupts we care about now - but w/o MIE */
  1621. mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
  1622. ohci_writel(mask, &ohci->regs->intrenable);
  1623. #ifdef OHCI_USE_NPS
  1624. /* required for AMD-756 and some Mac platforms */
  1625. ohci_writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM,
  1626. &ohci->regs->roothub.a);
  1627. ohci_writel(RH_HS_LPSC, &ohci->regs->roothub.status);
  1628. #endif /* OHCI_USE_NPS */
  1629. /* connect the virtual root hub */
  1630. ohci->rh.devnum = 0;
  1631. return 0;
  1632. }
  1633. /*-------------------------------------------------------------------------*/
  1634. /* an interrupt happens */
  1635. static int hc_interrupt(ohci_t *ohci)
  1636. {
  1637. struct ohci_regs *regs = ohci->regs;
  1638. int ints;
  1639. int stat = -1;
  1640. invalidate_dcache_hcca(ohci->hcca);
  1641. if ((ohci->hcca->done_head != 0) &&
  1642. !(m32_swap(ohci->hcca->done_head) & 0x01)) {
  1643. ints = OHCI_INTR_WDH;
  1644. } else {
  1645. ints = ohci_readl(&regs->intrstatus);
  1646. if (ints == ~(u32)0) {
  1647. ohci->disabled++;
  1648. err("%s device removed!", ohci->slot_name);
  1649. return -1;
  1650. } else {
  1651. ints &= ohci_readl(&regs->intrenable);
  1652. if (ints == 0) {
  1653. dbg("hc_interrupt: returning..\n");
  1654. return 0xff;
  1655. }
  1656. }
  1657. }
  1658. /* dbg("Interrupt: %x frame: %x", ints,
  1659. le16_to_cpu(ohci->hcca->frame_no)); */
  1660. if (ints & OHCI_INTR_RHSC)
  1661. stat = 0xff;
  1662. if (ints & OHCI_INTR_UE) {
  1663. ohci->disabled++;
  1664. err("OHCI Unrecoverable Error, controller usb-%s disabled",
  1665. ohci->slot_name);
  1666. /* e.g. due to PCI Master/Target Abort */
  1667. #ifdef DEBUG
  1668. ohci_dump(ohci, 1);
  1669. #else
  1670. ohci_mdelay(1);
  1671. #endif
  1672. /* FIXME: be optimistic, hope that bug won't repeat often. */
  1673. /* Make some non-interrupt context restart the controller. */
  1674. /* Count and limit the retries though; either hardware or */
  1675. /* software errors can go forever... */
  1676. hc_reset(ohci);
  1677. return -1;
  1678. }
  1679. if (ints & OHCI_INTR_WDH) {
  1680. ohci_mdelay(1);
  1681. ohci_writel(OHCI_INTR_WDH, &regs->intrdisable);
  1682. (void)ohci_readl(&regs->intrdisable); /* flush */
  1683. stat = dl_done_list(ohci);
  1684. ohci_writel(OHCI_INTR_WDH, &regs->intrenable);
  1685. (void)ohci_readl(&regs->intrdisable); /* flush */
  1686. }
  1687. if (ints & OHCI_INTR_SO) {
  1688. dbg("USB Schedule overrun\n");
  1689. ohci_writel(OHCI_INTR_SO, &regs->intrenable);
  1690. stat = -1;
  1691. }
  1692. /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
  1693. if (ints & OHCI_INTR_SF) {
  1694. unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1;
  1695. mdelay(1);
  1696. ohci_writel(OHCI_INTR_SF, &regs->intrdisable);
  1697. if (ohci->ed_rm_list[frame] != NULL)
  1698. ohci_writel(OHCI_INTR_SF, &regs->intrenable);
  1699. stat = 0xff;
  1700. }
  1701. ohci_writel(ints, &regs->intrstatus);
  1702. return stat;
  1703. }
  1704. /*-------------------------------------------------------------------------*/
  1705. #if !CONFIG_IS_ENABLED(DM_USB)
  1706. /*-------------------------------------------------------------------------*/
  1707. /* De-allocate all resources.. */
  1708. static void hc_release_ohci(ohci_t *ohci)
  1709. {
  1710. dbg("USB HC release ohci usb-%s", ohci->slot_name);
  1711. if (!ohci->disabled)
  1712. hc_reset(ohci);
  1713. }
  1714. /*-------------------------------------------------------------------------*/
  1715. /*
  1716. * low level initalisation routine, called from usb.c
  1717. */
  1718. static char ohci_inited = 0;
  1719. int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
  1720. {
  1721. #ifdef CONFIG_PCI_OHCI
  1722. pci_dev_t pdev;
  1723. #endif
  1724. #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
  1725. /* cpu dependant init */
  1726. if (usb_cpu_init())
  1727. return -1;
  1728. #endif
  1729. #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
  1730. /* board dependant init */
  1731. if (board_usb_init(index, USB_INIT_HOST))
  1732. return -1;
  1733. #endif
  1734. memset(&gohci, 0, sizeof(ohci_t));
  1735. /* align the storage */
  1736. if ((__u32)&ghcca[0] & 0xff) {
  1737. err("HCCA not aligned!!");
  1738. return -1;
  1739. }
  1740. gohci.hcca = &ghcca[0];
  1741. info("aligned ghcca %p", gohci.hcca);
  1742. memset(gohci.hcca, 0, sizeof(struct ohci_hcca));
  1743. gohci.disabled = 1;
  1744. gohci.sleeping = 0;
  1745. gohci.irq = -1;
  1746. #ifdef CONFIG_PCI_OHCI
  1747. pdev = pci_find_devices(ohci_pci_ids, CONFIG_PCI_OHCI_DEVNO);
  1748. if (pdev != -1) {
  1749. u16 vid, did;
  1750. u32 base;
  1751. pci_read_config_word(pdev, PCI_VENDOR_ID, &vid);
  1752. pci_read_config_word(pdev, PCI_DEVICE_ID, &did);
  1753. printf("OHCI pci controller (%04x, %04x) found @(%d:%d:%d)\n",
  1754. vid, did, (pdev >> 16) & 0xff,
  1755. (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7);
  1756. pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base);
  1757. printf("OHCI regs address 0x%08x\n", base);
  1758. gohci.regs = (struct ohci_regs *)base;
  1759. } else {
  1760. printf("%s: OHCI devnr: %d not found\n", __func__,
  1761. CONFIG_PCI_OHCI_DEVNO);
  1762. return -1;
  1763. }
  1764. #else
  1765. gohci.regs = (struct ohci_regs *)CONFIG_SYS_USB_OHCI_REGS_BASE;
  1766. #endif
  1767. gohci.flags = 0;
  1768. gohci.slot_name = CONFIG_SYS_USB_OHCI_SLOT_NAME;
  1769. if (hc_reset (&gohci) < 0) {
  1770. hc_release_ohci (&gohci);
  1771. err ("can't reset usb-%s", gohci.slot_name);
  1772. #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
  1773. /* board dependant cleanup */
  1774. board_usb_cleanup(index, USB_INIT_HOST);
  1775. #endif
  1776. #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
  1777. /* cpu dependant cleanup */
  1778. usb_cpu_init_fail();
  1779. #endif
  1780. return -1;
  1781. }
  1782. if (hc_start(&gohci) < 0) {
  1783. err("can't start usb-%s", gohci.slot_name);
  1784. hc_release_ohci(&gohci);
  1785. /* Initialization failed */
  1786. #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
  1787. /* board dependant cleanup */
  1788. usb_board_stop();
  1789. #endif
  1790. #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
  1791. /* cpu dependant cleanup */
  1792. usb_cpu_stop();
  1793. #endif
  1794. return -1;
  1795. }
  1796. #ifdef DEBUG
  1797. ohci_dump(&gohci, 1);
  1798. #else
  1799. ohci_mdelay(1);
  1800. #endif
  1801. ohci_inited = 1;
  1802. return 0;
  1803. }
  1804. int usb_lowlevel_stop(int index)
  1805. {
  1806. /* this gets called really early - before the controller has */
  1807. /* even been initialized! */
  1808. if (!ohci_inited)
  1809. return 0;
  1810. /* TODO release any interrupts, etc. */
  1811. /* call hc_release_ohci() here ? */
  1812. hc_reset(&gohci);
  1813. #ifdef CONFIG_SYS_USB_OHCI_BOARD_INIT
  1814. /* board dependant cleanup */
  1815. if (usb_board_stop())
  1816. return -1;
  1817. #endif
  1818. #ifdef CONFIG_SYS_USB_OHCI_CPU_INIT
  1819. /* cpu dependant cleanup */
  1820. if (usb_cpu_stop())
  1821. return -1;
  1822. #endif
  1823. /* This driver is no longer initialised. It needs a new low-level
  1824. * init (board/cpu) before it can be used again. */
  1825. ohci_inited = 0;
  1826. return 0;
  1827. }
  1828. int submit_control_msg(struct usb_device *dev, unsigned long pipe,
  1829. void *buffer, int transfer_len, struct devrequest *setup)
  1830. {
  1831. return _ohci_submit_control_msg(&gohci, dev, pipe, buffer,
  1832. transfer_len, setup);
  1833. }
  1834. #endif
  1835. #if CONFIG_IS_ENABLED(DM_USB)
  1836. static int ohci_submit_control_msg(struct udevice *dev, struct usb_device *udev,
  1837. unsigned long pipe, void *buffer, int length,
  1838. struct devrequest *setup)
  1839. {
  1840. ohci_t *ohci = dev_get_priv(usb_get_bus(dev));
  1841. return _ohci_submit_control_msg(ohci, udev, pipe, buffer,
  1842. length, setup);
  1843. }
  1844. static int ohci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
  1845. unsigned long pipe, void *buffer, int length)
  1846. {
  1847. ohci_t *ohci = dev_get_priv(usb_get_bus(dev));
  1848. return submit_common_msg(ohci, udev, pipe, buffer, length, NULL, 0);
  1849. }
  1850. static int ohci_submit_int_msg(struct udevice *dev, struct usb_device *udev,
  1851. unsigned long pipe, void *buffer, int length,
  1852. int interval, bool nonblock)
  1853. {
  1854. ohci_t *ohci = dev_get_priv(usb_get_bus(dev));
  1855. return submit_common_msg(ohci, udev, pipe, buffer, length,
  1856. NULL, interval);
  1857. }
  1858. static struct int_queue *ohci_create_int_queue(struct udevice *dev,
  1859. struct usb_device *udev, unsigned long pipe, int queuesize,
  1860. int elementsize, void *buffer, int interval)
  1861. {
  1862. ohci_t *ohci = dev_get_priv(usb_get_bus(dev));
  1863. return _ohci_create_int_queue(ohci, udev, pipe, queuesize, elementsize,
  1864. buffer, interval);
  1865. }
  1866. static void *ohci_poll_int_queue(struct udevice *dev, struct usb_device *udev,
  1867. struct int_queue *queue)
  1868. {
  1869. ohci_t *ohci = dev_get_priv(usb_get_bus(dev));
  1870. return _ohci_poll_int_queue(ohci, udev, queue);
  1871. }
  1872. static int ohci_destroy_int_queue(struct udevice *dev, struct usb_device *udev,
  1873. struct int_queue *queue)
  1874. {
  1875. ohci_t *ohci = dev_get_priv(usb_get_bus(dev));
  1876. return _ohci_destroy_int_queue(ohci, udev, queue);
  1877. }
  1878. int ohci_register(struct udevice *dev, struct ohci_regs *regs)
  1879. {
  1880. struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
  1881. ohci_t *ohci = dev_get_priv(dev);
  1882. u32 reg;
  1883. priv->desc_before_addr = true;
  1884. ohci->regs = regs;
  1885. ohci->hcca = memalign(256, sizeof(struct ohci_hcca));
  1886. if (!ohci->hcca)
  1887. return -ENOMEM;
  1888. memset(ohci->hcca, 0, sizeof(struct ohci_hcca));
  1889. flush_dcache_hcca(ohci->hcca);
  1890. if (hc_reset(ohci) < 0)
  1891. return -EIO;
  1892. if (hc_start(ohci) < 0)
  1893. return -EIO;
  1894. reg = ohci_readl(&regs->revision);
  1895. printf("USB OHCI %x.%x\n", (reg >> 4) & 0xf, reg & 0xf);
  1896. return 0;
  1897. }
  1898. int ohci_deregister(struct udevice *dev)
  1899. {
  1900. ohci_t *ohci = dev_get_priv(dev);
  1901. if (hc_reset(ohci) < 0)
  1902. return -EIO;
  1903. free(ohci->hcca);
  1904. return 0;
  1905. }
  1906. struct dm_usb_ops ohci_usb_ops = {
  1907. .control = ohci_submit_control_msg,
  1908. .bulk = ohci_submit_bulk_msg,
  1909. .interrupt = ohci_submit_int_msg,
  1910. .create_int_queue = ohci_create_int_queue,
  1911. .poll_int_queue = ohci_poll_int_queue,
  1912. .destroy_int_queue = ohci_destroy_int_queue,
  1913. };
  1914. #endif