ehci-vf.c 8.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2015 Sanchayan Maity <sanchayan.maity@toradex.com>
  4. * Copyright (C) 2015 Toradex AG
  5. *
  6. * Based on ehci-mx6 driver
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <usb.h>
  11. #include <errno.h>
  12. #include <linux/compiler.h>
  13. #include <asm/io.h>
  14. #include <asm-generic/gpio.h>
  15. #include <asm/arch/clock.h>
  16. #include <asm/arch/imx-regs.h>
  17. #include <asm/arch/crm_regs.h>
  18. #include <asm/mach-imx/iomux-v3.h>
  19. #include <asm/mach-imx/regs-usbphy.h>
  20. #include <usb/ehci-ci.h>
  21. #include <linux/libfdt.h>
  22. #include <fdtdec.h>
  23. #include "ehci.h"
  24. #define USB_NC_REG_OFFSET 0x00000800
  25. #define ANADIG_PLL_CTRL_EN_USB_CLKS (1 << 6)
  26. #define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
  27. #define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
  28. /* USBCMD */
  29. #define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
  30. #define UCMD_RESET (1 << 1) /* controller reset */
  31. DECLARE_GLOBAL_DATA_PTR;
  32. static const unsigned phy_bases[] = {
  33. USB_PHY0_BASE_ADDR,
  34. USB_PHY1_BASE_ADDR,
  35. };
  36. static const unsigned nc_reg_bases[] = {
  37. USBC0_BASE_ADDR,
  38. USBC1_BASE_ADDR,
  39. };
  40. static void usb_internal_phy_clock_gate(int index)
  41. {
  42. void __iomem *phy_reg;
  43. phy_reg = (void __iomem *)phy_bases[index];
  44. clrbits_le32(phy_reg + USBPHY_CTRL, USBPHY_CTRL_CLKGATE);
  45. }
  46. static void usb_power_config(int index)
  47. {
  48. struct anadig_reg __iomem *anadig =
  49. (struct anadig_reg __iomem *)ANADIG_BASE_ADDR;
  50. void __iomem *pll_ctrl;
  51. switch (index) {
  52. case 0:
  53. pll_ctrl = &anadig->pll3_ctrl;
  54. clrbits_le32(pll_ctrl, ANADIG_PLL3_CTRL_BYPASS);
  55. setbits_le32(pll_ctrl, ANADIG_PLL3_CTRL_ENABLE
  56. | ANADIG_PLL3_CTRL_POWERDOWN
  57. | ANADIG_PLL_CTRL_EN_USB_CLKS);
  58. break;
  59. case 1:
  60. pll_ctrl = &anadig->pll7_ctrl;
  61. clrbits_le32(pll_ctrl, ANADIG_PLL7_CTRL_BYPASS);
  62. setbits_le32(pll_ctrl, ANADIG_PLL7_CTRL_ENABLE
  63. | ANADIG_PLL7_CTRL_POWERDOWN
  64. | ANADIG_PLL_CTRL_EN_USB_CLKS);
  65. break;
  66. default:
  67. return;
  68. }
  69. }
  70. static void usb_phy_enable(int index, struct usb_ehci *ehci)
  71. {
  72. void __iomem *phy_reg;
  73. void __iomem *phy_ctrl;
  74. void __iomem *usb_cmd;
  75. phy_reg = (void __iomem *)phy_bases[index];
  76. phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
  77. usb_cmd = (void __iomem *)&ehci->usbcmd;
  78. /* Stop then Reset */
  79. clrbits_le32(usb_cmd, UCMD_RUN_STOP);
  80. while (readl(usb_cmd) & UCMD_RUN_STOP)
  81. ;
  82. setbits_le32(usb_cmd, UCMD_RESET);
  83. while (readl(usb_cmd) & UCMD_RESET)
  84. ;
  85. /* Reset USBPHY module */
  86. setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST);
  87. udelay(10);
  88. /* Remove CLKGATE and SFTRST */
  89. clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
  90. udelay(10);
  91. /* Power up the PHY */
  92. writel(0, phy_reg + USBPHY_PWD);
  93. /* Enable FS/LS device */
  94. setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 |
  95. USBPHY_CTRL_ENUTMILEVEL3);
  96. }
  97. static void usb_oc_config(int index)
  98. {
  99. void __iomem *ctrl;
  100. ctrl = (void __iomem *)(nc_reg_bases[index] + USB_NC_REG_OFFSET);
  101. setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
  102. setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
  103. }
  104. int __weak board_usb_phy_mode(int port)
  105. {
  106. return 0;
  107. }
  108. int __weak board_ehci_hcd_init(int port)
  109. {
  110. return 0;
  111. }
  112. int ehci_vf_common_init(struct usb_ehci *ehci, int index)
  113. {
  114. int ret;
  115. /* Do board specific initialisation */
  116. ret = board_ehci_hcd_init(index);
  117. if (ret)
  118. return ret;
  119. usb_power_config(index);
  120. usb_oc_config(index);
  121. usb_internal_phy_clock_gate(index);
  122. usb_phy_enable(index, ehci);
  123. return 0;
  124. }
  125. #if !CONFIG_IS_ENABLED(DM_USB)
  126. int ehci_hcd_init(int index, enum usb_init_type init,
  127. struct ehci_hccr **hccr, struct ehci_hcor **hcor)
  128. {
  129. struct usb_ehci *ehci;
  130. enum usb_init_type type;
  131. int ret;
  132. if (index >= ARRAY_SIZE(nc_reg_bases))
  133. return -EINVAL;
  134. ehci = (struct usb_ehci *)nc_reg_bases[index];
  135. ret = ehci_vf_common_init(index);
  136. if (ret)
  137. return ret;
  138. *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
  139. *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
  140. HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
  141. type = board_usb_phy_mode(index);
  142. if (type != init)
  143. return -ENODEV;
  144. if (init == USB_INIT_DEVICE) {
  145. setbits_le32(&ehci->usbmode, CM_DEVICE);
  146. writel((PORT_PTS_UTMI | PORT_PTS_PTW), &ehci->portsc);
  147. setbits_le32(&ehci->portsc, USB_EN);
  148. } else if (init == USB_INIT_HOST) {
  149. setbits_le32(&ehci->usbmode, CM_HOST);
  150. writel((PORT_PTS_UTMI | PORT_PTS_PTW), &ehci->portsc);
  151. setbits_le32(&ehci->portsc, USB_EN);
  152. }
  153. return 0;
  154. }
  155. int ehci_hcd_stop(int index)
  156. {
  157. return 0;
  158. }
  159. #else
  160. /* Possible port types (dual role mode) */
  161. enum dr_mode {
  162. DR_MODE_NONE = 0,
  163. DR_MODE_HOST, /* supports host operation */
  164. DR_MODE_DEVICE, /* supports device operation */
  165. DR_MODE_OTG, /* supports both */
  166. };
  167. struct ehci_vf_priv_data {
  168. struct ehci_ctrl ctrl;
  169. struct usb_ehci *ehci;
  170. struct gpio_desc cdet_gpio;
  171. enum usb_init_type init_type;
  172. enum dr_mode dr_mode;
  173. u32 portnr;
  174. };
  175. static int vf_usb_ofdata_to_platdata(struct udevice *dev)
  176. {
  177. struct ehci_vf_priv_data *priv = dev_get_priv(dev);
  178. const void *dt_blob = gd->fdt_blob;
  179. int node = dev_of_offset(dev);
  180. const char *mode;
  181. priv->portnr = dev->seq;
  182. priv->ehci = (struct usb_ehci *)devfdt_get_addr(dev);
  183. mode = fdt_getprop(dt_blob, node, "dr_mode", NULL);
  184. if (mode) {
  185. if (0 == strcmp(mode, "host")) {
  186. priv->dr_mode = DR_MODE_HOST;
  187. priv->init_type = USB_INIT_HOST;
  188. } else if (0 == strcmp(mode, "peripheral")) {
  189. priv->dr_mode = DR_MODE_DEVICE;
  190. priv->init_type = USB_INIT_DEVICE;
  191. } else if (0 == strcmp(mode, "otg")) {
  192. priv->dr_mode = DR_MODE_OTG;
  193. /*
  194. * We set init_type to device by default when OTG
  195. * mode is requested. If a valid gpio is provided
  196. * we will switch the init_type based on the state
  197. * of the gpio pin.
  198. */
  199. priv->init_type = USB_INIT_DEVICE;
  200. } else {
  201. debug("%s: Cannot decode dr_mode '%s'\n",
  202. __func__, mode);
  203. return -EINVAL;
  204. }
  205. } else {
  206. priv->dr_mode = DR_MODE_HOST;
  207. priv->init_type = USB_INIT_HOST;
  208. }
  209. if (priv->dr_mode == DR_MODE_OTG) {
  210. gpio_request_by_name_nodev(offset_to_ofnode(node),
  211. "fsl,cdet-gpio", 0, &priv->cdet_gpio,
  212. GPIOD_IS_IN);
  213. if (dm_gpio_is_valid(&priv->cdet_gpio)) {
  214. if (dm_gpio_get_value(&priv->cdet_gpio))
  215. priv->init_type = USB_INIT_DEVICE;
  216. else
  217. priv->init_type = USB_INIT_HOST;
  218. }
  219. }
  220. return 0;
  221. }
  222. static int vf_init_after_reset(struct ehci_ctrl *dev)
  223. {
  224. struct ehci_vf_priv_data *priv = dev->priv;
  225. enum usb_init_type type = priv->init_type;
  226. struct usb_ehci *ehci = priv->ehci;
  227. int ret;
  228. ret = ehci_vf_common_init(priv->ehci, priv->portnr);
  229. if (ret)
  230. return ret;
  231. if (type == USB_INIT_DEVICE)
  232. return 0;
  233. setbits_le32(&ehci->usbmode, CM_HOST);
  234. writel((PORT_PTS_UTMI | PORT_PTS_PTW), &ehci->portsc);
  235. setbits_le32(&ehci->portsc, USB_EN);
  236. mdelay(10);
  237. return 0;
  238. }
  239. static const struct ehci_ops vf_ehci_ops = {
  240. .init_after_reset = vf_init_after_reset
  241. };
  242. static int vf_usb_bind(struct udevice *dev)
  243. {
  244. static int num_controllers;
  245. /*
  246. * Without this hack, if we return ENODEV for USB Controller 0, on
  247. * probe for the next controller, USB Controller 1 will be given a
  248. * sequence number of 0. This conflicts with our requirement of
  249. * sequence numbers while initialising the peripherals.
  250. */
  251. dev->req_seq = num_controllers;
  252. num_controllers++;
  253. return 0;
  254. }
  255. static int ehci_usb_probe(struct udevice *dev)
  256. {
  257. struct usb_platdata *plat = dev_get_platdata(dev);
  258. struct ehci_vf_priv_data *priv = dev_get_priv(dev);
  259. struct usb_ehci *ehci = priv->ehci;
  260. struct ehci_hccr *hccr;
  261. struct ehci_hcor *hcor;
  262. int ret;
  263. ret = ehci_vf_common_init(ehci, priv->portnr);
  264. if (ret)
  265. return ret;
  266. if (priv->init_type != plat->init_type)
  267. return -ENODEV;
  268. if (priv->init_type == USB_INIT_HOST) {
  269. setbits_le32(&ehci->usbmode, CM_HOST);
  270. writel((PORT_PTS_UTMI | PORT_PTS_PTW), &ehci->portsc);
  271. setbits_le32(&ehci->portsc, USB_EN);
  272. }
  273. mdelay(10);
  274. hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
  275. hcor = (struct ehci_hcor *)((uint32_t)hccr +
  276. HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
  277. return ehci_register(dev, hccr, hcor, &vf_ehci_ops, 0, priv->init_type);
  278. }
  279. static const struct udevice_id vf_usb_ids[] = {
  280. { .compatible = "fsl,vf610-usb" },
  281. { }
  282. };
  283. U_BOOT_DRIVER(usb_ehci) = {
  284. .name = "ehci_vf",
  285. .id = UCLASS_USB,
  286. .of_match = vf_usb_ids,
  287. .bind = vf_usb_bind,
  288. .probe = ehci_usb_probe,
  289. .remove = ehci_deregister,
  290. .ops = &ehci_usb_ops,
  291. .ofdata_to_platdata = vf_usb_ofdata_to_platdata,
  292. .platdata_auto_alloc_size = sizeof(struct usb_platdata),
  293. .priv_auto_alloc_size = sizeof(struct ehci_vf_priv_data),
  294. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  295. };
  296. #endif