ehci-tegra.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2011 The Chromium OS Authors.
  4. * Copyright (c) 2009-2015 NVIDIA Corporation
  5. * Copyright (c) 2013 Lucas Stach
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <linux/errno.h>
  10. #include <asm/io.h>
  11. #include <asm-generic/gpio.h>
  12. #include <asm/arch/clock.h>
  13. #include <asm/arch-tegra/usb.h>
  14. #include <asm/arch-tegra/clk_rst.h>
  15. #include <usb.h>
  16. #include <usb/ulpi.h>
  17. #include <linux/libfdt.h>
  18. #include "ehci.h"
  19. #define USB1_ADDR_MASK 0xFFFF0000
  20. #define HOSTPC1_DEVLC 0x84
  21. #define HOSTPC1_PSPD(x) (((x) >> 25) & 0x3)
  22. #ifdef CONFIG_USB_ULPI
  23. #ifndef CONFIG_USB_ULPI_VIEWPORT
  24. #error "To use CONFIG_USB_ULPI on Tegra Boards you have to also \
  25. define CONFIG_USB_ULPI_VIEWPORT"
  26. #endif
  27. #endif
  28. /* Parameters we need for USB */
  29. enum {
  30. PARAM_DIVN, /* PLL FEEDBACK DIVIDer */
  31. PARAM_DIVM, /* PLL INPUT DIVIDER */
  32. PARAM_DIVP, /* POST DIVIDER (2^N) */
  33. PARAM_CPCON, /* BASE PLLC CHARGE Pump setup ctrl */
  34. PARAM_LFCON, /* BASE PLLC LOOP FILter setup ctrl */
  35. PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */
  36. PARAM_STABLE_COUNT, /* PLL-U STABLE count */
  37. PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */
  38. PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */
  39. PARAM_DEBOUNCE_A_TIME, /* 10MS DELAY for BIAS_DEBOUNCE_A */
  40. PARAM_BIAS_TIME, /* 20US DELAY AFter bias cell op */
  41. PARAM_COUNT
  42. };
  43. /* Possible port types (dual role mode) */
  44. enum dr_mode {
  45. DR_MODE_NONE = 0,
  46. DR_MODE_HOST, /* supports host operation */
  47. DR_MODE_DEVICE, /* supports device operation */
  48. DR_MODE_OTG, /* supports both */
  49. };
  50. enum usb_ctlr_type {
  51. USB_CTLR_T20,
  52. USB_CTLR_T30,
  53. USB_CTLR_T114,
  54. USB_CTLR_T210,
  55. USB_CTRL_COUNT,
  56. };
  57. /* Information about a USB port */
  58. struct fdt_usb {
  59. struct ehci_ctrl ehci;
  60. struct usb_ctlr *reg; /* address of registers in physical memory */
  61. unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */
  62. unsigned ulpi:1; /* 1 if port has external ULPI transceiver */
  63. unsigned enabled:1; /* 1 to enable, 0 to disable */
  64. unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */
  65. enum usb_ctlr_type type;
  66. enum usb_init_type init_type;
  67. enum dr_mode dr_mode; /* dual role mode */
  68. enum periph_id periph_id;/* peripheral id */
  69. struct gpio_desc vbus_gpio; /* GPIO for vbus enable */
  70. struct gpio_desc phy_reset_gpio; /* GPIO to reset ULPI phy */
  71. };
  72. /*
  73. * This table has USB timing parameters for each Oscillator frequency we
  74. * support. There are four sets of values:
  75. *
  76. * 1. PLLU configuration information (reference clock is osc/clk_m and
  77. * PLLU-FOs are fixed at 12MHz/60MHz/480MHz).
  78. *
  79. * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz
  80. * ----------------------------------------------------------------------
  81. * DIVN 960 (0x3c0) 200 (0c8) 960 (3c0h) 960 (3c0)
  82. * DIVM 13 (0d) 4 (04) 12 (0c) 26 (1a)
  83. * Filter frequency (MHz) 1 4.8 6 2
  84. * CPCON 1100b 0011b 1100b 1100b
  85. * LFCON0 0 0 0 0
  86. *
  87. * 2. PLL CONFIGURATION & PARAMETERS for different clock generators:
  88. *
  89. * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz
  90. * ---------------------------------------------------------------------------
  91. * PLLU_ENABLE_DLY_COUNT 02 (0x02) 03 (03) 02 (02) 04 (04)
  92. * PLLU_STABLE_COUNT 51 (33) 75 (4B) 47 (2F) 102 (66)
  93. * PLL_ACTIVE_DLY_COUNT 05 (05) 06 (06) 04 (04) 09 (09)
  94. * XTAL_FREQ_COUNT 127 (7F) 187 (BB) 118 (76) 254 (FE)
  95. *
  96. * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and
  97. * SessEnd. Each of these signals have their own debouncer and for each of
  98. * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or
  99. * BIAS_DEBOUNCE_B).
  100. *
  101. * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows:
  102. * 0xffff -> No debouncing at all
  103. * <n> ms = <n> *1000 / (1/19.2MHz) / 4
  104. *
  105. * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have:
  106. * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0
  107. *
  108. * We need to use only DebounceA for BOOTROM. We don't need the DebounceB
  109. * values, so we can keep those to default.
  110. *
  111. * 4. The 20 microsecond delay after bias cell operation.
  112. */
  113. static const unsigned T20_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
  114. /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */
  115. { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 },
  116. { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 },
  117. { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 },
  118. { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 },
  119. { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 },
  120. { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }
  121. };
  122. static const unsigned T30_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
  123. /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */
  124. { 0x3C0, 0x0D, 0x00, 0xC, 1, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 5 },
  125. { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 7 },
  126. { 0x3C0, 0x0C, 0x00, 0xC, 1, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 },
  127. { 0x3C0, 0x1A, 0x00, 0xC, 1, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 },
  128. { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 },
  129. { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }
  130. };
  131. static const unsigned T114_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
  132. /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */
  133. { 0x3C0, 0x0D, 0x00, 0xC, 2, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 6 },
  134. { 0x0C8, 0x04, 0x00, 0x3, 2, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 8 },
  135. { 0x3C0, 0x0C, 0x00, 0xC, 2, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 },
  136. { 0x3C0, 0x1A, 0x00, 0xC, 2, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 11 },
  137. { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 },
  138. { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }
  139. };
  140. /* NOTE: 13/26MHz settings are N/A for T210, so dupe 12MHz settings for now */
  141. static const unsigned T210_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
  142. /* DivN, DivM, DivP, KCP, KVCO, Delays Debounce, Bias */
  143. { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 32500, 5 },
  144. { 0x019, 0x01, 0x01, 0x0, 0, 0x03, 0x4B, 0x0C, 0xBB, 48000, 8 },
  145. { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 30000, 5 },
  146. { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 65000, 5 },
  147. { 0x019, 0x02, 0x01, 0x0, 0, 0x05, 0x96, 0x18, 0x177, 96000, 15 },
  148. { 0x028, 0x04, 0x01, 0x0, 0, 0x04, 0x66, 0x09, 0xFE, 120000, 20 }
  149. };
  150. /* UTMIP Idle Wait Delay */
  151. static const u8 utmip_idle_wait_delay = 17;
  152. /* UTMIP Elastic limit */
  153. static const u8 utmip_elastic_limit = 16;
  154. /* UTMIP High Speed Sync Start Delay */
  155. static const u8 utmip_hs_sync_start_delay = 9;
  156. struct fdt_usb_controller {
  157. /* flag to determine whether controller supports hostpc register */
  158. u32 has_hostpc:1;
  159. const unsigned *pll_parameter;
  160. };
  161. static struct fdt_usb_controller fdt_usb_controllers[USB_CTRL_COUNT] = {
  162. {
  163. .has_hostpc = 0,
  164. .pll_parameter = (const unsigned *)T20_usb_pll,
  165. },
  166. {
  167. .has_hostpc = 1,
  168. .pll_parameter = (const unsigned *)T30_usb_pll,
  169. },
  170. {
  171. .has_hostpc = 1,
  172. .pll_parameter = (const unsigned *)T114_usb_pll,
  173. },
  174. {
  175. .has_hostpc = 1,
  176. .pll_parameter = (const unsigned *)T210_usb_pll,
  177. },
  178. };
  179. /*
  180. * A known hardware issue where Connect Status Change bit of PORTSC register
  181. * of USB1 controller will be set after Port Reset.
  182. * We have to clear it in order for later device enumeration to proceed.
  183. */
  184. static void tegra_ehci_powerup_fixup(struct ehci_ctrl *ctrl,
  185. uint32_t *status_reg, uint32_t *reg)
  186. {
  187. struct fdt_usb *config = ctrl->priv;
  188. struct fdt_usb_controller *controller;
  189. controller = &fdt_usb_controllers[config->type];
  190. mdelay(50);
  191. /* This is to avoid PORT_ENABLE bit to be cleared in "ehci-hcd.c". */
  192. if (controller->has_hostpc)
  193. *reg |= EHCI_PS_PE;
  194. if (!config->has_legacy_mode)
  195. return;
  196. /* For EHCI_PS_CSC to be cleared in ehci_hcd.c */
  197. if (ehci_readl(status_reg) & EHCI_PS_CSC)
  198. *reg |= EHCI_PS_CSC;
  199. }
  200. static void tegra_ehci_set_usbmode(struct ehci_ctrl *ctrl)
  201. {
  202. struct fdt_usb *config = ctrl->priv;
  203. struct usb_ctlr *usbctlr;
  204. uint32_t tmp;
  205. usbctlr = config->reg;
  206. tmp = ehci_readl(&usbctlr->usb_mode);
  207. tmp |= USBMODE_CM_HC;
  208. ehci_writel(&usbctlr->usb_mode, tmp);
  209. }
  210. static int tegra_ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg)
  211. {
  212. struct fdt_usb *config = ctrl->priv;
  213. struct fdt_usb_controller *controller;
  214. uint32_t tmp;
  215. uint32_t *reg_ptr;
  216. controller = &fdt_usb_controllers[config->type];
  217. if (controller->has_hostpc) {
  218. reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd +
  219. HOSTPC1_DEVLC);
  220. tmp = ehci_readl(reg_ptr);
  221. return HOSTPC1_PSPD(tmp);
  222. } else
  223. return PORTSC_PSPD(reg);
  224. }
  225. /* Set up VBUS for host/device mode */
  226. static void set_up_vbus(struct fdt_usb *config, enum usb_init_type init)
  227. {
  228. /*
  229. * If we are an OTG port initializing in host mode,
  230. * check if remote host is driving VBus and bail out in this case.
  231. */
  232. if (init == USB_INIT_HOST &&
  233. config->dr_mode == DR_MODE_OTG &&
  234. (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)) {
  235. printf("tegrausb: VBUS input active; not enabling as host\n");
  236. return;
  237. }
  238. if (dm_gpio_is_valid(&config->vbus_gpio)) {
  239. int vbus_value;
  240. vbus_value = (init == USB_INIT_HOST);
  241. dm_gpio_set_value(&config->vbus_gpio, vbus_value);
  242. debug("set_up_vbus: GPIO %d %d\n",
  243. gpio_get_number(&config->vbus_gpio), vbus_value);
  244. }
  245. }
  246. static void usbf_reset_controller(struct fdt_usb *config,
  247. struct usb_ctlr *usbctlr)
  248. {
  249. /* Reset the USB controller with 2us delay */
  250. reset_periph(config->periph_id, 2);
  251. /*
  252. * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under
  253. * base address
  254. */
  255. if (config->has_legacy_mode)
  256. setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE);
  257. /* Put UTMIP1/3 in reset */
  258. setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
  259. /* Enable the UTMIP PHY */
  260. if (config->utmi)
  261. setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB);
  262. }
  263. static const unsigned *get_pll_timing(struct fdt_usb_controller *controller)
  264. {
  265. const unsigned *timing;
  266. timing = controller->pll_parameter +
  267. clock_get_osc_freq() * PARAM_COUNT;
  268. return timing;
  269. }
  270. /* select the PHY to use with a USB controller */
  271. static void init_phy_mux(struct fdt_usb *config, uint pts,
  272. enum usb_init_type init)
  273. {
  274. struct usb_ctlr *usbctlr = config->reg;
  275. #if defined(CONFIG_TEGRA20)
  276. if (config->periph_id == PERIPH_ID_USBD) {
  277. clrsetbits_le32(&usbctlr->port_sc1, PTS1_MASK,
  278. pts << PTS1_SHIFT);
  279. clrbits_le32(&usbctlr->port_sc1, STS1);
  280. } else {
  281. clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
  282. pts << PTS_SHIFT);
  283. clrbits_le32(&usbctlr->port_sc1, STS);
  284. }
  285. #else
  286. /* Set to Host mode (if applicable) after Controller Reset was done */
  287. clrsetbits_le32(&usbctlr->usb_mode, USBMODE_CM_HC,
  288. (init == USB_INIT_HOST) ? USBMODE_CM_HC : 0);
  289. /*
  290. * Select PHY interface after setting host mode.
  291. * For device mode, the ordering requirement is not an issue, since
  292. * only the first USB controller supports device mode, and that USB
  293. * controller can only talk to a UTMI PHY, so the PHY selection is
  294. * already made at reset time, so this write is a no-op.
  295. */
  296. clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK,
  297. pts << PTS_SHIFT);
  298. clrbits_le32(&usbctlr->hostpc1_devlc, STS);
  299. #endif
  300. }
  301. /* set up the UTMI USB controller with the parameters provided */
  302. static int init_utmi_usb_controller(struct fdt_usb *config,
  303. enum usb_init_type init)
  304. {
  305. struct fdt_usb_controller *controller;
  306. u32 b_sess_valid_mask, val;
  307. int loop_count;
  308. const unsigned *timing;
  309. struct usb_ctlr *usbctlr = config->reg;
  310. struct clk_rst_ctlr *clkrst;
  311. struct usb_ctlr *usb1ctlr;
  312. clock_enable(config->periph_id);
  313. /* Reset the usb controller */
  314. usbf_reset_controller(config, usbctlr);
  315. /* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */
  316. clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
  317. /* Follow the crystal clock disable by >100ns delay */
  318. udelay(1);
  319. b_sess_valid_mask = (VBUS_B_SESS_VLD_SW_VALUE | VBUS_B_SESS_VLD_SW_EN);
  320. clrsetbits_le32(&usbctlr->phy_vbus_sensors, b_sess_valid_mask,
  321. (init == USB_INIT_DEVICE) ? b_sess_valid_mask : 0);
  322. /*
  323. * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP
  324. * mux must be switched to actually use a_sess_vld threshold.
  325. */
  326. if (config->dr_mode == DR_MODE_OTG &&
  327. dm_gpio_is_valid(&config->vbus_gpio))
  328. clrsetbits_le32(&usbctlr->usb1_legacy_ctrl,
  329. VBUS_SENSE_CTL_MASK,
  330. VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT);
  331. controller = &fdt_usb_controllers[config->type];
  332. debug("controller=%p, type=%d\n", controller, config->type);
  333. /*
  334. * PLL Delay CONFIGURATION settings. The following parameters control
  335. * the bring up of the plls.
  336. */
  337. timing = get_pll_timing(controller);
  338. if (!controller->has_hostpc) {
  339. val = readl(&usbctlr->utmip_misc_cfg1);
  340. clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
  341. timing[PARAM_STABLE_COUNT] <<
  342. UTMIP_PLLU_STABLE_COUNT_SHIFT);
  343. clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
  344. timing[PARAM_ACTIVE_DELAY_COUNT] <<
  345. UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
  346. writel(val, &usbctlr->utmip_misc_cfg1);
  347. /* Set PLL enable delay count and crystal frequency count */
  348. val = readl(&usbctlr->utmip_pll_cfg1);
  349. clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
  350. timing[PARAM_ENABLE_DELAY_COUNT] <<
  351. UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
  352. clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
  353. timing[PARAM_XTAL_FREQ_COUNT] <<
  354. UTMIP_XTAL_FREQ_COUNT_SHIFT);
  355. writel(val, &usbctlr->utmip_pll_cfg1);
  356. } else {
  357. clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  358. val = readl(&clkrst->crc_utmip_pll_cfg2);
  359. clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
  360. timing[PARAM_STABLE_COUNT] <<
  361. UTMIP_PLLU_STABLE_COUNT_SHIFT);
  362. clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
  363. timing[PARAM_ACTIVE_DELAY_COUNT] <<
  364. UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
  365. writel(val, &clkrst->crc_utmip_pll_cfg2);
  366. /* Set PLL enable delay count and crystal frequency count */
  367. val = readl(&clkrst->crc_utmip_pll_cfg1);
  368. clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
  369. timing[PARAM_ENABLE_DELAY_COUNT] <<
  370. UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
  371. clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
  372. timing[PARAM_XTAL_FREQ_COUNT] <<
  373. UTMIP_XTAL_FREQ_COUNT_SHIFT);
  374. writel(val, &clkrst->crc_utmip_pll_cfg1);
  375. /* Disable Power Down state for PLL */
  376. clrbits_le32(&clkrst->crc_utmip_pll_cfg1,
  377. PLLU_POWERDOWN | PLL_ENABLE_POWERDOWN |
  378. PLL_ACTIVE_POWERDOWN);
  379. /* Recommended PHY settings for EYE diagram */
  380. val = readl(&usbctlr->utmip_xcvr_cfg0);
  381. clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MASK,
  382. 0x4 << UTMIP_XCVR_SETUP_SHIFT);
  383. clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MSB_MASK,
  384. 0x3 << UTMIP_XCVR_SETUP_MSB_SHIFT);
  385. clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW_MSB_MASK,
  386. 0x8 << UTMIP_XCVR_HSSLEW_MSB_SHIFT);
  387. writel(val, &usbctlr->utmip_xcvr_cfg0);
  388. clrsetbits_le32(&usbctlr->utmip_xcvr_cfg1,
  389. UTMIP_XCVR_TERM_RANGE_ADJ_MASK,
  390. 0x7 << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT);
  391. /* Some registers can be controlled from USB1 only. */
  392. if (config->periph_id != PERIPH_ID_USBD) {
  393. clock_enable(PERIPH_ID_USBD);
  394. /* Disable Reset if in Reset state */
  395. reset_set_enable(PERIPH_ID_USBD, 0);
  396. }
  397. usb1ctlr = (struct usb_ctlr *)
  398. ((unsigned long)config->reg & USB1_ADDR_MASK);
  399. val = readl(&usb1ctlr->utmip_bias_cfg0);
  400. setbits_le32(&val, UTMIP_HSDISCON_LEVEL_MSB);
  401. clrsetbits_le32(&val, UTMIP_HSDISCON_LEVEL_MASK,
  402. 0x1 << UTMIP_HSDISCON_LEVEL_SHIFT);
  403. clrsetbits_le32(&val, UTMIP_HSSQUELCH_LEVEL_MASK,
  404. 0x2 << UTMIP_HSSQUELCH_LEVEL_SHIFT);
  405. writel(val, &usb1ctlr->utmip_bias_cfg0);
  406. /* Miscellaneous setting mentioned in Programming Guide */
  407. clrbits_le32(&usbctlr->utmip_misc_cfg0,
  408. UTMIP_SUSPEND_EXIT_ON_EDGE);
  409. }
  410. /* Setting the tracking length time */
  411. clrsetbits_le32(&usbctlr->utmip_bias_cfg1,
  412. UTMIP_BIAS_PDTRK_COUNT_MASK,
  413. timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT);
  414. /* Program debounce time for VBUS to become valid */
  415. clrsetbits_le32(&usbctlr->utmip_debounce_cfg0,
  416. UTMIP_DEBOUNCE_CFG0_MASK,
  417. timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT);
  418. if (timing[PARAM_DEBOUNCE_A_TIME] > 0xFFFF) {
  419. clrsetbits_le32(&usbctlr->utmip_debounce_cfg0,
  420. UTMIP_DEBOUNCE_CFG0_MASK,
  421. (timing[PARAM_DEBOUNCE_A_TIME] >> 1)
  422. << UTMIP_DEBOUNCE_CFG0_SHIFT);
  423. clrsetbits_le32(&usbctlr->utmip_bias_cfg1,
  424. UTMIP_BIAS_DEBOUNCE_TIMESCALE_MASK,
  425. 1 << UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT);
  426. }
  427. setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J);
  428. /* Disable battery charge enabling bit */
  429. setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG);
  430. clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE);
  431. setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL);
  432. /*
  433. * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT
  434. * Setting these fields, together with default values of the
  435. * other fields, results in programming the registers below as
  436. * follows:
  437. * UTMIP_HSRX_CFG0 = 0x9168c000
  438. * UTMIP_HSRX_CFG1 = 0x13
  439. */
  440. /* Set PLL enable delay count and Crystal frequency count */
  441. val = readl(&usbctlr->utmip_hsrx_cfg0);
  442. clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK,
  443. utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT);
  444. clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK,
  445. utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT);
  446. writel(val, &usbctlr->utmip_hsrx_cfg0);
  447. /* Configure the UTMIP_HS_SYNC_START_DLY */
  448. clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1,
  449. UTMIP_HS_SYNC_START_DLY_MASK,
  450. utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT);
  451. /* Preceed the crystal clock disable by >100ns delay. */
  452. udelay(1);
  453. /* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */
  454. setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
  455. if (controller->has_hostpc) {
  456. if (config->periph_id == PERIPH_ID_USBD)
  457. clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
  458. UTMIP_FORCE_PD_SAMP_A_POWERDOWN);
  459. if (config->periph_id == PERIPH_ID_USB2)
  460. clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
  461. UTMIP_FORCE_PD_SAMP_B_POWERDOWN);
  462. if (config->periph_id == PERIPH_ID_USB3)
  463. clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
  464. UTMIP_FORCE_PD_SAMP_C_POWERDOWN);
  465. }
  466. /* Finished the per-controller init. */
  467. /* De-assert UTMIP_RESET to bring out of reset. */
  468. clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
  469. /* Wait for the phy clock to become valid in 100 ms */
  470. for (loop_count = 100000; loop_count != 0; loop_count--) {
  471. if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID)
  472. break;
  473. udelay(1);
  474. }
  475. if (!loop_count)
  476. return -ETIMEDOUT;
  477. /* Disable ICUSB FS/LS transceiver */
  478. clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1);
  479. /* Select UTMI parallel interface */
  480. init_phy_mux(config, PTS_UTMI, init);
  481. /* Deassert power down state */
  482. clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN |
  483. UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN);
  484. clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN |
  485. UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN);
  486. if (controller->has_hostpc) {
  487. /*
  488. * BIAS Pad Power Down is common among all 3 USB
  489. * controllers and can be controlled from USB1 only.
  490. */
  491. usb1ctlr = (struct usb_ctlr *)
  492. ((unsigned long)config->reg & USB1_ADDR_MASK);
  493. clrbits_le32(&usb1ctlr->utmip_bias_cfg0, UTMIP_BIASPD);
  494. udelay(25);
  495. clrbits_le32(&usb1ctlr->utmip_bias_cfg1,
  496. UTMIP_FORCE_PDTRK_POWERDOWN);
  497. }
  498. return 0;
  499. }
  500. #ifdef CONFIG_USB_ULPI
  501. /* if board file does not set a ULPI reference frequency we default to 24MHz */
  502. #ifndef CONFIG_ULPI_REF_CLK
  503. #define CONFIG_ULPI_REF_CLK 24000000
  504. #endif
  505. /* set up the ULPI USB controller with the parameters provided */
  506. static int init_ulpi_usb_controller(struct fdt_usb *config,
  507. enum usb_init_type init)
  508. {
  509. u32 val;
  510. int loop_count;
  511. struct ulpi_viewport ulpi_vp;
  512. struct usb_ctlr *usbctlr = config->reg;
  513. int ret;
  514. /* set up ULPI reference clock on pllp_out4 */
  515. clock_enable(PERIPH_ID_DEV2_OUT);
  516. clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CONFIG_ULPI_REF_CLK);
  517. /* reset ULPI phy */
  518. if (dm_gpio_is_valid(&config->phy_reset_gpio)) {
  519. /*
  520. * This GPIO is typically active-low, and marked as such in
  521. * device tree. dm_gpio_set_value() takes this into account
  522. * and inverts the value we pass here if required. In other
  523. * words, this first call logically asserts the reset signal,
  524. * which typically results in driving the physical GPIO low,
  525. * and the second call logically de-asserts the reset signal,
  526. * which typically results in driver the GPIO high.
  527. */
  528. dm_gpio_set_value(&config->phy_reset_gpio, 1);
  529. mdelay(5);
  530. dm_gpio_set_value(&config->phy_reset_gpio, 0);
  531. }
  532. /* Reset the usb controller */
  533. clock_enable(config->periph_id);
  534. usbf_reset_controller(config, usbctlr);
  535. /* enable pinmux bypass */
  536. setbits_le32(&usbctlr->ulpi_timing_ctrl_0,
  537. ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP);
  538. /* Select ULPI parallel interface */
  539. init_phy_mux(config, PTS_ULPI, init);
  540. /* enable ULPI transceiver */
  541. setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB);
  542. /* configure ULPI transceiver timings */
  543. val = 0;
  544. writel(val, &usbctlr->ulpi_timing_ctrl_1);
  545. val |= ULPI_DATA_TRIMMER_SEL(4);
  546. val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
  547. val |= ULPI_DIR_TRIMMER_SEL(4);
  548. writel(val, &usbctlr->ulpi_timing_ctrl_1);
  549. udelay(10);
  550. val |= ULPI_DATA_TRIMMER_LOAD;
  551. val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
  552. val |= ULPI_DIR_TRIMMER_LOAD;
  553. writel(val, &usbctlr->ulpi_timing_ctrl_1);
  554. /* set up phy for host operation with external vbus supply */
  555. ulpi_vp.port_num = 0;
  556. ulpi_vp.viewport_addr = (u32)&usbctlr->ulpi_viewport;
  557. ret = ulpi_init(&ulpi_vp);
  558. if (ret) {
  559. printf("Tegra ULPI viewport init failed\n");
  560. return ret;
  561. }
  562. ulpi_set_vbus(&ulpi_vp, 1, 1);
  563. ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 0);
  564. /* enable wakeup events */
  565. setbits_le32(&usbctlr->port_sc1, WKCN | WKDS | WKOC);
  566. /* Enable and wait for the phy clock to become valid in 100 ms */
  567. setbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR);
  568. for (loop_count = 100000; loop_count != 0; loop_count--) {
  569. if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID)
  570. break;
  571. udelay(1);
  572. }
  573. if (!loop_count)
  574. return -ETIMEDOUT;
  575. clrbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR);
  576. return 0;
  577. }
  578. #else
  579. static int init_ulpi_usb_controller(struct fdt_usb *config,
  580. enum usb_init_type init)
  581. {
  582. printf("No code to set up ULPI controller, please enable"
  583. "CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT");
  584. return -ENOSYS;
  585. }
  586. #endif
  587. static void config_clock(const u32 timing[])
  588. {
  589. debug("%s: DIVM = %d, DIVN = %d, DIVP = %d, cpcon/lfcon = %d/%d\n",
  590. __func__, timing[PARAM_DIVM], timing[PARAM_DIVN],
  591. timing[PARAM_DIVP], timing[PARAM_CPCON], timing[PARAM_LFCON]);
  592. clock_start_pll(CLOCK_ID_USB,
  593. timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP],
  594. timing[PARAM_CPCON], timing[PARAM_LFCON]);
  595. }
  596. static int fdt_decode_usb(struct udevice *dev, struct fdt_usb *config)
  597. {
  598. const char *phy, *mode;
  599. config->reg = (struct usb_ctlr *)dev_read_addr(dev);
  600. debug("reg=%p\n", config->reg);
  601. mode = dev_read_string(dev, "dr_mode");
  602. if (mode) {
  603. if (0 == strcmp(mode, "host"))
  604. config->dr_mode = DR_MODE_HOST;
  605. else if (0 == strcmp(mode, "peripheral"))
  606. config->dr_mode = DR_MODE_DEVICE;
  607. else if (0 == strcmp(mode, "otg"))
  608. config->dr_mode = DR_MODE_OTG;
  609. else {
  610. debug("%s: Cannot decode dr_mode '%s'\n", __func__,
  611. mode);
  612. return -EINVAL;
  613. }
  614. } else {
  615. config->dr_mode = DR_MODE_HOST;
  616. }
  617. phy = dev_read_string(dev, "phy_type");
  618. config->utmi = phy && 0 == strcmp("utmi", phy);
  619. config->ulpi = phy && 0 == strcmp("ulpi", phy);
  620. config->has_legacy_mode = dev_read_bool(dev, "nvidia,has-legacy-mode");
  621. config->periph_id = clock_decode_periph_id(dev);
  622. if (config->periph_id == PERIPH_ID_NONE) {
  623. debug("%s: Missing/invalid peripheral ID\n", __func__);
  624. return -EINVAL;
  625. }
  626. gpio_request_by_name(dev, "nvidia,vbus-gpio", 0, &config->vbus_gpio,
  627. GPIOD_IS_OUT);
  628. gpio_request_by_name(dev, "nvidia,phy-reset-gpio", 0,
  629. &config->phy_reset_gpio, GPIOD_IS_OUT);
  630. debug("legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, vbus=%d, phy_reset=%d, dr_mode=%d, reg=%p\n",
  631. config->has_legacy_mode, config->utmi, config->ulpi,
  632. config->periph_id, gpio_get_number(&config->vbus_gpio),
  633. gpio_get_number(&config->phy_reset_gpio), config->dr_mode,
  634. config->reg);
  635. return 0;
  636. }
  637. int usb_common_init(struct fdt_usb *config, enum usb_init_type init)
  638. {
  639. int ret = 0;
  640. switch (init) {
  641. case USB_INIT_HOST:
  642. switch (config->dr_mode) {
  643. case DR_MODE_HOST:
  644. case DR_MODE_OTG:
  645. break;
  646. default:
  647. printf("tegrausb: Invalid dr_mode %d for host mode\n",
  648. config->dr_mode);
  649. return -1;
  650. }
  651. break;
  652. case USB_INIT_DEVICE:
  653. if (config->periph_id != PERIPH_ID_USBD) {
  654. printf("tegrausb: Device mode only supported on first USB controller\n");
  655. return -1;
  656. }
  657. if (!config->utmi) {
  658. printf("tegrausb: Device mode only supported with UTMI PHY\n");
  659. return -1;
  660. }
  661. switch (config->dr_mode) {
  662. case DR_MODE_DEVICE:
  663. case DR_MODE_OTG:
  664. break;
  665. default:
  666. printf("tegrausb: Invalid dr_mode %d for device mode\n",
  667. config->dr_mode);
  668. return -1;
  669. }
  670. break;
  671. default:
  672. printf("tegrausb: Unknown USB_INIT_* %d\n", init);
  673. return -1;
  674. }
  675. debug("%d, %d\n", config->utmi, config->ulpi);
  676. if (config->utmi)
  677. ret = init_utmi_usb_controller(config, init);
  678. else if (config->ulpi)
  679. ret = init_ulpi_usb_controller(config, init);
  680. if (ret)
  681. return ret;
  682. set_up_vbus(config, init);
  683. config->init_type = init;
  684. return 0;
  685. }
  686. void usb_common_uninit(struct fdt_usb *priv)
  687. {
  688. struct usb_ctlr *usbctlr;
  689. usbctlr = priv->reg;
  690. /* Stop controller */
  691. writel(0, &usbctlr->usb_cmd);
  692. udelay(1000);
  693. /* Initiate controller reset */
  694. writel(2, &usbctlr->usb_cmd);
  695. udelay(1000);
  696. }
  697. static const struct ehci_ops tegra_ehci_ops = {
  698. .set_usb_mode = tegra_ehci_set_usbmode,
  699. .get_port_speed = tegra_ehci_get_port_speed,
  700. .powerup_fixup = tegra_ehci_powerup_fixup,
  701. };
  702. static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
  703. {
  704. struct fdt_usb *priv = dev_get_priv(dev);
  705. int ret;
  706. ret = fdt_decode_usb(dev, priv);
  707. if (ret)
  708. return ret;
  709. priv->type = dev_get_driver_data(dev);
  710. return 0;
  711. }
  712. static int ehci_usb_probe(struct udevice *dev)
  713. {
  714. struct usb_platdata *plat = dev_get_platdata(dev);
  715. struct fdt_usb *priv = dev_get_priv(dev);
  716. struct ehci_hccr *hccr;
  717. struct ehci_hcor *hcor;
  718. static bool clk_done;
  719. int ret;
  720. ret = usb_common_init(priv, plat->init_type);
  721. if (ret)
  722. return ret;
  723. hccr = (struct ehci_hccr *)&priv->reg->cap_length;
  724. hcor = (struct ehci_hcor *)&priv->reg->usb_cmd;
  725. if (!clk_done) {
  726. config_clock(get_pll_timing(&fdt_usb_controllers[priv->type]));
  727. clk_done = true;
  728. }
  729. return ehci_register(dev, hccr, hcor, &tegra_ehci_ops, 0,
  730. plat->init_type);
  731. }
  732. static const struct udevice_id ehci_usb_ids[] = {
  733. { .compatible = "nvidia,tegra20-ehci", .data = USB_CTLR_T20 },
  734. { .compatible = "nvidia,tegra30-ehci", .data = USB_CTLR_T30 },
  735. { .compatible = "nvidia,tegra114-ehci", .data = USB_CTLR_T114 },
  736. { .compatible = "nvidia,tegra210-ehci", .data = USB_CTLR_T210 },
  737. { }
  738. };
  739. U_BOOT_DRIVER(usb_ehci) = {
  740. .name = "ehci_tegra",
  741. .id = UCLASS_USB,
  742. .of_match = ehci_usb_ids,
  743. .ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
  744. .probe = ehci_usb_probe,
  745. .remove = ehci_deregister,
  746. .ops = &ehci_usb_ops,
  747. .platdata_auto_alloc_size = sizeof(struct usb_platdata),
  748. .priv_auto_alloc_size = sizeof(struct fdt_usb),
  749. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  750. };