ehci-mxs.c 4.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale i.MX28 USB Host driver
  4. *
  5. * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  6. * on behalf of DENX Software Engineering GmbH
  7. */
  8. #include <common.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <errno.h>
  12. #include "ehci.h"
  13. /* This DIGCTL register ungates clock to USB */
  14. #define HW_DIGCTL_CTRL 0x8001c000
  15. #define HW_DIGCTL_CTRL_USB0_CLKGATE (1 << 2)
  16. #define HW_DIGCTL_CTRL_USB1_CLKGATE (1 << 16)
  17. struct ehci_mxs_port {
  18. uint32_t usb_regs;
  19. struct mxs_usbphy_regs *phy_regs;
  20. struct mxs_register_32 *pll;
  21. uint32_t pll_en_bits;
  22. uint32_t pll_dis_bits;
  23. uint32_t gate_bits;
  24. };
  25. static const struct ehci_mxs_port mxs_port[] = {
  26. #ifdef CONFIG_EHCI_MXS_PORT0
  27. {
  28. MXS_USBCTRL0_BASE,
  29. (struct mxs_usbphy_regs *)MXS_USBPHY0_BASE,
  30. (struct mxs_register_32 *)(MXS_CLKCTRL_BASE +
  31. offsetof(struct mxs_clkctrl_regs,
  32. hw_clkctrl_pll0ctrl0_reg)),
  33. CLKCTRL_PLL0CTRL0_EN_USB_CLKS | CLKCTRL_PLL0CTRL0_POWER,
  34. CLKCTRL_PLL0CTRL0_EN_USB_CLKS,
  35. HW_DIGCTL_CTRL_USB0_CLKGATE,
  36. },
  37. #endif
  38. #ifdef CONFIG_EHCI_MXS_PORT1
  39. {
  40. MXS_USBCTRL1_BASE,
  41. (struct mxs_usbphy_regs *)MXS_USBPHY1_BASE,
  42. (struct mxs_register_32 *)(MXS_CLKCTRL_BASE +
  43. offsetof(struct mxs_clkctrl_regs,
  44. hw_clkctrl_pll1ctrl0_reg)),
  45. CLKCTRL_PLL1CTRL0_EN_USB_CLKS | CLKCTRL_PLL1CTRL0_POWER,
  46. CLKCTRL_PLL1CTRL0_EN_USB_CLKS,
  47. HW_DIGCTL_CTRL_USB1_CLKGATE,
  48. },
  49. #endif
  50. };
  51. static int ehci_mxs_toggle_clock(const struct ehci_mxs_port *port, int enable)
  52. {
  53. struct mxs_register_32 *digctl_ctrl =
  54. (struct mxs_register_32 *)HW_DIGCTL_CTRL;
  55. int pll_offset, dig_offset;
  56. if (enable) {
  57. pll_offset = offsetof(struct mxs_register_32, reg_set);
  58. dig_offset = offsetof(struct mxs_register_32, reg_clr);
  59. writel(port->gate_bits, (u32)&digctl_ctrl->reg + dig_offset);
  60. writel(port->pll_en_bits, (u32)port->pll + pll_offset);
  61. } else {
  62. pll_offset = offsetof(struct mxs_register_32, reg_clr);
  63. dig_offset = offsetof(struct mxs_register_32, reg_set);
  64. writel(port->pll_dis_bits, (u32)port->pll + pll_offset);
  65. writel(port->gate_bits, (u32)&digctl_ctrl->reg + dig_offset);
  66. }
  67. return 0;
  68. }
  69. int __weak board_ehci_hcd_init(int port)
  70. {
  71. return 0;
  72. }
  73. int __weak board_ehci_hcd_exit(int port)
  74. {
  75. return 0;
  76. }
  77. int ehci_hcd_init(int index, enum usb_init_type init,
  78. struct ehci_hccr **hccr, struct ehci_hcor **hcor)
  79. {
  80. int ret;
  81. uint32_t usb_base, cap_base;
  82. const struct ehci_mxs_port *port;
  83. if ((index < 0) || (index >= ARRAY_SIZE(mxs_port))) {
  84. printf("Invalid port index (index = %d)!\n", index);
  85. return -EINVAL;
  86. }
  87. ret = board_ehci_hcd_init(index);
  88. if (ret)
  89. return ret;
  90. port = &mxs_port[index];
  91. /* Reset the PHY block */
  92. writel(USBPHY_CTRL_SFTRST, &port->phy_regs->hw_usbphy_ctrl_set);
  93. udelay(10);
  94. writel(USBPHY_CTRL_SFTRST | USBPHY_CTRL_CLKGATE,
  95. &port->phy_regs->hw_usbphy_ctrl_clr);
  96. /* Enable USB clock */
  97. ret = ehci_mxs_toggle_clock(port, 1);
  98. if (ret)
  99. return ret;
  100. /* Start USB PHY */
  101. writel(0, &port->phy_regs->hw_usbphy_pwd);
  102. /* Enable UTMI+ Level 2 and Level 3 compatibility */
  103. writel(USBPHY_CTRL_ENUTMILEVEL3 | USBPHY_CTRL_ENUTMILEVEL2 | 1,
  104. &port->phy_regs->hw_usbphy_ctrl_set);
  105. usb_base = port->usb_regs + 0x100;
  106. *hccr = (struct ehci_hccr *)usb_base;
  107. cap_base = ehci_readl(&(*hccr)->cr_capbase);
  108. *hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base));
  109. return 0;
  110. }
  111. int ehci_hcd_stop(int index)
  112. {
  113. int ret;
  114. uint32_t usb_base, cap_base, tmp;
  115. struct ehci_hccr *hccr;
  116. struct ehci_hcor *hcor;
  117. const struct ehci_mxs_port *port;
  118. if ((index < 0) || (index >= ARRAY_SIZE(mxs_port))) {
  119. printf("Invalid port index (index = %d)!\n", index);
  120. return -EINVAL;
  121. }
  122. port = &mxs_port[index];
  123. /* Stop the USB port */
  124. usb_base = port->usb_regs + 0x100;
  125. hccr = (struct ehci_hccr *)usb_base;
  126. cap_base = ehci_readl(&hccr->cr_capbase);
  127. hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base));
  128. tmp = ehci_readl(&hcor->or_usbcmd);
  129. tmp &= ~CMD_RUN;
  130. ehci_writel(&hcor->or_usbcmd, tmp);
  131. /* Disable the PHY */
  132. tmp = USBPHY_PWD_RXPWDRX | USBPHY_PWD_RXPWDDIFF |
  133. USBPHY_PWD_RXPWD1PT1 | USBPHY_PWD_RXPWDENV |
  134. USBPHY_PWD_TXPWDV2I | USBPHY_PWD_TXPWDIBIAS |
  135. USBPHY_PWD_TXPWDFS;
  136. writel(tmp, &port->phy_regs->hw_usbphy_pwd);
  137. /* Disable USB clock */
  138. ret = ehci_mxs_toggle_clock(port, 0);
  139. board_ehci_hcd_exit(index);
  140. return ret;
  141. }