ehci-mx6.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
  4. * Copyright (C) 2010 Freescale Semiconductor, Inc.
  5. */
  6. #include <common.h>
  7. #include <usb.h>
  8. #include <errno.h>
  9. #include <wait_bit.h>
  10. #include <linux/compiler.h>
  11. #include <usb/ehci-ci.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/imx-regs.h>
  14. #include <asm/arch/clock.h>
  15. #include <asm/mach-imx/iomux-v3.h>
  16. #include <asm/mach-imx/sys_proto.h>
  17. #include <dm.h>
  18. #include <asm/mach-types.h>
  19. #include <power/regulator.h>
  20. #include <linux/usb/otg.h>
  21. #include "ehci.h"
  22. DECLARE_GLOBAL_DATA_PTR;
  23. #define USB_OTGREGS_OFFSET 0x000
  24. #define USB_H1REGS_OFFSET 0x200
  25. #define USB_H2REGS_OFFSET 0x400
  26. #define USB_H3REGS_OFFSET 0x600
  27. #define USB_OTHERREGS_OFFSET 0x800
  28. #define USB_H1_CTRL_OFFSET 0x04
  29. #define USBPHY_CTRL 0x00000030
  30. #define USBPHY_CTRL_SET 0x00000034
  31. #define USBPHY_CTRL_CLR 0x00000038
  32. #define USBPHY_CTRL_TOG 0x0000003c
  33. #define USBPHY_PWD 0x00000000
  34. #define USBPHY_CTRL_SFTRST 0x80000000
  35. #define USBPHY_CTRL_CLKGATE 0x40000000
  36. #define USBPHY_CTRL_ENUTMILEVEL3 0x00008000
  37. #define USBPHY_CTRL_ENUTMILEVEL2 0x00004000
  38. #define USBPHY_CTRL_OTG_ID 0x08000000
  39. #define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000
  40. #define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000
  41. #define ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000
  42. #define ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000
  43. #define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000
  44. #define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040
  45. #define USBNC_OFFSET 0x200
  46. #define USBNC_PHY_STATUS_OFFSET 0x23C
  47. #define USBNC_PHYSTATUS_ID_DIG (1 << 4) /* otg_id status */
  48. #define USBNC_PHYCFG2_ACAENB (1 << 4) /* otg_id detection enable */
  49. #define UCTRL_PWR_POL (1 << 9) /* OTG Polarity of Power Pin */
  50. #define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
  51. #define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
  52. /* USBCMD */
  53. #define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
  54. #define UCMD_RESET (1 << 1) /* controller reset */
  55. #if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
  56. static const unsigned phy_bases[] = {
  57. USB_PHY0_BASE_ADDR,
  58. #if defined(USB_PHY1_BASE_ADDR)
  59. USB_PHY1_BASE_ADDR,
  60. #endif
  61. };
  62. static void usb_internal_phy_clock_gate(int index, int on)
  63. {
  64. void __iomem *phy_reg;
  65. if (index >= ARRAY_SIZE(phy_bases))
  66. return;
  67. phy_reg = (void __iomem *)phy_bases[index];
  68. phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
  69. writel(USBPHY_CTRL_CLKGATE, phy_reg);
  70. }
  71. static void usb_power_config(int index)
  72. {
  73. #if defined(CONFIG_MX7ULP)
  74. struct usbphy_regs __iomem *usbphy =
  75. (struct usbphy_regs __iomem *)USB_PHY0_BASE_ADDR;
  76. if (index > 0)
  77. return;
  78. writel(ANADIG_USB2_CHRG_DETECT_EN_B |
  79. ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
  80. &usbphy->usb1_chrg_detect);
  81. scg_enable_usb_pll(true);
  82. #else
  83. struct anatop_regs __iomem *anatop =
  84. (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
  85. void __iomem *chrg_detect;
  86. void __iomem *pll_480_ctrl_clr;
  87. void __iomem *pll_480_ctrl_set;
  88. switch (index) {
  89. case 0:
  90. chrg_detect = &anatop->usb1_chrg_detect;
  91. pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr;
  92. pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set;
  93. break;
  94. case 1:
  95. chrg_detect = &anatop->usb2_chrg_detect;
  96. pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr;
  97. pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set;
  98. break;
  99. default:
  100. return;
  101. }
  102. /*
  103. * Some phy and power's special controls
  104. * 1. The external charger detector needs to be disabled
  105. * or the signal at DP will be poor
  106. * 2. The PLL's power and output to usb
  107. * is totally controlled by IC, so the Software only needs
  108. * to enable them at initializtion.
  109. */
  110. writel(ANADIG_USB2_CHRG_DETECT_EN_B |
  111. ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
  112. chrg_detect);
  113. writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
  114. pll_480_ctrl_clr);
  115. writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
  116. ANADIG_USB2_PLL_480_CTRL_POWER |
  117. ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
  118. pll_480_ctrl_set);
  119. #endif
  120. }
  121. /* Return 0 : host node, <>0 : device mode */
  122. static int usb_phy_enable(int index, struct usb_ehci *ehci)
  123. {
  124. void __iomem *phy_reg;
  125. void __iomem *phy_ctrl;
  126. void __iomem *usb_cmd;
  127. int ret;
  128. if (index >= ARRAY_SIZE(phy_bases))
  129. return 0;
  130. phy_reg = (void __iomem *)phy_bases[index];
  131. phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
  132. usb_cmd = (void __iomem *)&ehci->usbcmd;
  133. /* Stop then Reset */
  134. clrbits_le32(usb_cmd, UCMD_RUN_STOP);
  135. ret = wait_for_bit_le32(usb_cmd, UCMD_RUN_STOP, false, 10000, false);
  136. if (ret)
  137. return ret;
  138. setbits_le32(usb_cmd, UCMD_RESET);
  139. ret = wait_for_bit_le32(usb_cmd, UCMD_RESET, false, 10000, false);
  140. if (ret)
  141. return ret;
  142. /* Reset USBPHY module */
  143. setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST);
  144. udelay(10);
  145. /* Remove CLKGATE and SFTRST */
  146. clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
  147. udelay(10);
  148. /* Power up the PHY */
  149. writel(0, phy_reg + USBPHY_PWD);
  150. /* enable FS/LS device */
  151. setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 |
  152. USBPHY_CTRL_ENUTMILEVEL3);
  153. return 0;
  154. }
  155. int usb_phy_mode(int port)
  156. {
  157. void __iomem *phy_reg;
  158. void __iomem *phy_ctrl;
  159. u32 val;
  160. phy_reg = (void __iomem *)phy_bases[port];
  161. phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
  162. val = readl(phy_ctrl);
  163. if (val & USBPHY_CTRL_OTG_ID)
  164. return USB_INIT_DEVICE;
  165. else
  166. return USB_INIT_HOST;
  167. }
  168. #if defined(CONFIG_MX7ULP)
  169. struct usbnc_regs {
  170. u32 ctrl1;
  171. u32 ctrl2;
  172. u32 reserve0[2];
  173. u32 hsic_ctrl;
  174. };
  175. #else
  176. /* Base address for this IP block is 0x02184800 */
  177. struct usbnc_regs {
  178. u32 ctrl[4]; /* otg/host1-3 */
  179. u32 uh2_hsic_ctrl;
  180. u32 uh3_hsic_ctrl;
  181. u32 otg_phy_ctrl_0;
  182. u32 uh1_phy_ctrl_0;
  183. };
  184. #endif
  185. #elif defined(CONFIG_MX7)
  186. struct usbnc_regs {
  187. u32 ctrl1;
  188. u32 ctrl2;
  189. u32 reserve1[10];
  190. u32 phy_cfg1;
  191. u32 phy_cfg2;
  192. u32 reserve2;
  193. u32 phy_status;
  194. u32 reserve3[4];
  195. u32 adp_cfg1;
  196. u32 adp_cfg2;
  197. u32 adp_status;
  198. };
  199. static void usb_power_config(int index)
  200. {
  201. struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
  202. (0x10000 * index) + USBNC_OFFSET);
  203. void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);
  204. /*
  205. * Clear the ACAENB to enable usb_otg_id detection,
  206. * otherwise it is the ACA detection enabled.
  207. */
  208. clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
  209. }
  210. int usb_phy_mode(int port)
  211. {
  212. struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
  213. (0x10000 * port) + USBNC_OFFSET);
  214. void __iomem *status = (void __iomem *)(&usbnc->phy_status);
  215. u32 val;
  216. val = readl(status);
  217. if (val & USBNC_PHYSTATUS_ID_DIG)
  218. return USB_INIT_DEVICE;
  219. else
  220. return USB_INIT_HOST;
  221. }
  222. #endif
  223. static void usb_oc_config(int index)
  224. {
  225. #if defined(CONFIG_MX6)
  226. struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
  227. USB_OTHERREGS_OFFSET);
  228. void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
  229. #elif defined(CONFIG_MX7) || defined(CONFIG_MX7ULP)
  230. struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
  231. (0x10000 * index) + USBNC_OFFSET);
  232. void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1);
  233. #endif
  234. #if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
  235. /* mx6qarm2 seems to required a different setting*/
  236. clrbits_le32(ctrl, UCTRL_OVER_CUR_POL);
  237. #else
  238. setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
  239. #endif
  240. setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
  241. /* Set power polarity to high active */
  242. #ifdef CONFIG_MXC_USB_OTG_HACTIVE
  243. setbits_le32(ctrl, UCTRL_PWR_POL);
  244. #else
  245. clrbits_le32(ctrl, UCTRL_PWR_POL);
  246. #endif
  247. }
  248. /**
  249. * board_usb_phy_mode - override usb phy mode
  250. * @port: usb host/otg port
  251. *
  252. * Target board specific, override usb_phy_mode.
  253. * When usb-otg is used as usb host port, iomux pad usb_otg_id can be
  254. * left disconnected in this case usb_phy_mode will not be able to identify
  255. * the phy mode that usb port is used.
  256. * Machine file overrides board_usb_phy_mode.
  257. *
  258. * Return: USB_INIT_DEVICE or USB_INIT_HOST
  259. */
  260. int __weak board_usb_phy_mode(int port)
  261. {
  262. return usb_phy_mode(port);
  263. }
  264. /**
  265. * board_ehci_hcd_init - set usb vbus voltage
  266. * @port: usb otg port
  267. *
  268. * Target board specific, setup iomux pad to setup supply vbus voltage
  269. * for usb otg port. Machine board file overrides board_ehci_hcd_init
  270. *
  271. * Return: 0 Success
  272. */
  273. int __weak board_ehci_hcd_init(int port)
  274. {
  275. return 0;
  276. }
  277. /**
  278. * board_ehci_power - enables/disables usb vbus voltage
  279. * @port: usb otg port
  280. * @on: on/off vbus voltage
  281. *
  282. * Enables/disables supply vbus voltage for usb otg port.
  283. * Machine board file overrides board_ehci_power
  284. *
  285. * Return: 0 Success
  286. */
  287. int __weak board_ehci_power(int port, int on)
  288. {
  289. return 0;
  290. }
  291. int ehci_mx6_common_init(struct usb_ehci *ehci, int index)
  292. {
  293. int ret;
  294. enable_usboh3_clk(1);
  295. mdelay(1);
  296. /* Do board specific initialization */
  297. ret = board_ehci_hcd_init(index);
  298. if (ret)
  299. return ret;
  300. usb_power_config(index);
  301. usb_oc_config(index);
  302. #if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
  303. usb_internal_phy_clock_gate(index, 1);
  304. usb_phy_enable(index, ehci);
  305. #endif
  306. return 0;
  307. }
  308. #if !CONFIG_IS_ENABLED(DM_USB)
  309. int ehci_hcd_init(int index, enum usb_init_type init,
  310. struct ehci_hccr **hccr, struct ehci_hcor **hcor)
  311. {
  312. enum usb_init_type type;
  313. #if defined(CONFIG_MX6)
  314. u32 controller_spacing = 0x200;
  315. #elif defined(CONFIG_MX7) || defined(CONFIG_MX7ULP)
  316. u32 controller_spacing = 0x10000;
  317. #endif
  318. struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
  319. (controller_spacing * index));
  320. int ret;
  321. if (index > 3)
  322. return -EINVAL;
  323. if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
  324. if (usb_fused((ulong)ehci)) {
  325. printf("SoC fuse indicates USB@0x%lx is unavailable.\n",
  326. (ulong)ehci);
  327. return -ENODEV;
  328. }
  329. }
  330. ret = ehci_mx6_common_init(ehci, index);
  331. if (ret)
  332. return ret;
  333. type = board_usb_phy_mode(index);
  334. if (hccr && hcor) {
  335. *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
  336. *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
  337. HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
  338. }
  339. if ((type == init) || (type == USB_INIT_DEVICE))
  340. board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1);
  341. if (type != init)
  342. return -ENODEV;
  343. if (type == USB_INIT_DEVICE)
  344. return 0;
  345. setbits_le32(&ehci->usbmode, CM_HOST);
  346. writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
  347. setbits_le32(&ehci->portsc, USB_EN);
  348. mdelay(10);
  349. return 0;
  350. }
  351. int ehci_hcd_stop(int index)
  352. {
  353. return 0;
  354. }
  355. #else
  356. struct ehci_mx6_priv_data {
  357. struct ehci_ctrl ctrl;
  358. struct usb_ehci *ehci;
  359. struct udevice *vbus_supply;
  360. enum usb_init_type init_type;
  361. int portnr;
  362. };
  363. static int mx6_init_after_reset(struct ehci_ctrl *dev)
  364. {
  365. struct ehci_mx6_priv_data *priv = dev->priv;
  366. enum usb_init_type type = priv->init_type;
  367. struct usb_ehci *ehci = priv->ehci;
  368. int ret;
  369. ret = ehci_mx6_common_init(priv->ehci, priv->portnr);
  370. if (ret)
  371. return ret;
  372. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  373. if (priv->vbus_supply) {
  374. ret = regulator_set_enable(priv->vbus_supply,
  375. (type == USB_INIT_DEVICE) ?
  376. false : true);
  377. if (ret) {
  378. puts("Error enabling VBUS supply\n");
  379. return ret;
  380. }
  381. }
  382. #endif
  383. if (type == USB_INIT_DEVICE)
  384. return 0;
  385. setbits_le32(&ehci->usbmode, CM_HOST);
  386. writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
  387. setbits_le32(&ehci->portsc, USB_EN);
  388. mdelay(10);
  389. return 0;
  390. }
  391. static const struct ehci_ops mx6_ehci_ops = {
  392. .init_after_reset = mx6_init_after_reset
  393. };
  394. static int ehci_usb_phy_mode(struct udevice *dev)
  395. {
  396. struct usb_platdata *plat = dev_get_platdata(dev);
  397. void *__iomem addr = (void *__iomem)devfdt_get_addr(dev);
  398. void *__iomem phy_ctrl, *__iomem phy_status;
  399. const void *blob = gd->fdt_blob;
  400. int offset = dev_of_offset(dev), phy_off;
  401. u32 val;
  402. /*
  403. * About fsl,usbphy, Refer to
  404. * Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt.
  405. */
  406. if (is_mx6() || is_mx7ulp()) {
  407. phy_off = fdtdec_lookup_phandle(blob,
  408. offset,
  409. "fsl,usbphy");
  410. if (phy_off < 0)
  411. return -EINVAL;
  412. addr = (void __iomem *)fdtdec_get_addr(blob, phy_off,
  413. "reg");
  414. if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
  415. return -EINVAL;
  416. phy_ctrl = (void __iomem *)(addr + USBPHY_CTRL);
  417. val = readl(phy_ctrl);
  418. if (val & USBPHY_CTRL_OTG_ID)
  419. plat->init_type = USB_INIT_DEVICE;
  420. else
  421. plat->init_type = USB_INIT_HOST;
  422. } else if (is_mx7()) {
  423. phy_status = (void __iomem *)(addr +
  424. USBNC_PHY_STATUS_OFFSET);
  425. val = readl(phy_status);
  426. if (val & USBNC_PHYSTATUS_ID_DIG)
  427. plat->init_type = USB_INIT_DEVICE;
  428. else
  429. plat->init_type = USB_INIT_HOST;
  430. } else {
  431. return -EINVAL;
  432. }
  433. return 0;
  434. }
  435. static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
  436. {
  437. struct usb_platdata *plat = dev_get_platdata(dev);
  438. enum usb_dr_mode dr_mode;
  439. dr_mode = usb_get_dr_mode(dev->node);
  440. switch (dr_mode) {
  441. case USB_DR_MODE_HOST:
  442. plat->init_type = USB_INIT_HOST;
  443. break;
  444. case USB_DR_MODE_PERIPHERAL:
  445. plat->init_type = USB_INIT_DEVICE;
  446. break;
  447. case USB_DR_MODE_OTG:
  448. case USB_DR_MODE_UNKNOWN:
  449. return ehci_usb_phy_mode(dev);
  450. };
  451. return 0;
  452. }
  453. static int ehci_usb_bind(struct udevice *dev)
  454. {
  455. /*
  456. * TODO:
  457. * This driver is only partly converted to DT probing and still uses
  458. * a tremendous amount of hard-coded addresses. To make things worse,
  459. * the driver depends on specific sequential indexing of controllers,
  460. * from which it derives offsets in the PHY and ANATOP register sets.
  461. *
  462. * Here we attempt to calculate these indexes from DT information as
  463. * well as we can. The USB controllers on all existing iMX6 SoCs
  464. * are placed next to each other, at addresses incremented by 0x200,
  465. * and iMX7 their addresses are shifted by 0x10000.
  466. * Thus, the index is derived from the multiple of 0x200 (0x10000 for
  467. * iMX7) offset from the first controller address.
  468. *
  469. * However, to complete conversion of this driver to DT probing, the
  470. * following has to be done:
  471. * - DM clock framework support for iMX must be implemented
  472. * - usb_power_config() has to be converted to clock framework
  473. * -> Thus, the ad-hoc "index" variable goes away.
  474. * - USB PHY handling has to be factored out into separate driver
  475. * -> Thus, the ad-hoc "index" variable goes away from the PHY
  476. * code, the PHY driver must parse it's address from DT. This
  477. * USB driver must find the PHY driver via DT phandle.
  478. * -> usb_power_config() shall be moved to PHY driver
  479. * With these changes in place, the ad-hoc indexing goes away and
  480. * the driver is fully converted to DT probing.
  481. */
  482. u32 controller_spacing = is_mx7() ? 0x10000 : 0x200;
  483. fdt_addr_t addr = devfdt_get_addr_index(dev, 0);
  484. dev->req_seq = (addr - USB_BASE_ADDR) / controller_spacing;
  485. return 0;
  486. }
  487. static int ehci_usb_probe(struct udevice *dev)
  488. {
  489. struct usb_platdata *plat = dev_get_platdata(dev);
  490. struct usb_ehci *ehci = (struct usb_ehci *)devfdt_get_addr(dev);
  491. struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
  492. enum usb_init_type type = plat->init_type;
  493. struct ehci_hccr *hccr;
  494. struct ehci_hcor *hcor;
  495. int ret;
  496. if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
  497. if (usb_fused((ulong)ehci)) {
  498. printf("SoC fuse indicates USB@0x%lx is unavailable.\n",
  499. (ulong)ehci);
  500. return -ENODEV;
  501. }
  502. }
  503. priv->ehci = ehci;
  504. priv->portnr = dev->seq;
  505. priv->init_type = type;
  506. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  507. ret = device_get_supply_regulator(dev, "vbus-supply",
  508. &priv->vbus_supply);
  509. if (ret)
  510. debug("%s: No vbus supply\n", dev->name);
  511. #endif
  512. ret = ehci_mx6_common_init(ehci, priv->portnr);
  513. if (ret)
  514. return ret;
  515. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  516. if (priv->vbus_supply) {
  517. ret = regulator_set_enable(priv->vbus_supply,
  518. (type == USB_INIT_DEVICE) ?
  519. false : true);
  520. if (ret) {
  521. puts("Error enabling VBUS supply\n");
  522. return ret;
  523. }
  524. }
  525. #endif
  526. if (priv->init_type == USB_INIT_HOST) {
  527. setbits_le32(&ehci->usbmode, CM_HOST);
  528. writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
  529. setbits_le32(&ehci->portsc, USB_EN);
  530. }
  531. mdelay(10);
  532. hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
  533. hcor = (struct ehci_hcor *)((uint32_t)hccr +
  534. HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
  535. return ehci_register(dev, hccr, hcor, &mx6_ehci_ops, 0, priv->init_type);
  536. }
  537. static const struct udevice_id mx6_usb_ids[] = {
  538. { .compatible = "fsl,imx27-usb" },
  539. { }
  540. };
  541. U_BOOT_DRIVER(usb_mx6) = {
  542. .name = "ehci_mx6",
  543. .id = UCLASS_USB,
  544. .of_match = mx6_usb_ids,
  545. .ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
  546. .bind = ehci_usb_bind,
  547. .probe = ehci_usb_probe,
  548. .remove = ehci_deregister,
  549. .ops = &ehci_usb_ops,
  550. .platdata_auto_alloc_size = sizeof(struct usb_platdata),
  551. .priv_auto_alloc_size = sizeof(struct ehci_mx6_priv_data),
  552. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  553. };
  554. #endif