ehci-hcd.c 48 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*-
  3. * Copyright (c) 2007-2008, Juniper Networks, Inc.
  4. * Copyright (c) 2008, Excito Elektronik i Skåne AB
  5. * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
  6. *
  7. * All rights reserved.
  8. */
  9. #include <common.h>
  10. #include <cpu_func.h>
  11. #include <dm.h>
  12. #include <errno.h>
  13. #include <asm/byteorder.h>
  14. #include <asm/unaligned.h>
  15. #include <usb.h>
  16. #include <asm/io.h>
  17. #include <malloc.h>
  18. #include <memalign.h>
  19. #include <watchdog.h>
  20. #include <dm/device_compat.h>
  21. #include <linux/compiler.h>
  22. #include "ehci.h"
  23. #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
  24. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  25. #endif
  26. /*
  27. * EHCI spec page 20 says that the HC may take up to 16 uFrames (= 4ms) to halt.
  28. * Let's time out after 8 to have a little safety margin on top of that.
  29. */
  30. #define HCHALT_TIMEOUT (8 * 1000)
  31. #if !CONFIG_IS_ENABLED(DM_USB)
  32. static struct ehci_ctrl ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
  33. #endif
  34. #define ALIGN_END_ADDR(type, ptr, size) \
  35. ((unsigned long)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN))
  36. static struct descriptor {
  37. struct usb_hub_descriptor hub;
  38. struct usb_device_descriptor device;
  39. struct usb_linux_config_descriptor config;
  40. struct usb_linux_interface_descriptor interface;
  41. struct usb_endpoint_descriptor endpoint;
  42. } __attribute__ ((packed)) descriptor = {
  43. {
  44. 0x8, /* bDescLength */
  45. 0x29, /* bDescriptorType: hub descriptor */
  46. 2, /* bNrPorts -- runtime modified */
  47. 0, /* wHubCharacteristics */
  48. 10, /* bPwrOn2PwrGood */
  49. 0, /* bHubCntrCurrent */
  50. { /* Device removable */
  51. } /* at most 7 ports! XXX */
  52. },
  53. {
  54. 0x12, /* bLength */
  55. 1, /* bDescriptorType: UDESC_DEVICE */
  56. cpu_to_le16(0x0200), /* bcdUSB: v2.0 */
  57. 9, /* bDeviceClass: UDCLASS_HUB */
  58. 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
  59. 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */
  60. 64, /* bMaxPacketSize: 64 bytes */
  61. 0x0000, /* idVendor */
  62. 0x0000, /* idProduct */
  63. cpu_to_le16(0x0100), /* bcdDevice */
  64. 1, /* iManufacturer */
  65. 2, /* iProduct */
  66. 0, /* iSerialNumber */
  67. 1 /* bNumConfigurations: 1 */
  68. },
  69. {
  70. 0x9,
  71. 2, /* bDescriptorType: UDESC_CONFIG */
  72. cpu_to_le16(0x19),
  73. 1, /* bNumInterface */
  74. 1, /* bConfigurationValue */
  75. 0, /* iConfiguration */
  76. 0x40, /* bmAttributes: UC_SELF_POWER */
  77. 0 /* bMaxPower */
  78. },
  79. {
  80. 0x9, /* bLength */
  81. 4, /* bDescriptorType: UDESC_INTERFACE */
  82. 0, /* bInterfaceNumber */
  83. 0, /* bAlternateSetting */
  84. 1, /* bNumEndpoints */
  85. 9, /* bInterfaceClass: UICLASS_HUB */
  86. 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
  87. 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
  88. 0 /* iInterface */
  89. },
  90. {
  91. 0x7, /* bLength */
  92. 5, /* bDescriptorType: UDESC_ENDPOINT */
  93. 0x81, /* bEndpointAddress:
  94. * UE_DIR_IN | EHCI_INTR_ENDPT
  95. */
  96. 3, /* bmAttributes: UE_INTERRUPT */
  97. 8, /* wMaxPacketSize */
  98. 255 /* bInterval */
  99. },
  100. };
  101. #if defined(CONFIG_EHCI_IS_TDI)
  102. #define ehci_is_TDI() (1)
  103. #else
  104. #define ehci_is_TDI() (0)
  105. #endif
  106. static struct ehci_ctrl *ehci_get_ctrl(struct usb_device *udev)
  107. {
  108. #if CONFIG_IS_ENABLED(DM_USB)
  109. return dev_get_priv(usb_get_bus(udev->dev));
  110. #else
  111. return udev->controller;
  112. #endif
  113. }
  114. static int ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg)
  115. {
  116. return PORTSC_PSPD(reg);
  117. }
  118. static void ehci_set_usbmode(struct ehci_ctrl *ctrl)
  119. {
  120. uint32_t tmp;
  121. uint32_t *reg_ptr;
  122. reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd + USBMODE);
  123. tmp = ehci_readl(reg_ptr);
  124. tmp |= USBMODE_CM_HC;
  125. #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
  126. tmp |= USBMODE_BE;
  127. #else
  128. tmp &= ~USBMODE_BE;
  129. #endif
  130. ehci_writel(reg_ptr, tmp);
  131. }
  132. static void ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg,
  133. uint32_t *reg)
  134. {
  135. mdelay(50);
  136. }
  137. static uint32_t *ehci_get_portsc_register(struct ehci_ctrl *ctrl, int port)
  138. {
  139. int max_ports = HCS_N_PORTS(ehci_readl(&ctrl->hccr->cr_hcsparams));
  140. if (port < 0 || port >= max_ports) {
  141. /* Printing the message would cause a scan failure! */
  142. debug("The request port(%u) exceeds maximum port number\n",
  143. port);
  144. return NULL;
  145. }
  146. return (uint32_t *)&ctrl->hcor->or_portsc[port];
  147. }
  148. static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
  149. {
  150. uint32_t result;
  151. do {
  152. result = ehci_readl(ptr);
  153. udelay(5);
  154. if (result == ~(uint32_t)0)
  155. return -1;
  156. result &= mask;
  157. if (result == done)
  158. return 0;
  159. usec--;
  160. } while (usec > 0);
  161. return -1;
  162. }
  163. static int ehci_reset(struct ehci_ctrl *ctrl)
  164. {
  165. uint32_t cmd;
  166. int ret = 0;
  167. cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
  168. cmd = (cmd & ~CMD_RUN) | CMD_RESET;
  169. ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
  170. ret = handshake((uint32_t *)&ctrl->hcor->or_usbcmd,
  171. CMD_RESET, 0, 250 * 1000);
  172. if (ret < 0) {
  173. printf("EHCI fail to reset\n");
  174. goto out;
  175. }
  176. if (ehci_is_TDI())
  177. ctrl->ops.set_usb_mode(ctrl);
  178. #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH
  179. cmd = ehci_readl(&ctrl->hcor->or_txfilltuning);
  180. cmd &= ~TXFIFO_THRESH_MASK;
  181. cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH);
  182. ehci_writel(&ctrl->hcor->or_txfilltuning, cmd);
  183. #endif
  184. out:
  185. return ret;
  186. }
  187. static int ehci_shutdown(struct ehci_ctrl *ctrl)
  188. {
  189. int i, ret = 0;
  190. uint32_t cmd, reg;
  191. int max_ports = HCS_N_PORTS(ehci_readl(&ctrl->hccr->cr_hcsparams));
  192. cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
  193. /* If not run, directly return */
  194. if (!(cmd & CMD_RUN))
  195. return 0;
  196. cmd &= ~(CMD_PSE | CMD_ASE);
  197. ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
  198. ret = handshake(&ctrl->hcor->or_usbsts, STS_ASS | STS_PSS, 0,
  199. 100 * 1000);
  200. if (!ret) {
  201. for (i = 0; i < max_ports; i++) {
  202. reg = ehci_readl(&ctrl->hcor->or_portsc[i]);
  203. reg |= EHCI_PS_SUSP;
  204. ehci_writel(&ctrl->hcor->or_portsc[i], reg);
  205. }
  206. cmd &= ~CMD_RUN;
  207. ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
  208. ret = handshake(&ctrl->hcor->or_usbsts, STS_HALT, STS_HALT,
  209. HCHALT_TIMEOUT);
  210. }
  211. if (ret)
  212. puts("EHCI failed to shut down host controller.\n");
  213. return ret;
  214. }
  215. static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
  216. {
  217. uint32_t delta, next;
  218. unsigned long addr = (unsigned long)buf;
  219. int idx;
  220. if (addr != ALIGN(addr, ARCH_DMA_MINALIGN))
  221. debug("EHCI-HCD: Misaligned buffer address (%p)\n", buf);
  222. flush_dcache_range(addr, ALIGN(addr + sz, ARCH_DMA_MINALIGN));
  223. idx = 0;
  224. while (idx < QT_BUFFER_CNT) {
  225. td->qt_buffer[idx] = cpu_to_hc32(virt_to_phys((void *)addr));
  226. td->qt_buffer_hi[idx] = 0;
  227. next = (addr + EHCI_PAGE_SIZE) & ~(EHCI_PAGE_SIZE - 1);
  228. delta = next - addr;
  229. if (delta >= sz)
  230. break;
  231. sz -= delta;
  232. addr = next;
  233. idx++;
  234. }
  235. if (idx == QT_BUFFER_CNT) {
  236. printf("out of buffer pointers (%zu bytes left)\n", sz);
  237. return -1;
  238. }
  239. return 0;
  240. }
  241. static inline u8 ehci_encode_speed(enum usb_device_speed speed)
  242. {
  243. #define QH_HIGH_SPEED 2
  244. #define QH_FULL_SPEED 0
  245. #define QH_LOW_SPEED 1
  246. if (speed == USB_SPEED_HIGH)
  247. return QH_HIGH_SPEED;
  248. if (speed == USB_SPEED_LOW)
  249. return QH_LOW_SPEED;
  250. return QH_FULL_SPEED;
  251. }
  252. static void ehci_update_endpt2_dev_n_port(struct usb_device *udev,
  253. struct QH *qh)
  254. {
  255. uint8_t portnr = 0;
  256. uint8_t hubaddr = 0;
  257. if (udev->speed != USB_SPEED_LOW && udev->speed != USB_SPEED_FULL)
  258. return;
  259. usb_find_usb2_hub_address_port(udev, &hubaddr, &portnr);
  260. qh->qh_endpt2 |= cpu_to_hc32(QH_ENDPT2_PORTNUM(portnr) |
  261. QH_ENDPT2_HUBADDR(hubaddr));
  262. }
  263. static int ehci_enable_async(struct ehci_ctrl *ctrl)
  264. {
  265. u32 cmd;
  266. int ret;
  267. /* Enable async. schedule. */
  268. cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
  269. if (cmd & CMD_ASE)
  270. return 0;
  271. cmd |= CMD_ASE;
  272. ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
  273. ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, STS_ASS,
  274. 100 * 1000);
  275. if (ret < 0)
  276. printf("EHCI fail timeout STS_ASS set\n");
  277. return ret;
  278. }
  279. static int ehci_disable_async(struct ehci_ctrl *ctrl)
  280. {
  281. u32 cmd;
  282. int ret;
  283. if (ctrl->async_locked)
  284. return 0;
  285. /* Disable async schedule. */
  286. cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
  287. if (!(cmd & CMD_ASE))
  288. return 0;
  289. cmd &= ~CMD_ASE;
  290. ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
  291. ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, 0,
  292. 100 * 1000);
  293. if (ret < 0)
  294. printf("EHCI fail timeout STS_ASS reset\n");
  295. return ret;
  296. }
  297. static int
  298. ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
  299. int length, struct devrequest *req)
  300. {
  301. ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN);
  302. struct qTD *qtd;
  303. int qtd_count = 0;
  304. int qtd_counter = 0;
  305. volatile struct qTD *vtd;
  306. unsigned long ts;
  307. uint32_t *tdp;
  308. uint32_t endpt, maxpacket, token, usbsts, qhtoken;
  309. uint32_t c, toggle;
  310. int timeout;
  311. int ret = 0;
  312. struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
  313. debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
  314. buffer, length, req);
  315. if (req != NULL)
  316. debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
  317. req->request, req->request,
  318. req->requesttype, req->requesttype,
  319. le16_to_cpu(req->value), le16_to_cpu(req->value),
  320. le16_to_cpu(req->index));
  321. #define PKT_ALIGN 512
  322. /*
  323. * The USB transfer is split into qTD transfers. Eeach qTD transfer is
  324. * described by a transfer descriptor (the qTD). The qTDs form a linked
  325. * list with a queue head (QH).
  326. *
  327. * Each qTD transfer starts with a new USB packet, i.e. a packet cannot
  328. * have its beginning in a qTD transfer and its end in the following
  329. * one, so the qTD transfer lengths have to be chosen accordingly.
  330. *
  331. * Each qTD transfer uses up to QT_BUFFER_CNT data buffers, mapped to
  332. * single pages. The first data buffer can start at any offset within a
  333. * page (not considering the cache-line alignment issues), while the
  334. * following buffers must be page-aligned. There is no alignment
  335. * constraint on the size of a qTD transfer.
  336. */
  337. if (req != NULL)
  338. /* 1 qTD will be needed for SETUP, and 1 for ACK. */
  339. qtd_count += 1 + 1;
  340. if (length > 0 || req == NULL) {
  341. /*
  342. * Determine the qTD transfer size that will be used for the
  343. * data payload (not considering the first qTD transfer, which
  344. * may be longer or shorter, and the final one, which may be
  345. * shorter).
  346. *
  347. * In order to keep each packet within a qTD transfer, the qTD
  348. * transfer size is aligned to PKT_ALIGN, which is a multiple of
  349. * wMaxPacketSize (except in some cases for interrupt transfers,
  350. * see comment in submit_int_msg()).
  351. *
  352. * By default, i.e. if the input buffer is aligned to PKT_ALIGN,
  353. * QT_BUFFER_CNT full pages will be used.
  354. */
  355. int xfr_sz = QT_BUFFER_CNT;
  356. /*
  357. * However, if the input buffer is not aligned to PKT_ALIGN, the
  358. * qTD transfer size will be one page shorter, and the first qTD
  359. * data buffer of each transfer will be page-unaligned.
  360. */
  361. if ((unsigned long)buffer & (PKT_ALIGN - 1))
  362. xfr_sz--;
  363. /* Convert the qTD transfer size to bytes. */
  364. xfr_sz *= EHCI_PAGE_SIZE;
  365. /*
  366. * Approximate by excess the number of qTDs that will be
  367. * required for the data payload. The exact formula is way more
  368. * complicated and saves at most 2 qTDs, i.e. a total of 128
  369. * bytes.
  370. */
  371. qtd_count += 2 + length / xfr_sz;
  372. }
  373. /*
  374. * Threshold value based on the worst-case total size of the allocated qTDs for
  375. * a mass-storage transfer of 65535 blocks of 512 bytes.
  376. */
  377. #if CONFIG_SYS_MALLOC_LEN <= 64 + 128 * 1024
  378. #warning CONFIG_SYS_MALLOC_LEN may be too small for EHCI
  379. #endif
  380. qtd = memalign(USB_DMA_MINALIGN, qtd_count * sizeof(struct qTD));
  381. if (qtd == NULL) {
  382. printf("unable to allocate TDs\n");
  383. return -1;
  384. }
  385. memset(qh, 0, sizeof(struct QH));
  386. memset(qtd, 0, qtd_count * sizeof(*qtd));
  387. toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
  388. /*
  389. * Setup QH (3.6 in ehci-r10.pdf)
  390. *
  391. * qh_link ................. 03-00 H
  392. * qh_endpt1 ............... 07-04 H
  393. * qh_endpt2 ............... 0B-08 H
  394. * - qh_curtd
  395. * qh_overlay.qt_next ...... 13-10 H
  396. * - qh_overlay.qt_altnext
  397. */
  398. qh->qh_link = cpu_to_hc32(virt_to_phys(&ctrl->qh_list) | QH_LINK_TYPE_QH);
  399. c = (dev->speed != USB_SPEED_HIGH) && !usb_pipeendpoint(pipe);
  400. maxpacket = usb_maxpacket(dev, pipe);
  401. endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) |
  402. QH_ENDPT1_MAXPKTLEN(maxpacket) | QH_ENDPT1_H(0) |
  403. QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD) |
  404. QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) |
  405. QH_ENDPT1_DEVADDR(usb_pipedevice(pipe));
  406. /* Force FS for fsl HS quirk */
  407. if (!ctrl->has_fsl_erratum_a005275)
  408. endpt |= QH_ENDPT1_EPS(ehci_encode_speed(dev->speed));
  409. else
  410. endpt |= QH_ENDPT1_EPS(ehci_encode_speed(QH_FULL_SPEED));
  411. qh->qh_endpt1 = cpu_to_hc32(endpt);
  412. endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0);
  413. qh->qh_endpt2 = cpu_to_hc32(endpt);
  414. ehci_update_endpt2_dev_n_port(dev, qh);
  415. qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  416. qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  417. tdp = &qh->qh_overlay.qt_next;
  418. if (req != NULL) {
  419. /*
  420. * Setup request qTD (3.5 in ehci-r10.pdf)
  421. *
  422. * qt_next ................ 03-00 H
  423. * qt_altnext ............. 07-04 H
  424. * qt_token ............... 0B-08 H
  425. *
  426. * [ buffer, buffer_hi ] loaded with "req".
  427. */
  428. qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  429. qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  430. token = QT_TOKEN_DT(0) | QT_TOKEN_TOTALBYTES(sizeof(*req)) |
  431. QT_TOKEN_IOC(0) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
  432. QT_TOKEN_PID(QT_TOKEN_PID_SETUP) |
  433. QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
  434. qtd[qtd_counter].qt_token = cpu_to_hc32(token);
  435. if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req))) {
  436. printf("unable to construct SETUP TD\n");
  437. goto fail;
  438. }
  439. /* Update previous qTD! */
  440. *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter]));
  441. tdp = &qtd[qtd_counter++].qt_next;
  442. toggle = 1;
  443. }
  444. if (length > 0 || req == NULL) {
  445. uint8_t *buf_ptr = buffer;
  446. int left_length = length;
  447. do {
  448. /*
  449. * Determine the size of this qTD transfer. By default,
  450. * QT_BUFFER_CNT full pages can be used.
  451. */
  452. int xfr_bytes = QT_BUFFER_CNT * EHCI_PAGE_SIZE;
  453. /*
  454. * However, if the input buffer is not page-aligned, the
  455. * portion of the first page before the buffer start
  456. * offset within that page is unusable.
  457. */
  458. xfr_bytes -= (unsigned long)buf_ptr & (EHCI_PAGE_SIZE - 1);
  459. /*
  460. * In order to keep each packet within a qTD transfer,
  461. * align the qTD transfer size to PKT_ALIGN.
  462. */
  463. xfr_bytes &= ~(PKT_ALIGN - 1);
  464. /*
  465. * This transfer may be shorter than the available qTD
  466. * transfer size that has just been computed.
  467. */
  468. xfr_bytes = min(xfr_bytes, left_length);
  469. /*
  470. * Setup request qTD (3.5 in ehci-r10.pdf)
  471. *
  472. * qt_next ................ 03-00 H
  473. * qt_altnext ............. 07-04 H
  474. * qt_token ............... 0B-08 H
  475. *
  476. * [ buffer, buffer_hi ] loaded with "buffer".
  477. */
  478. qtd[qtd_counter].qt_next =
  479. cpu_to_hc32(QT_NEXT_TERMINATE);
  480. qtd[qtd_counter].qt_altnext =
  481. cpu_to_hc32(QT_NEXT_TERMINATE);
  482. token = QT_TOKEN_DT(toggle) |
  483. QT_TOKEN_TOTALBYTES(xfr_bytes) |
  484. QT_TOKEN_IOC(req == NULL) | QT_TOKEN_CPAGE(0) |
  485. QT_TOKEN_CERR(3) |
  486. QT_TOKEN_PID(usb_pipein(pipe) ?
  487. QT_TOKEN_PID_IN : QT_TOKEN_PID_OUT) |
  488. QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
  489. qtd[qtd_counter].qt_token = cpu_to_hc32(token);
  490. if (ehci_td_buffer(&qtd[qtd_counter], buf_ptr,
  491. xfr_bytes)) {
  492. printf("unable to construct DATA TD\n");
  493. goto fail;
  494. }
  495. /* Update previous qTD! */
  496. *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter]));
  497. tdp = &qtd[qtd_counter++].qt_next;
  498. /*
  499. * Data toggle has to be adjusted since the qTD transfer
  500. * size is not always an even multiple of
  501. * wMaxPacketSize.
  502. */
  503. if ((xfr_bytes / maxpacket) & 1)
  504. toggle ^= 1;
  505. buf_ptr += xfr_bytes;
  506. left_length -= xfr_bytes;
  507. } while (left_length > 0);
  508. }
  509. if (req != NULL) {
  510. /*
  511. * Setup request qTD (3.5 in ehci-r10.pdf)
  512. *
  513. * qt_next ................ 03-00 H
  514. * qt_altnext ............. 07-04 H
  515. * qt_token ............... 0B-08 H
  516. */
  517. qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  518. qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  519. token = QT_TOKEN_DT(1) | QT_TOKEN_TOTALBYTES(0) |
  520. QT_TOKEN_IOC(1) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
  521. QT_TOKEN_PID(usb_pipein(pipe) ?
  522. QT_TOKEN_PID_OUT : QT_TOKEN_PID_IN) |
  523. QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
  524. qtd[qtd_counter].qt_token = cpu_to_hc32(token);
  525. /* Update previous qTD! */
  526. *tdp = cpu_to_hc32(virt_to_phys(&qtd[qtd_counter]));
  527. tdp = &qtd[qtd_counter++].qt_next;
  528. }
  529. ctrl->qh_list.qh_link = cpu_to_hc32(virt_to_phys(qh) | QH_LINK_TYPE_QH);
  530. /* Flush dcache */
  531. flush_dcache_range((unsigned long)&ctrl->qh_list,
  532. ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
  533. flush_dcache_range((unsigned long)qh, ALIGN_END_ADDR(struct QH, qh, 1));
  534. flush_dcache_range((unsigned long)qtd,
  535. ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
  536. usbsts = ehci_readl(&ctrl->hcor->or_usbsts);
  537. ehci_writel(&ctrl->hcor->or_usbsts, (usbsts & 0x3f));
  538. ret = ehci_enable_async(ctrl);
  539. if (ret)
  540. goto fail;
  541. /* Wait for TDs to be processed. */
  542. ts = get_timer(0);
  543. vtd = &qtd[qtd_counter - 1];
  544. timeout = USB_TIMEOUT_MS(pipe);
  545. do {
  546. /* Invalidate dcache */
  547. invalidate_dcache_range((unsigned long)&ctrl->qh_list,
  548. ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
  549. invalidate_dcache_range((unsigned long)qh,
  550. ALIGN_END_ADDR(struct QH, qh, 1));
  551. invalidate_dcache_range((unsigned long)qtd,
  552. ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
  553. token = hc32_to_cpu(vtd->qt_token);
  554. if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE))
  555. break;
  556. WATCHDOG_RESET();
  557. } while (get_timer(ts) < timeout);
  558. qhtoken = hc32_to_cpu(qh->qh_overlay.qt_token);
  559. ctrl->qh_list.qh_link = cpu_to_hc32(virt_to_phys(&ctrl->qh_list) | QH_LINK_TYPE_QH);
  560. flush_dcache_range((unsigned long)&ctrl->qh_list,
  561. ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
  562. /*
  563. * Invalidate the memory area occupied by buffer
  564. * Don't try to fix the buffer alignment, if it isn't properly
  565. * aligned it's upper layer's fault so let invalidate_dcache_range()
  566. * vow about it. But we have to fix the length as it's actual
  567. * transfer length and can be unaligned. This is potentially
  568. * dangerous operation, it's responsibility of the calling
  569. * code to make sure enough space is reserved.
  570. */
  571. if (buffer != NULL && length > 0)
  572. invalidate_dcache_range((unsigned long)buffer,
  573. ALIGN((unsigned long)buffer + length, ARCH_DMA_MINALIGN));
  574. /* Check that the TD processing happened */
  575. if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)
  576. printf("EHCI timed out on TD - token=%#x\n", token);
  577. ret = ehci_disable_async(ctrl);
  578. if (ret)
  579. goto fail;
  580. if (!(QT_TOKEN_GET_STATUS(qhtoken) & QT_TOKEN_STATUS_ACTIVE)) {
  581. debug("TOKEN=%#x\n", qhtoken);
  582. switch (QT_TOKEN_GET_STATUS(qhtoken) &
  583. ~(QT_TOKEN_STATUS_SPLITXSTATE | QT_TOKEN_STATUS_PERR)) {
  584. case 0:
  585. toggle = QT_TOKEN_GET_DT(qhtoken);
  586. usb_settoggle(dev, usb_pipeendpoint(pipe),
  587. usb_pipeout(pipe), toggle);
  588. dev->status = 0;
  589. break;
  590. case QT_TOKEN_STATUS_HALTED:
  591. dev->status = USB_ST_STALLED;
  592. break;
  593. case QT_TOKEN_STATUS_ACTIVE | QT_TOKEN_STATUS_DATBUFERR:
  594. case QT_TOKEN_STATUS_DATBUFERR:
  595. dev->status = USB_ST_BUF_ERR;
  596. break;
  597. case QT_TOKEN_STATUS_HALTED | QT_TOKEN_STATUS_BABBLEDET:
  598. case QT_TOKEN_STATUS_BABBLEDET:
  599. dev->status = USB_ST_BABBLE_DET;
  600. break;
  601. default:
  602. dev->status = USB_ST_CRC_ERR;
  603. if (QT_TOKEN_GET_STATUS(qhtoken) & QT_TOKEN_STATUS_HALTED)
  604. dev->status |= USB_ST_STALLED;
  605. break;
  606. }
  607. dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(qhtoken);
  608. } else {
  609. dev->act_len = 0;
  610. #ifndef CONFIG_USB_EHCI_FARADAY
  611. debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
  612. dev->devnum, ehci_readl(&ctrl->hcor->or_usbsts),
  613. ehci_readl(&ctrl->hcor->or_portsc[0]),
  614. ehci_readl(&ctrl->hcor->or_portsc[1]));
  615. #endif
  616. }
  617. free(qtd);
  618. return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
  619. fail:
  620. free(qtd);
  621. return -1;
  622. }
  623. static int ehci_submit_root(struct usb_device *dev, unsigned long pipe,
  624. void *buffer, int length, struct devrequest *req)
  625. {
  626. uint8_t tmpbuf[4];
  627. u16 typeReq;
  628. void *srcptr = NULL;
  629. int len, srclen;
  630. uint32_t reg;
  631. uint32_t *status_reg;
  632. int port = le16_to_cpu(req->index) & 0xff;
  633. struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
  634. srclen = 0;
  635. debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n",
  636. req->request, req->request,
  637. req->requesttype, req->requesttype,
  638. le16_to_cpu(req->value), le16_to_cpu(req->index));
  639. typeReq = req->request | req->requesttype << 8;
  640. switch (typeReq) {
  641. case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
  642. case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
  643. case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
  644. status_reg = ctrl->ops.get_portsc_register(ctrl, port - 1);
  645. if (!status_reg)
  646. return -1;
  647. break;
  648. default:
  649. status_reg = NULL;
  650. break;
  651. }
  652. switch (typeReq) {
  653. case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
  654. switch (le16_to_cpu(req->value) >> 8) {
  655. case USB_DT_DEVICE:
  656. debug("USB_DT_DEVICE request\n");
  657. srcptr = &descriptor.device;
  658. srclen = descriptor.device.bLength;
  659. break;
  660. case USB_DT_CONFIG:
  661. debug("USB_DT_CONFIG config\n");
  662. srcptr = &descriptor.config;
  663. srclen = descriptor.config.bLength +
  664. descriptor.interface.bLength +
  665. descriptor.endpoint.bLength;
  666. break;
  667. case USB_DT_STRING:
  668. debug("USB_DT_STRING config\n");
  669. switch (le16_to_cpu(req->value) & 0xff) {
  670. case 0: /* Language */
  671. srcptr = "\4\3\1\0";
  672. srclen = 4;
  673. break;
  674. case 1: /* Vendor */
  675. srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
  676. srclen = 14;
  677. break;
  678. case 2: /* Product */
  679. srcptr = "\52\3E\0H\0C\0I\0 "
  680. "\0H\0o\0s\0t\0 "
  681. "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
  682. srclen = 42;
  683. break;
  684. default:
  685. debug("unknown value DT_STRING %x\n",
  686. le16_to_cpu(req->value));
  687. goto unknown;
  688. }
  689. break;
  690. default:
  691. debug("unknown value %x\n", le16_to_cpu(req->value));
  692. goto unknown;
  693. }
  694. break;
  695. case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
  696. switch (le16_to_cpu(req->value) >> 8) {
  697. case USB_DT_HUB:
  698. debug("USB_DT_HUB config\n");
  699. srcptr = &descriptor.hub;
  700. srclen = descriptor.hub.bLength;
  701. break;
  702. default:
  703. debug("unknown value %x\n", le16_to_cpu(req->value));
  704. goto unknown;
  705. }
  706. break;
  707. case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
  708. debug("USB_REQ_SET_ADDRESS\n");
  709. ctrl->rootdev = le16_to_cpu(req->value);
  710. break;
  711. case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
  712. debug("USB_REQ_SET_CONFIGURATION\n");
  713. /* Nothing to do */
  714. break;
  715. case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
  716. tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
  717. tmpbuf[1] = 0;
  718. srcptr = tmpbuf;
  719. srclen = 2;
  720. break;
  721. case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
  722. memset(tmpbuf, 0, 4);
  723. reg = ehci_readl(status_reg);
  724. if (reg & EHCI_PS_CS)
  725. tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
  726. if (reg & EHCI_PS_PE)
  727. tmpbuf[0] |= USB_PORT_STAT_ENABLE;
  728. if (reg & EHCI_PS_SUSP)
  729. tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
  730. if (reg & EHCI_PS_OCA)
  731. tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
  732. if (reg & EHCI_PS_PR)
  733. tmpbuf[0] |= USB_PORT_STAT_RESET;
  734. if (reg & EHCI_PS_PP)
  735. tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
  736. if (ehci_is_TDI()) {
  737. switch (ctrl->ops.get_port_speed(ctrl, reg)) {
  738. case PORTSC_PSPD_FS:
  739. break;
  740. case PORTSC_PSPD_LS:
  741. tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
  742. break;
  743. case PORTSC_PSPD_HS:
  744. default:
  745. tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
  746. break;
  747. }
  748. } else {
  749. tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
  750. }
  751. if (reg & EHCI_PS_CSC)
  752. tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
  753. if (reg & EHCI_PS_PEC)
  754. tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
  755. if (reg & EHCI_PS_OCC)
  756. tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
  757. if (ctrl->portreset & (1 << port))
  758. tmpbuf[2] |= USB_PORT_STAT_C_RESET;
  759. srcptr = tmpbuf;
  760. srclen = 4;
  761. break;
  762. case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
  763. reg = ehci_readl(status_reg);
  764. reg &= ~EHCI_PS_CLEAR;
  765. switch (le16_to_cpu(req->value)) {
  766. case USB_PORT_FEAT_ENABLE:
  767. reg |= EHCI_PS_PE;
  768. ehci_writel(status_reg, reg);
  769. break;
  770. case USB_PORT_FEAT_POWER:
  771. if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams))) {
  772. reg |= EHCI_PS_PP;
  773. ehci_writel(status_reg, reg);
  774. }
  775. break;
  776. case USB_PORT_FEAT_RESET:
  777. if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS &&
  778. !ehci_is_TDI() &&
  779. EHCI_PS_IS_LOWSPEED(reg)) {
  780. /* Low speed device, give up ownership. */
  781. debug("port %d low speed --> companion\n",
  782. port - 1);
  783. reg |= EHCI_PS_PO;
  784. ehci_writel(status_reg, reg);
  785. return -ENXIO;
  786. } else {
  787. int ret;
  788. /* Disable chirp for HS erratum */
  789. if (ctrl->has_fsl_erratum_a005275)
  790. reg |= PORTSC_FSL_PFSC;
  791. reg |= EHCI_PS_PR;
  792. reg &= ~EHCI_PS_PE;
  793. ehci_writel(status_reg, reg);
  794. /*
  795. * caller must wait, then call GetPortStatus
  796. * usb 2.0 specification say 50 ms resets on
  797. * root
  798. */
  799. ctrl->ops.powerup_fixup(ctrl, status_reg, &reg);
  800. ehci_writel(status_reg, reg & ~EHCI_PS_PR);
  801. /*
  802. * A host controller must terminate the reset
  803. * and stabilize the state of the port within
  804. * 2 milliseconds
  805. */
  806. ret = handshake(status_reg, EHCI_PS_PR, 0,
  807. 2 * 1000);
  808. if (!ret) {
  809. reg = ehci_readl(status_reg);
  810. if ((reg & (EHCI_PS_PE | EHCI_PS_CS))
  811. == EHCI_PS_CS && !ehci_is_TDI()) {
  812. debug("port %d full speed --> companion\n", port - 1);
  813. reg &= ~EHCI_PS_CLEAR;
  814. reg |= EHCI_PS_PO;
  815. ehci_writel(status_reg, reg);
  816. return -ENXIO;
  817. } else {
  818. ctrl->portreset |= 1 << port;
  819. }
  820. } else {
  821. printf("port(%d) reset error\n",
  822. port - 1);
  823. }
  824. }
  825. break;
  826. case USB_PORT_FEAT_TEST:
  827. ehci_shutdown(ctrl);
  828. reg &= ~(0xf << 16);
  829. reg |= ((le16_to_cpu(req->index) >> 8) & 0xf) << 16;
  830. ehci_writel(status_reg, reg);
  831. break;
  832. default:
  833. debug("unknown feature %x\n", le16_to_cpu(req->value));
  834. goto unknown;
  835. }
  836. /* unblock posted writes */
  837. (void) ehci_readl(&ctrl->hcor->or_usbcmd);
  838. break;
  839. case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
  840. reg = ehci_readl(status_reg);
  841. reg &= ~EHCI_PS_CLEAR;
  842. switch (le16_to_cpu(req->value)) {
  843. case USB_PORT_FEAT_ENABLE:
  844. reg &= ~EHCI_PS_PE;
  845. break;
  846. case USB_PORT_FEAT_C_ENABLE:
  847. reg |= EHCI_PS_PE;
  848. break;
  849. case USB_PORT_FEAT_POWER:
  850. if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams)))
  851. reg &= ~EHCI_PS_PP;
  852. break;
  853. case USB_PORT_FEAT_C_CONNECTION:
  854. reg |= EHCI_PS_CSC;
  855. break;
  856. case USB_PORT_FEAT_OVER_CURRENT:
  857. reg |= EHCI_PS_OCC;
  858. break;
  859. case USB_PORT_FEAT_C_RESET:
  860. ctrl->portreset &= ~(1 << port);
  861. break;
  862. default:
  863. debug("unknown feature %x\n", le16_to_cpu(req->value));
  864. goto unknown;
  865. }
  866. ehci_writel(status_reg, reg);
  867. /* unblock posted write */
  868. (void) ehci_readl(&ctrl->hcor->or_usbcmd);
  869. break;
  870. default:
  871. debug("Unknown request\n");
  872. goto unknown;
  873. }
  874. mdelay(1);
  875. len = min3(srclen, (int)le16_to_cpu(req->length), length);
  876. if (srcptr != NULL && len > 0)
  877. memcpy(buffer, srcptr, len);
  878. else
  879. debug("Len is 0\n");
  880. dev->act_len = len;
  881. dev->status = 0;
  882. return 0;
  883. unknown:
  884. debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n",
  885. req->requesttype, req->request, le16_to_cpu(req->value),
  886. le16_to_cpu(req->index), le16_to_cpu(req->length));
  887. dev->act_len = 0;
  888. dev->status = USB_ST_STALLED;
  889. return -1;
  890. }
  891. static const struct ehci_ops default_ehci_ops = {
  892. .set_usb_mode = ehci_set_usbmode,
  893. .get_port_speed = ehci_get_port_speed,
  894. .powerup_fixup = ehci_powerup_fixup,
  895. .get_portsc_register = ehci_get_portsc_register,
  896. };
  897. static void ehci_setup_ops(struct ehci_ctrl *ctrl, const struct ehci_ops *ops)
  898. {
  899. if (!ops) {
  900. ctrl->ops = default_ehci_ops;
  901. } else {
  902. ctrl->ops = *ops;
  903. if (!ctrl->ops.set_usb_mode)
  904. ctrl->ops.set_usb_mode = ehci_set_usbmode;
  905. if (!ctrl->ops.get_port_speed)
  906. ctrl->ops.get_port_speed = ehci_get_port_speed;
  907. if (!ctrl->ops.powerup_fixup)
  908. ctrl->ops.powerup_fixup = ehci_powerup_fixup;
  909. if (!ctrl->ops.get_portsc_register)
  910. ctrl->ops.get_portsc_register =
  911. ehci_get_portsc_register;
  912. }
  913. }
  914. #if !CONFIG_IS_ENABLED(DM_USB)
  915. void ehci_set_controller_priv(int index, void *priv, const struct ehci_ops *ops)
  916. {
  917. struct ehci_ctrl *ctrl = &ehcic[index];
  918. ctrl->priv = priv;
  919. ehci_setup_ops(ctrl, ops);
  920. }
  921. void *ehci_get_controller_priv(int index)
  922. {
  923. return ehcic[index].priv;
  924. }
  925. #endif
  926. static int ehci_common_init(struct ehci_ctrl *ctrl, uint tweaks)
  927. {
  928. struct QH *qh_list;
  929. struct QH *periodic;
  930. uint32_t reg;
  931. uint32_t cmd;
  932. int i;
  933. /* Set the high address word (aka segment) for 64-bit controller */
  934. if (ehci_readl(&ctrl->hccr->cr_hccparams) & 1)
  935. ehci_writel(&ctrl->hcor->or_ctrldssegment, 0);
  936. qh_list = &ctrl->qh_list;
  937. /* Set head of reclaim list */
  938. memset(qh_list, 0, sizeof(*qh_list));
  939. qh_list->qh_link = cpu_to_hc32(virt_to_phys(qh_list) | QH_LINK_TYPE_QH);
  940. qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) |
  941. QH_ENDPT1_EPS(USB_SPEED_HIGH));
  942. qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  943. qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  944. qh_list->qh_overlay.qt_token =
  945. cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED));
  946. flush_dcache_range((unsigned long)qh_list,
  947. ALIGN_END_ADDR(struct QH, qh_list, 1));
  948. /* Set async. queue head pointer. */
  949. ehci_writel(&ctrl->hcor->or_asynclistaddr, virt_to_phys(qh_list));
  950. /*
  951. * Set up periodic list
  952. * Step 1: Parent QH for all periodic transfers.
  953. */
  954. ctrl->periodic_schedules = 0;
  955. periodic = &ctrl->periodic_queue;
  956. memset(periodic, 0, sizeof(*periodic));
  957. periodic->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
  958. periodic->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  959. periodic->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  960. flush_dcache_range((unsigned long)periodic,
  961. ALIGN_END_ADDR(struct QH, periodic, 1));
  962. /*
  963. * Step 2: Setup frame-list: Every microframe, USB tries the same list.
  964. * In particular, device specifications on polling frequency
  965. * are disregarded. Keyboards seem to send NAK/NYet reliably
  966. * when polled with an empty buffer.
  967. *
  968. * Split Transactions will be spread across microframes using
  969. * S-mask and C-mask.
  970. */
  971. if (ctrl->periodic_list == NULL)
  972. ctrl->periodic_list = memalign(4096, 1024 * 4);
  973. if (!ctrl->periodic_list)
  974. return -ENOMEM;
  975. for (i = 0; i < 1024; i++) {
  976. ctrl->periodic_list[i] = cpu_to_hc32((unsigned long)periodic
  977. | QH_LINK_TYPE_QH);
  978. }
  979. flush_dcache_range((unsigned long)ctrl->periodic_list,
  980. ALIGN_END_ADDR(uint32_t, ctrl->periodic_list,
  981. 1024));
  982. /* Set periodic list base address */
  983. ehci_writel(&ctrl->hcor->or_periodiclistbase,
  984. (unsigned long)ctrl->periodic_list);
  985. reg = ehci_readl(&ctrl->hccr->cr_hcsparams);
  986. descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
  987. debug("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
  988. /* Port Indicators */
  989. if (HCS_INDICATOR(reg))
  990. put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
  991. | 0x80, &descriptor.hub.wHubCharacteristics);
  992. /* Port Power Control */
  993. if (HCS_PPC(reg))
  994. put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
  995. | 0x01, &descriptor.hub.wHubCharacteristics);
  996. /* Start the host controller. */
  997. cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
  998. /*
  999. * Philips, Intel, and maybe others need CMD_RUN before the
  1000. * root hub will detect new devices (why?); NEC doesn't
  1001. */
  1002. cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
  1003. cmd |= CMD_RUN;
  1004. ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
  1005. if (!(tweaks & EHCI_TWEAK_NO_INIT_CF)) {
  1006. /* take control over the ports */
  1007. cmd = ehci_readl(&ctrl->hcor->or_configflag);
  1008. cmd |= FLAG_CF;
  1009. ehci_writel(&ctrl->hcor->or_configflag, cmd);
  1010. }
  1011. /* unblock posted write */
  1012. cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
  1013. mdelay(5);
  1014. reg = HC_VERSION(ehci_readl(&ctrl->hccr->cr_capbase));
  1015. printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff);
  1016. return 0;
  1017. }
  1018. #if !CONFIG_IS_ENABLED(DM_USB)
  1019. int usb_lowlevel_stop(int index)
  1020. {
  1021. ehci_shutdown(&ehcic[index]);
  1022. return ehci_hcd_stop(index);
  1023. }
  1024. int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
  1025. {
  1026. struct ehci_ctrl *ctrl = &ehcic[index];
  1027. uint tweaks = 0;
  1028. int rc;
  1029. /**
  1030. * Set ops to default_ehci_ops, ehci_hcd_init should call
  1031. * ehci_set_controller_priv to change any of these function pointers.
  1032. */
  1033. ctrl->ops = default_ehci_ops;
  1034. rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor);
  1035. if (rc)
  1036. return rc;
  1037. if (!ctrl->hccr || !ctrl->hcor)
  1038. return -1;
  1039. if (init == USB_INIT_DEVICE)
  1040. goto done;
  1041. /* EHCI spec section 4.1 */
  1042. if (ehci_reset(ctrl))
  1043. return -1;
  1044. #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
  1045. rc = ehci_hcd_init(index, init, &ctrl->hccr, &ctrl->hcor);
  1046. if (rc)
  1047. return rc;
  1048. #endif
  1049. #ifdef CONFIG_USB_EHCI_FARADAY
  1050. tweaks |= EHCI_TWEAK_NO_INIT_CF;
  1051. #endif
  1052. rc = ehci_common_init(ctrl, tweaks);
  1053. if (rc)
  1054. return rc;
  1055. ctrl->rootdev = 0;
  1056. done:
  1057. *controller = &ehcic[index];
  1058. return 0;
  1059. }
  1060. #endif
  1061. static int _ehci_submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
  1062. void *buffer, int length)
  1063. {
  1064. if (usb_pipetype(pipe) != PIPE_BULK) {
  1065. debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
  1066. return -1;
  1067. }
  1068. return ehci_submit_async(dev, pipe, buffer, length, NULL);
  1069. }
  1070. static int _ehci_submit_control_msg(struct usb_device *dev, unsigned long pipe,
  1071. void *buffer, int length,
  1072. struct devrequest *setup)
  1073. {
  1074. struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
  1075. if (usb_pipetype(pipe) != PIPE_CONTROL) {
  1076. debug("non-control pipe (type=%lu)", usb_pipetype(pipe));
  1077. return -1;
  1078. }
  1079. if (usb_pipedevice(pipe) == ctrl->rootdev) {
  1080. if (!ctrl->rootdev)
  1081. dev->speed = USB_SPEED_HIGH;
  1082. return ehci_submit_root(dev, pipe, buffer, length, setup);
  1083. }
  1084. return ehci_submit_async(dev, pipe, buffer, length, setup);
  1085. }
  1086. struct int_queue {
  1087. int elementsize;
  1088. unsigned long pipe;
  1089. struct QH *first;
  1090. struct QH *current;
  1091. struct QH *last;
  1092. struct qTD *tds;
  1093. };
  1094. #define NEXT_QH(qh) (struct QH *)((unsigned long)hc32_to_cpu((qh)->qh_link) & ~0x1f)
  1095. static int
  1096. enable_periodic(struct ehci_ctrl *ctrl)
  1097. {
  1098. uint32_t cmd;
  1099. struct ehci_hcor *hcor = ctrl->hcor;
  1100. int ret;
  1101. cmd = ehci_readl(&hcor->or_usbcmd);
  1102. cmd |= CMD_PSE;
  1103. ehci_writel(&hcor->or_usbcmd, cmd);
  1104. ret = handshake((uint32_t *)&hcor->or_usbsts,
  1105. STS_PSS, STS_PSS, 100 * 1000);
  1106. if (ret < 0) {
  1107. printf("EHCI failed: timeout when enabling periodic list\n");
  1108. return -ETIMEDOUT;
  1109. }
  1110. udelay(1000);
  1111. return 0;
  1112. }
  1113. static int
  1114. disable_periodic(struct ehci_ctrl *ctrl)
  1115. {
  1116. uint32_t cmd;
  1117. struct ehci_hcor *hcor = ctrl->hcor;
  1118. int ret;
  1119. cmd = ehci_readl(&hcor->or_usbcmd);
  1120. cmd &= ~CMD_PSE;
  1121. ehci_writel(&hcor->or_usbcmd, cmd);
  1122. ret = handshake((uint32_t *)&hcor->or_usbsts,
  1123. STS_PSS, 0, 100 * 1000);
  1124. if (ret < 0) {
  1125. printf("EHCI failed: timeout when disabling periodic list\n");
  1126. return -ETIMEDOUT;
  1127. }
  1128. return 0;
  1129. }
  1130. static struct int_queue *_ehci_create_int_queue(struct usb_device *dev,
  1131. unsigned long pipe, int queuesize, int elementsize,
  1132. void *buffer, int interval)
  1133. {
  1134. struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
  1135. struct int_queue *result = NULL;
  1136. uint32_t i, toggle;
  1137. /*
  1138. * Interrupt transfers requiring several transactions are not supported
  1139. * because bInterval is ignored.
  1140. *
  1141. * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2
  1142. * <= PKT_ALIGN if several qTDs are required, while the USB
  1143. * specification does not constrain this for interrupt transfers. That
  1144. * means that ehci_submit_async() would support interrupt transfers
  1145. * requiring several transactions only as long as the transfer size does
  1146. * not require more than a single qTD.
  1147. */
  1148. if (elementsize > usb_maxpacket(dev, pipe)) {
  1149. printf("%s: xfers requiring several transactions are not supported.\n",
  1150. __func__);
  1151. return NULL;
  1152. }
  1153. debug("Enter create_int_queue\n");
  1154. if (usb_pipetype(pipe) != PIPE_INTERRUPT) {
  1155. debug("non-interrupt pipe (type=%lu)", usb_pipetype(pipe));
  1156. return NULL;
  1157. }
  1158. /* limit to 4 full pages worth of data -
  1159. * we can safely fit them in a single TD,
  1160. * no matter the alignment
  1161. */
  1162. if (elementsize >= 16384) {
  1163. debug("too large elements for interrupt transfers\n");
  1164. return NULL;
  1165. }
  1166. result = malloc(sizeof(*result));
  1167. if (!result) {
  1168. debug("ehci intr queue: out of memory\n");
  1169. goto fail1;
  1170. }
  1171. result->elementsize = elementsize;
  1172. result->pipe = pipe;
  1173. result->first = memalign(USB_DMA_MINALIGN,
  1174. sizeof(struct QH) * queuesize);
  1175. if (!result->first) {
  1176. debug("ehci intr queue: out of memory\n");
  1177. goto fail2;
  1178. }
  1179. result->current = result->first;
  1180. result->last = result->first + queuesize - 1;
  1181. result->tds = memalign(USB_DMA_MINALIGN,
  1182. sizeof(struct qTD) * queuesize);
  1183. if (!result->tds) {
  1184. debug("ehci intr queue: out of memory\n");
  1185. goto fail3;
  1186. }
  1187. memset(result->first, 0, sizeof(struct QH) * queuesize);
  1188. memset(result->tds, 0, sizeof(struct qTD) * queuesize);
  1189. toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
  1190. for (i = 0; i < queuesize; i++) {
  1191. struct QH *qh = result->first + i;
  1192. struct qTD *td = result->tds + i;
  1193. void **buf = &qh->buffer;
  1194. qh->qh_link = cpu_to_hc32((unsigned long)(qh+1) | QH_LINK_TYPE_QH);
  1195. if (i == queuesize - 1)
  1196. qh->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
  1197. qh->qh_overlay.qt_next = cpu_to_hc32((unsigned long)td);
  1198. qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  1199. qh->qh_endpt1 =
  1200. cpu_to_hc32((0 << 28) | /* No NAK reload (ehci 4.9) */
  1201. (usb_maxpacket(dev, pipe) << 16) | /* MPS */
  1202. (1 << 14) |
  1203. QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) |
  1204. (usb_pipeendpoint(pipe) << 8) | /* Endpoint Number */
  1205. (usb_pipedevice(pipe) << 0));
  1206. qh->qh_endpt2 = cpu_to_hc32((1 << 30) | /* 1 Tx per mframe */
  1207. (1 << 0)); /* S-mask: microframe 0 */
  1208. if (dev->speed == USB_SPEED_LOW ||
  1209. dev->speed == USB_SPEED_FULL) {
  1210. /* C-mask: microframes 2-4 */
  1211. qh->qh_endpt2 |= cpu_to_hc32((0x1c << 8));
  1212. }
  1213. ehci_update_endpt2_dev_n_port(dev, qh);
  1214. td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  1215. td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  1216. debug("communication direction is '%s'\n",
  1217. usb_pipein(pipe) ? "in" : "out");
  1218. td->qt_token = cpu_to_hc32(
  1219. QT_TOKEN_DT(toggle) |
  1220. (elementsize << 16) |
  1221. ((usb_pipein(pipe) ? 1 : 0) << 8) | /* IN/OUT token */
  1222. 0x80); /* active */
  1223. td->qt_buffer[0] =
  1224. cpu_to_hc32((unsigned long)buffer + i * elementsize);
  1225. td->qt_buffer[1] =
  1226. cpu_to_hc32((td->qt_buffer[0] + 0x1000) & ~0xfff);
  1227. td->qt_buffer[2] =
  1228. cpu_to_hc32((td->qt_buffer[0] + 0x2000) & ~0xfff);
  1229. td->qt_buffer[3] =
  1230. cpu_to_hc32((td->qt_buffer[0] + 0x3000) & ~0xfff);
  1231. td->qt_buffer[4] =
  1232. cpu_to_hc32((td->qt_buffer[0] + 0x4000) & ~0xfff);
  1233. *buf = buffer + i * elementsize;
  1234. toggle ^= 1;
  1235. }
  1236. flush_dcache_range((unsigned long)buffer,
  1237. ALIGN_END_ADDR(char, buffer,
  1238. queuesize * elementsize));
  1239. flush_dcache_range((unsigned long)result->first,
  1240. ALIGN_END_ADDR(struct QH, result->first,
  1241. queuesize));
  1242. flush_dcache_range((unsigned long)result->tds,
  1243. ALIGN_END_ADDR(struct qTD, result->tds,
  1244. queuesize));
  1245. if (ctrl->periodic_schedules > 0) {
  1246. if (disable_periodic(ctrl) < 0) {
  1247. debug("FATAL: periodic should never fail, but did");
  1248. goto fail3;
  1249. }
  1250. }
  1251. /* hook up to periodic list */
  1252. struct QH *list = &ctrl->periodic_queue;
  1253. result->last->qh_link = list->qh_link;
  1254. list->qh_link = cpu_to_hc32((unsigned long)result->first | QH_LINK_TYPE_QH);
  1255. flush_dcache_range((unsigned long)result->last,
  1256. ALIGN_END_ADDR(struct QH, result->last, 1));
  1257. flush_dcache_range((unsigned long)list,
  1258. ALIGN_END_ADDR(struct QH, list, 1));
  1259. if (enable_periodic(ctrl) < 0) {
  1260. debug("FATAL: periodic should never fail, but did");
  1261. goto fail3;
  1262. }
  1263. ctrl->periodic_schedules++;
  1264. debug("Exit create_int_queue\n");
  1265. return result;
  1266. fail3:
  1267. free(result->tds);
  1268. fail2:
  1269. free(result->first);
  1270. free(result);
  1271. fail1:
  1272. return NULL;
  1273. }
  1274. static void *_ehci_poll_int_queue(struct usb_device *dev,
  1275. struct int_queue *queue)
  1276. {
  1277. struct QH *cur = queue->current;
  1278. struct qTD *cur_td;
  1279. uint32_t token, toggle;
  1280. unsigned long pipe = queue->pipe;
  1281. /* depleted queue */
  1282. if (cur == NULL) {
  1283. debug("Exit poll_int_queue with completed queue\n");
  1284. return NULL;
  1285. }
  1286. /* still active */
  1287. cur_td = &queue->tds[queue->current - queue->first];
  1288. invalidate_dcache_range((unsigned long)cur_td,
  1289. ALIGN_END_ADDR(struct qTD, cur_td, 1));
  1290. token = hc32_to_cpu(cur_td->qt_token);
  1291. if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE) {
  1292. debug("Exit poll_int_queue with no completed intr transfer. token is %x\n", token);
  1293. return NULL;
  1294. }
  1295. toggle = QT_TOKEN_GET_DT(token);
  1296. usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), toggle);
  1297. if (!(cur->qh_link & QH_LINK_TERMINATE))
  1298. queue->current++;
  1299. else
  1300. queue->current = NULL;
  1301. invalidate_dcache_range((unsigned long)cur->buffer,
  1302. ALIGN_END_ADDR(char, cur->buffer,
  1303. queue->elementsize));
  1304. debug("Exit poll_int_queue with completed intr transfer. token is %x at %p (first at %p)\n",
  1305. token, cur, queue->first);
  1306. return cur->buffer;
  1307. }
  1308. /* Do not free buffers associated with QHs, they're owned by someone else */
  1309. static int _ehci_destroy_int_queue(struct usb_device *dev,
  1310. struct int_queue *queue)
  1311. {
  1312. struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
  1313. int result = -1;
  1314. unsigned long timeout;
  1315. if (disable_periodic(ctrl) < 0) {
  1316. debug("FATAL: periodic should never fail, but did");
  1317. goto out;
  1318. }
  1319. ctrl->periodic_schedules--;
  1320. struct QH *cur = &ctrl->periodic_queue;
  1321. timeout = get_timer(0) + 500; /* abort after 500ms */
  1322. while (!(cur->qh_link & cpu_to_hc32(QH_LINK_TERMINATE))) {
  1323. debug("considering %p, with qh_link %x\n", cur, cur->qh_link);
  1324. if (NEXT_QH(cur) == queue->first) {
  1325. debug("found candidate. removing from chain\n");
  1326. cur->qh_link = queue->last->qh_link;
  1327. flush_dcache_range((unsigned long)cur,
  1328. ALIGN_END_ADDR(struct QH, cur, 1));
  1329. result = 0;
  1330. break;
  1331. }
  1332. cur = NEXT_QH(cur);
  1333. if (get_timer(0) > timeout) {
  1334. printf("Timeout destroying interrupt endpoint queue\n");
  1335. result = -1;
  1336. goto out;
  1337. }
  1338. }
  1339. if (ctrl->periodic_schedules > 0) {
  1340. result = enable_periodic(ctrl);
  1341. if (result < 0)
  1342. debug("FATAL: periodic should never fail, but did");
  1343. }
  1344. out:
  1345. free(queue->tds);
  1346. free(queue->first);
  1347. free(queue);
  1348. return result;
  1349. }
  1350. static int _ehci_submit_int_msg(struct usb_device *dev, unsigned long pipe,
  1351. void *buffer, int length, int interval,
  1352. bool nonblock)
  1353. {
  1354. void *backbuffer;
  1355. struct int_queue *queue;
  1356. unsigned long timeout;
  1357. int result = 0, ret;
  1358. debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
  1359. dev, pipe, buffer, length, interval);
  1360. queue = _ehci_create_int_queue(dev, pipe, 1, length, buffer, interval);
  1361. if (!queue)
  1362. return -1;
  1363. timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
  1364. while ((backbuffer = _ehci_poll_int_queue(dev, queue)) == NULL)
  1365. if (get_timer(0) > timeout) {
  1366. printf("Timeout poll on interrupt endpoint\n");
  1367. result = -ETIMEDOUT;
  1368. break;
  1369. }
  1370. if (backbuffer != buffer) {
  1371. debug("got wrong buffer back (%p instead of %p)\n",
  1372. backbuffer, buffer);
  1373. return -EINVAL;
  1374. }
  1375. ret = _ehci_destroy_int_queue(dev, queue);
  1376. if (ret < 0)
  1377. return ret;
  1378. /* everything worked out fine */
  1379. return result;
  1380. }
  1381. static int _ehci_lock_async(struct ehci_ctrl *ctrl, int lock)
  1382. {
  1383. ctrl->async_locked = lock;
  1384. if (lock)
  1385. return 0;
  1386. return ehci_disable_async(ctrl);
  1387. }
  1388. #if !CONFIG_IS_ENABLED(DM_USB)
  1389. int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
  1390. void *buffer, int length)
  1391. {
  1392. return _ehci_submit_bulk_msg(dev, pipe, buffer, length);
  1393. }
  1394. int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1395. int length, struct devrequest *setup)
  1396. {
  1397. return _ehci_submit_control_msg(dev, pipe, buffer, length, setup);
  1398. }
  1399. int submit_int_msg(struct usb_device *dev, unsigned long pipe,
  1400. void *buffer, int length, int interval, bool nonblock)
  1401. {
  1402. return _ehci_submit_int_msg(dev, pipe, buffer, length, interval,
  1403. nonblock);
  1404. }
  1405. struct int_queue *create_int_queue(struct usb_device *dev,
  1406. unsigned long pipe, int queuesize, int elementsize,
  1407. void *buffer, int interval)
  1408. {
  1409. return _ehci_create_int_queue(dev, pipe, queuesize, elementsize,
  1410. buffer, interval);
  1411. }
  1412. void *poll_int_queue(struct usb_device *dev, struct int_queue *queue)
  1413. {
  1414. return _ehci_poll_int_queue(dev, queue);
  1415. }
  1416. int destroy_int_queue(struct usb_device *dev, struct int_queue *queue)
  1417. {
  1418. return _ehci_destroy_int_queue(dev, queue);
  1419. }
  1420. int usb_lock_async(struct usb_device *dev, int lock)
  1421. {
  1422. struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
  1423. return _ehci_lock_async(ctrl, lock);
  1424. }
  1425. #endif
  1426. #if CONFIG_IS_ENABLED(DM_USB)
  1427. static int ehci_submit_control_msg(struct udevice *dev, struct usb_device *udev,
  1428. unsigned long pipe, void *buffer, int length,
  1429. struct devrequest *setup)
  1430. {
  1431. debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
  1432. dev->name, udev, udev->dev->name, udev->portnr);
  1433. return _ehci_submit_control_msg(udev, pipe, buffer, length, setup);
  1434. }
  1435. static int ehci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
  1436. unsigned long pipe, void *buffer, int length)
  1437. {
  1438. debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
  1439. return _ehci_submit_bulk_msg(udev, pipe, buffer, length);
  1440. }
  1441. static int ehci_submit_int_msg(struct udevice *dev, struct usb_device *udev,
  1442. unsigned long pipe, void *buffer, int length,
  1443. int interval, bool nonblock)
  1444. {
  1445. debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
  1446. return _ehci_submit_int_msg(udev, pipe, buffer, length, interval,
  1447. nonblock);
  1448. }
  1449. static struct int_queue *ehci_create_int_queue(struct udevice *dev,
  1450. struct usb_device *udev, unsigned long pipe, int queuesize,
  1451. int elementsize, void *buffer, int interval)
  1452. {
  1453. debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
  1454. return _ehci_create_int_queue(udev, pipe, queuesize, elementsize,
  1455. buffer, interval);
  1456. }
  1457. static void *ehci_poll_int_queue(struct udevice *dev, struct usb_device *udev,
  1458. struct int_queue *queue)
  1459. {
  1460. debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
  1461. return _ehci_poll_int_queue(udev, queue);
  1462. }
  1463. static int ehci_destroy_int_queue(struct udevice *dev, struct usb_device *udev,
  1464. struct int_queue *queue)
  1465. {
  1466. debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
  1467. return _ehci_destroy_int_queue(udev, queue);
  1468. }
  1469. static int ehci_get_max_xfer_size(struct udevice *dev, size_t *size)
  1470. {
  1471. /*
  1472. * EHCD can handle any transfer length as long as there is enough
  1473. * free heap space left, hence set the theoretical max number here.
  1474. */
  1475. *size = SIZE_MAX;
  1476. return 0;
  1477. }
  1478. static int ehci_lock_async(struct udevice *dev, int lock)
  1479. {
  1480. struct ehci_ctrl *ctrl = dev_get_priv(dev);
  1481. return _ehci_lock_async(ctrl, lock);
  1482. }
  1483. int ehci_register(struct udevice *dev, struct ehci_hccr *hccr,
  1484. struct ehci_hcor *hcor, const struct ehci_ops *ops,
  1485. uint tweaks, enum usb_init_type init)
  1486. {
  1487. struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
  1488. struct ehci_ctrl *ctrl = dev_get_priv(dev);
  1489. int ret = -1;
  1490. debug("%s: dev='%s', ctrl=%p, hccr=%p, hcor=%p, init=%d\n", __func__,
  1491. dev->name, ctrl, hccr, hcor, init);
  1492. if (!ctrl || !hccr || !hcor)
  1493. goto err;
  1494. priv->desc_before_addr = true;
  1495. ehci_setup_ops(ctrl, ops);
  1496. ctrl->hccr = hccr;
  1497. ctrl->hcor = hcor;
  1498. ctrl->priv = ctrl;
  1499. ctrl->init = init;
  1500. if (ctrl->init == USB_INIT_DEVICE)
  1501. goto done;
  1502. ret = ehci_reset(ctrl);
  1503. if (ret)
  1504. goto err;
  1505. if (ctrl->ops.init_after_reset) {
  1506. ret = ctrl->ops.init_after_reset(ctrl);
  1507. if (ret)
  1508. goto err;
  1509. }
  1510. ret = ehci_common_init(ctrl, tweaks);
  1511. if (ret)
  1512. goto err;
  1513. done:
  1514. return 0;
  1515. err:
  1516. free(ctrl);
  1517. debug("%s: failed, ret=%d\n", __func__, ret);
  1518. return ret;
  1519. }
  1520. int ehci_deregister(struct udevice *dev)
  1521. {
  1522. struct ehci_ctrl *ctrl = dev_get_priv(dev);
  1523. if (ctrl->init == USB_INIT_DEVICE)
  1524. return 0;
  1525. ehci_shutdown(ctrl);
  1526. return 0;
  1527. }
  1528. struct dm_usb_ops ehci_usb_ops = {
  1529. .control = ehci_submit_control_msg,
  1530. .bulk = ehci_submit_bulk_msg,
  1531. .interrupt = ehci_submit_int_msg,
  1532. .create_int_queue = ehci_create_int_queue,
  1533. .poll_int_queue = ehci_poll_int_queue,
  1534. .destroy_int_queue = ehci_destroy_int_queue,
  1535. .get_max_xfer_size = ehci_get_max_xfer_size,
  1536. .lock_async = ehci_lock_async,
  1537. };
  1538. #endif
  1539. #ifdef CONFIG_PHY
  1540. int ehci_setup_phy(struct udevice *dev, struct phy *phy, int index)
  1541. {
  1542. int ret;
  1543. if (!phy)
  1544. return 0;
  1545. ret = generic_phy_get_by_index(dev, index, phy);
  1546. if (ret) {
  1547. if (ret != -ENOENT) {
  1548. dev_err(dev, "failed to get usb phy\n");
  1549. return ret;
  1550. }
  1551. } else {
  1552. ret = generic_phy_init(phy);
  1553. if (ret) {
  1554. dev_err(dev, "failed to init usb phy\n");
  1555. return ret;
  1556. }
  1557. ret = generic_phy_power_on(phy);
  1558. if (ret) {
  1559. dev_err(dev, "failed to power on usb phy\n");
  1560. return generic_phy_exit(phy);
  1561. }
  1562. }
  1563. return 0;
  1564. }
  1565. int ehci_shutdown_phy(struct udevice *dev, struct phy *phy)
  1566. {
  1567. int ret = 0;
  1568. if (!phy)
  1569. return 0;
  1570. if (generic_phy_valid(phy)) {
  1571. ret = generic_phy_power_off(phy);
  1572. if (ret) {
  1573. dev_err(dev, "failed to power off usb phy\n");
  1574. return ret;
  1575. }
  1576. ret = generic_phy_exit(phy);
  1577. if (ret) {
  1578. dev_err(dev, "failed to power off usb phy\n");
  1579. return ret;
  1580. }
  1581. }
  1582. return 0;
  1583. }
  1584. #else
  1585. int ehci_setup_phy(struct udevice *dev, struct phy *phy, int index)
  1586. {
  1587. return 0;
  1588. }
  1589. int ehci_shutdown_phy(struct udevice *dev, struct phy *phy)
  1590. {
  1591. return 0;
  1592. }
  1593. #endif