ehci-fsl.c 7.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009, 2011, 2016 Freescale Semiconductor, Inc.
  4. *
  5. * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
  6. *
  7. * Author: Tor Krill tor@excito.com
  8. */
  9. #include <common.h>
  10. #include <env.h>
  11. #include <pci.h>
  12. #include <usb.h>
  13. #include <asm/io.h>
  14. #include <usb/ehci-ci.h>
  15. #include <hwconfig.h>
  16. #include <fsl_usb.h>
  17. #include <fdt_support.h>
  18. #include <dm.h>
  19. #include "ehci.h"
  20. DECLARE_GLOBAL_DATA_PTR;
  21. #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
  22. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  23. #endif
  24. #if CONFIG_IS_ENABLED(DM_USB)
  25. struct ehci_fsl_priv {
  26. struct ehci_ctrl ehci;
  27. fdt_addr_t hcd_base;
  28. char *phy_type;
  29. };
  30. #endif
  31. static void set_txfifothresh(struct usb_ehci *, u32);
  32. #if CONFIG_IS_ENABLED(DM_USB)
  33. static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci,
  34. struct ehci_hccr *hccr, struct ehci_hcor *hcor);
  35. #else
  36. static int ehci_fsl_init(int index, struct usb_ehci *ehci,
  37. struct ehci_hccr *hccr, struct ehci_hcor *hcor);
  38. #endif
  39. /* Check USB PHY clock valid */
  40. static int usb_phy_clk_valid(struct usb_ehci *ehci)
  41. {
  42. if (!((in_be32(&ehci->control) & PHY_CLK_VALID) ||
  43. in_be32(&ehci->prictrl))) {
  44. printf("USB PHY clock invalid!\n");
  45. return 0;
  46. } else {
  47. return 1;
  48. }
  49. }
  50. #if CONFIG_IS_ENABLED(DM_USB)
  51. static int ehci_fsl_ofdata_to_platdata(struct udevice *dev)
  52. {
  53. struct ehci_fsl_priv *priv = dev_get_priv(dev);
  54. const void *prop;
  55. prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy_type",
  56. NULL);
  57. if (prop) {
  58. priv->phy_type = (char *)prop;
  59. debug("phy_type %s\n", priv->phy_type);
  60. }
  61. return 0;
  62. }
  63. static int ehci_fsl_init_after_reset(struct ehci_ctrl *ctrl)
  64. {
  65. struct usb_ehci *ehci = NULL;
  66. struct ehci_fsl_priv *priv = container_of(ctrl, struct ehci_fsl_priv,
  67. ehci);
  68. #ifdef CONFIG_PPC
  69. ehci = (struct usb_ehci *)lower_32_bits(priv->hcd_base);
  70. #else
  71. ehci = (struct usb_ehci *)priv->hcd_base;
  72. #endif
  73. if (ehci_fsl_init(priv, ehci, priv->ehci.hccr, priv->ehci.hcor) < 0)
  74. return -ENXIO;
  75. return 0;
  76. }
  77. static const struct ehci_ops fsl_ehci_ops = {
  78. .init_after_reset = ehci_fsl_init_after_reset,
  79. };
  80. static int ehci_fsl_probe(struct udevice *dev)
  81. {
  82. struct ehci_fsl_priv *priv = dev_get_priv(dev);
  83. struct usb_ehci *ehci = NULL;
  84. struct ehci_hccr *hccr;
  85. struct ehci_hcor *hcor;
  86. struct ehci_ctrl *ehci_ctrl = &priv->ehci;
  87. /*
  88. * Get the base address for EHCI controller from the device node
  89. */
  90. priv->hcd_base = devfdt_get_addr(dev);
  91. if (priv->hcd_base == FDT_ADDR_T_NONE) {
  92. debug("Can't get the EHCI register base address\n");
  93. return -ENXIO;
  94. }
  95. #ifdef CONFIG_PPC
  96. ehci = (struct usb_ehci *)lower_32_bits(priv->hcd_base);
  97. #else
  98. ehci = (struct usb_ehci *)priv->hcd_base;
  99. #endif
  100. hccr = (struct ehci_hccr *)(&ehci->caplength);
  101. hcor = (struct ehci_hcor *)
  102. ((void *)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
  103. ehci_ctrl->has_fsl_erratum_a005275 = has_erratum_a005275();
  104. if (ehci_fsl_init(priv, ehci, hccr, hcor) < 0)
  105. return -ENXIO;
  106. debug("ehci-fsl: init hccr %p and hcor %p hc_length %d\n",
  107. (void *)hccr, (void *)hcor,
  108. HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
  109. return ehci_register(dev, hccr, hcor, &fsl_ehci_ops, 0, USB_INIT_HOST);
  110. }
  111. static const struct udevice_id ehci_usb_ids[] = {
  112. { .compatible = "fsl-usb2-mph", },
  113. { .compatible = "fsl-usb2-dr", },
  114. { }
  115. };
  116. U_BOOT_DRIVER(ehci_fsl) = {
  117. .name = "ehci_fsl",
  118. .id = UCLASS_USB,
  119. .of_match = ehci_usb_ids,
  120. .ofdata_to_platdata = ehci_fsl_ofdata_to_platdata,
  121. .probe = ehci_fsl_probe,
  122. .remove = ehci_deregister,
  123. .ops = &ehci_usb_ops,
  124. .platdata_auto_alloc_size = sizeof(struct usb_platdata),
  125. .priv_auto_alloc_size = sizeof(struct ehci_fsl_priv),
  126. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  127. };
  128. #else
  129. /*
  130. * Create the appropriate control structures to manage
  131. * a new EHCI host controller.
  132. *
  133. * Excerpts from linux ehci fsl driver.
  134. */
  135. int ehci_hcd_init(int index, enum usb_init_type init,
  136. struct ehci_hccr **hccr, struct ehci_hcor **hcor)
  137. {
  138. struct ehci_ctrl *ehci_ctrl = container_of(hccr,
  139. struct ehci_ctrl, hccr);
  140. struct usb_ehci *ehci = NULL;
  141. switch (index) {
  142. case 0:
  143. ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
  144. break;
  145. case 1:
  146. ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB2_ADDR;
  147. break;
  148. default:
  149. printf("ERROR: wrong controller index!!\n");
  150. return -EINVAL;
  151. };
  152. *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
  153. *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
  154. HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
  155. ehci_ctrl->has_fsl_erratum_a005275 = has_erratum_a005275();
  156. return ehci_fsl_init(index, ehci, *hccr, *hcor);
  157. }
  158. /*
  159. * Destroy the appropriate control structures corresponding
  160. * the the EHCI host controller.
  161. */
  162. int ehci_hcd_stop(int index)
  163. {
  164. return 0;
  165. }
  166. #endif
  167. #if CONFIG_IS_ENABLED(DM_USB)
  168. static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci,
  169. struct ehci_hccr *hccr, struct ehci_hcor *hcor)
  170. #else
  171. static int ehci_fsl_init(int index, struct usb_ehci *ehci,
  172. struct ehci_hccr *hccr, struct ehci_hcor *hcor)
  173. #endif
  174. {
  175. const char *phy_type = NULL;
  176. #if !CONFIG_IS_ENABLED(DM_USB)
  177. size_t len;
  178. char current_usb_controller[5];
  179. #endif
  180. #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  181. char usb_phy[5];
  182. usb_phy[0] = '\0';
  183. #endif
  184. if (has_erratum_a007075()) {
  185. /*
  186. * A 5ms delay is needed after applying soft-reset to the
  187. * controller to let external ULPI phy come out of reset.
  188. * This delay needs to be added before re-initializing
  189. * the controller after soft-resetting completes
  190. */
  191. mdelay(5);
  192. }
  193. /* Set to Host mode */
  194. setbits_le32(&ehci->usbmode, CM_HOST);
  195. out_be32(&ehci->snoop1, SNOOP_SIZE_2GB);
  196. out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);
  197. /* Init phy */
  198. #if CONFIG_IS_ENABLED(DM_USB)
  199. if (priv->phy_type)
  200. phy_type = priv->phy_type;
  201. #else
  202. memset(current_usb_controller, '\0', 5);
  203. snprintf(current_usb_controller, sizeof(current_usb_controller),
  204. "usb%d", index+1);
  205. if (hwconfig_sub(current_usb_controller, "phy_type"))
  206. phy_type = hwconfig_subarg(current_usb_controller,
  207. "phy_type", &len);
  208. #endif
  209. else
  210. phy_type = env_get("usb_phy_type");
  211. if (!phy_type) {
  212. #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  213. /* if none specified assume internal UTMI */
  214. strcpy(usb_phy, "utmi");
  215. phy_type = usb_phy;
  216. #else
  217. printf("WARNING: USB phy type not defined !!\n");
  218. return -1;
  219. #endif
  220. }
  221. if (!strncmp(phy_type, "utmi", 4)) {
  222. #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
  223. clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
  224. PHY_CLK_SEL_UTMI);
  225. clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
  226. UTMI_PHY_EN);
  227. udelay(1000); /* delay required for PHY Clk to appear */
  228. #endif
  229. out_le32(&(hcor)->or_portsc[0], PORT_PTS_UTMI);
  230. clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
  231. USB_EN);
  232. } else {
  233. clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
  234. PHY_CLK_SEL_ULPI);
  235. clrsetbits_be32(&ehci->control, UTMI_PHY_EN |
  236. CONTROL_REGISTER_W1C_MASK, USB_EN);
  237. udelay(1000); /* delay required for PHY Clk to appear */
  238. if (!usb_phy_clk_valid(ehci))
  239. return -EINVAL;
  240. out_le32(&(hcor)->or_portsc[0], PORT_PTS_ULPI);
  241. }
  242. out_be32(&ehci->prictrl, 0x0000000c);
  243. out_be32(&ehci->age_cnt_limit, 0x00000040);
  244. out_be32(&ehci->sictrl, 0x00000001);
  245. in_le32(&ehci->usbmode);
  246. if (has_erratum_a007798())
  247. set_txfifothresh(ehci, TXFIFOTHRESH);
  248. if (has_erratum_a004477()) {
  249. /*
  250. * When reset is issued while any ULPI transaction is ongoing
  251. * then it may result to corruption of ULPI Function Control
  252. * Register which eventually causes phy clock to enter low
  253. * power mode which stops the clock. Thus delay is required
  254. * before reset to let ongoing ULPI transaction complete.
  255. */
  256. udelay(1);
  257. }
  258. return 0;
  259. }
  260. /*
  261. * Setting the value of TXFIFO_THRESH field in TXFILLTUNING register
  262. * to counter DDR latencies in writing data into Tx buffer.
  263. * This prevents Tx buffer from getting underrun
  264. */
  265. static void set_txfifothresh(struct usb_ehci *ehci, u32 txfifo_thresh)
  266. {
  267. u32 cmd;
  268. cmd = ehci_readl(&ehci->txfilltuning);
  269. cmd &= ~TXFIFO_THRESH_MASK;
  270. cmd |= TXFIFO_THRESH(txfifo_thresh);
  271. ehci_writel(&ehci->txfilltuning, cmd);
  272. }