ehci-exynos.c 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * SAMSUNG EXYNOS USB HOST EHCI Controller
  4. *
  5. * Copyright (C) 2012 Samsung Electronics Co.Ltd
  6. * Vivek Gautam <gautam.vivek@samsung.com>
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <fdtdec.h>
  11. #include <linux/libfdt.h>
  12. #include <malloc.h>
  13. #include <usb.h>
  14. #include <asm/arch/cpu.h>
  15. #include <asm/arch/ehci.h>
  16. #include <asm/arch/system.h>
  17. #include <asm/arch/power.h>
  18. #include <asm/gpio.h>
  19. #include <linux/errno.h>
  20. #include <linux/compat.h>
  21. #include "ehci.h"
  22. /* Declare global data pointer */
  23. DECLARE_GLOBAL_DATA_PTR;
  24. struct exynos_ehci_platdata {
  25. struct usb_platdata usb_plat;
  26. fdt_addr_t hcd_base;
  27. fdt_addr_t phy_base;
  28. struct gpio_desc vbus_gpio;
  29. };
  30. /**
  31. * Contains pointers to register base addresses
  32. * for the usb controller.
  33. */
  34. struct exynos_ehci {
  35. struct ehci_ctrl ctrl;
  36. struct exynos_usb_phy *usb;
  37. struct ehci_hccr *hcd;
  38. };
  39. static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
  40. {
  41. struct exynos_ehci_platdata *plat = dev_get_platdata(dev);
  42. const void *blob = gd->fdt_blob;
  43. unsigned int node;
  44. int depth;
  45. /*
  46. * Get the base address for XHCI controller from the device node
  47. */
  48. plat->hcd_base = devfdt_get_addr(dev);
  49. if (plat->hcd_base == FDT_ADDR_T_NONE) {
  50. debug("Can't get the XHCI register base address\n");
  51. return -ENXIO;
  52. }
  53. depth = 0;
  54. node = fdtdec_next_compatible_subnode(blob, dev_of_offset(dev),
  55. COMPAT_SAMSUNG_EXYNOS_USB_PHY, &depth);
  56. if (node <= 0) {
  57. debug("XHCI: Can't get device node for usb3-phy controller\n");
  58. return -ENODEV;
  59. }
  60. /*
  61. * Get the base address for usbphy from the device node
  62. */
  63. plat->phy_base = fdtdec_get_addr(blob, node, "reg");
  64. if (plat->phy_base == FDT_ADDR_T_NONE) {
  65. debug("Can't get the usbphy register address\n");
  66. return -ENXIO;
  67. }
  68. /* Vbus gpio */
  69. gpio_request_by_name(dev, "samsung,vbus-gpio", 0,
  70. &plat->vbus_gpio, GPIOD_IS_OUT);
  71. return 0;
  72. }
  73. static void exynos5_setup_usb_phy(struct exynos_usb_phy *usb)
  74. {
  75. u32 hsic_ctrl;
  76. clrbits_le32(&usb->usbphyctrl0,
  77. HOST_CTRL0_FSEL_MASK |
  78. HOST_CTRL0_COMMONON_N |
  79. /* HOST Phy setting */
  80. HOST_CTRL0_PHYSWRST |
  81. HOST_CTRL0_PHYSWRSTALL |
  82. HOST_CTRL0_SIDDQ |
  83. HOST_CTRL0_FORCESUSPEND |
  84. HOST_CTRL0_FORCESLEEP);
  85. setbits_le32(&usb->usbphyctrl0,
  86. /* Setting up the ref freq */
  87. (CLK_24MHZ << 16) |
  88. /* HOST Phy setting */
  89. HOST_CTRL0_LINKSWRST |
  90. HOST_CTRL0_UTMISWRST);
  91. udelay(10);
  92. clrbits_le32(&usb->usbphyctrl0,
  93. HOST_CTRL0_LINKSWRST |
  94. HOST_CTRL0_UTMISWRST);
  95. /* HSIC Phy Setting */
  96. hsic_ctrl = (HSIC_CTRL_FORCESUSPEND |
  97. HSIC_CTRL_FORCESLEEP |
  98. HSIC_CTRL_SIDDQ);
  99. clrbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
  100. clrbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
  101. hsic_ctrl = (((HSIC_CTRL_REFCLKDIV_12 & HSIC_CTRL_REFCLKDIV_MASK)
  102. << HSIC_CTRL_REFCLKDIV_SHIFT)
  103. | ((HSIC_CTRL_REFCLKSEL & HSIC_CTRL_REFCLKSEL_MASK)
  104. << HSIC_CTRL_REFCLKSEL_SHIFT)
  105. | HSIC_CTRL_UTMISWRST);
  106. setbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
  107. setbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
  108. udelay(10);
  109. clrbits_le32(&usb->hsicphyctrl1, HSIC_CTRL_PHYSWRST |
  110. HSIC_CTRL_UTMISWRST);
  111. clrbits_le32(&usb->hsicphyctrl2, HSIC_CTRL_PHYSWRST |
  112. HSIC_CTRL_UTMISWRST);
  113. udelay(20);
  114. /* EHCI Ctrl setting */
  115. setbits_le32(&usb->ehcictrl,
  116. EHCICTRL_ENAINCRXALIGN |
  117. EHCICTRL_ENAINCR4 |
  118. EHCICTRL_ENAINCR8 |
  119. EHCICTRL_ENAINCR16);
  120. }
  121. static void exynos4412_setup_usb_phy(struct exynos4412_usb_phy *usb)
  122. {
  123. writel(CLK_24MHZ, &usb->usbphyclk);
  124. clrbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 |
  125. PHYPWR_NORMAL_MASK_HSIC1 | PHYPWR_NORMAL_MASK_PHY1 |
  126. PHYPWR_NORMAL_MASK_PHY0));
  127. setbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST));
  128. udelay(10);
  129. clrbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST));
  130. }
  131. static void setup_usb_phy(struct exynos_usb_phy *usb)
  132. {
  133. set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
  134. set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN);
  135. if (cpu_is_exynos5())
  136. exynos5_setup_usb_phy(usb);
  137. else if (cpu_is_exynos4())
  138. if (proid_is_exynos4412())
  139. exynos4412_setup_usb_phy((struct exynos4412_usb_phy *)
  140. usb);
  141. }
  142. static void exynos5_reset_usb_phy(struct exynos_usb_phy *usb)
  143. {
  144. u32 hsic_ctrl;
  145. /* HOST_PHY reset */
  146. setbits_le32(&usb->usbphyctrl0,
  147. HOST_CTRL0_PHYSWRST |
  148. HOST_CTRL0_PHYSWRSTALL |
  149. HOST_CTRL0_SIDDQ |
  150. HOST_CTRL0_FORCESUSPEND |
  151. HOST_CTRL0_FORCESLEEP);
  152. /* HSIC Phy reset */
  153. hsic_ctrl = (HSIC_CTRL_FORCESUSPEND |
  154. HSIC_CTRL_FORCESLEEP |
  155. HSIC_CTRL_SIDDQ |
  156. HSIC_CTRL_PHYSWRST);
  157. setbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
  158. setbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
  159. }
  160. static void exynos4412_reset_usb_phy(struct exynos4412_usb_phy *usb)
  161. {
  162. setbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 |
  163. PHYPWR_NORMAL_MASK_HSIC1 | PHYPWR_NORMAL_MASK_PHY1 |
  164. PHYPWR_NORMAL_MASK_PHY0));
  165. }
  166. /* Reset the EHCI host controller. */
  167. static void reset_usb_phy(struct exynos_usb_phy *usb)
  168. {
  169. if (cpu_is_exynos5())
  170. exynos5_reset_usb_phy(usb);
  171. else if (cpu_is_exynos4())
  172. if (proid_is_exynos4412())
  173. exynos4412_reset_usb_phy((struct exynos4412_usb_phy *)
  174. usb);
  175. set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_DISABLE);
  176. }
  177. static int ehci_usb_probe(struct udevice *dev)
  178. {
  179. struct exynos_ehci_platdata *plat = dev_get_platdata(dev);
  180. struct exynos_ehci *ctx = dev_get_priv(dev);
  181. struct ehci_hcor *hcor;
  182. ctx->hcd = (struct ehci_hccr *)plat->hcd_base;
  183. ctx->usb = (struct exynos_usb_phy *)plat->phy_base;
  184. /* setup the Vbus gpio here */
  185. if (dm_gpio_is_valid(&plat->vbus_gpio))
  186. dm_gpio_set_value(&plat->vbus_gpio, 1);
  187. setup_usb_phy(ctx->usb);
  188. hcor = (struct ehci_hcor *)((uint32_t)ctx->hcd +
  189. HC_LENGTH(ehci_readl(&ctx->hcd->cr_capbase)));
  190. return ehci_register(dev, ctx->hcd, hcor, NULL, 0, USB_INIT_HOST);
  191. }
  192. static int ehci_usb_remove(struct udevice *dev)
  193. {
  194. struct exynos_ehci *ctx = dev_get_priv(dev);
  195. int ret;
  196. ret = ehci_deregister(dev);
  197. if (ret)
  198. return ret;
  199. reset_usb_phy(ctx->usb);
  200. return 0;
  201. }
  202. static const struct udevice_id ehci_usb_ids[] = {
  203. { .compatible = "samsung,exynos-ehci" },
  204. { }
  205. };
  206. U_BOOT_DRIVER(usb_ehci) = {
  207. .name = "ehci_exynos",
  208. .id = UCLASS_USB,
  209. .of_match = ehci_usb_ids,
  210. .ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
  211. .probe = ehci_usb_probe,
  212. .remove = ehci_usb_remove,
  213. .ops = &ehci_usb_ops,
  214. .priv_auto_alloc_size = sizeof(struct exynos_ehci),
  215. .platdata_auto_alloc_size = sizeof(struct exynos_ehci_platdata),
  216. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  217. };