dwc2.c 36 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
  4. * Copyright (C) 2014 Marek Vasut <marex@denx.de>
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <cpu_func.h>
  9. #include <dm.h>
  10. #include <errno.h>
  11. #include <generic-phy.h>
  12. #include <malloc.h>
  13. #include <memalign.h>
  14. #include <phys2bus.h>
  15. #include <usb.h>
  16. #include <usbroothubdes.h>
  17. #include <wait_bit.h>
  18. #include <asm/io.h>
  19. #include <dm/device_compat.h>
  20. #include <power/regulator.h>
  21. #include <reset.h>
  22. #include "dwc2.h"
  23. /* Use only HC channel 0. */
  24. #define DWC2_HC_CHANNEL 0
  25. #define DWC2_STATUS_BUF_SIZE 64
  26. #define DWC2_DATA_BUF_SIZE (CONFIG_USB_DWC2_BUFFER_SIZE * 1024)
  27. #define MAX_DEVICE 16
  28. #define MAX_ENDPOINT 16
  29. struct dwc2_priv {
  30. #if CONFIG_IS_ENABLED(DM_USB)
  31. uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
  32. uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
  33. #ifdef CONFIG_DM_REGULATOR
  34. struct udevice *vbus_supply;
  35. #endif
  36. struct phy phy;
  37. struct clk_bulk clks;
  38. #else
  39. uint8_t *aligned_buffer;
  40. uint8_t *status_buffer;
  41. #endif
  42. u8 in_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
  43. u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
  44. struct dwc2_core_regs *regs;
  45. int root_hub_devnum;
  46. bool ext_vbus;
  47. /*
  48. * The hnp/srp capability must be disabled if the platform
  49. * does't support hnp/srp. Otherwise the force mode can't work.
  50. */
  51. bool hnp_srp_disable;
  52. bool oc_disable;
  53. struct reset_ctl_bulk resets;
  54. };
  55. #if !CONFIG_IS_ENABLED(DM_USB)
  56. /* We need cacheline-aligned buffers for DMA transfers and dcache support */
  57. DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE,
  58. ARCH_DMA_MINALIGN);
  59. DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE,
  60. ARCH_DMA_MINALIGN);
  61. static struct dwc2_priv local;
  62. #endif
  63. /*
  64. * DWC2 IP interface
  65. */
  66. /*
  67. * Initializes the FSLSPClkSel field of the HCFG register
  68. * depending on the PHY type.
  69. */
  70. static void init_fslspclksel(struct dwc2_core_regs *regs)
  71. {
  72. uint32_t phyclk;
  73. #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
  74. phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
  75. #else
  76. /* High speed PHY running at full speed or high speed */
  77. phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
  78. #endif
  79. #ifdef CONFIG_DWC2_ULPI_FS_LS
  80. uint32_t hwcfg2 = readl(&regs->ghwcfg2);
  81. uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
  82. DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
  83. uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
  84. DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
  85. if (hval == 2 && fval == 1)
  86. phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
  87. #endif
  88. clrsetbits_le32(&regs->host_regs.hcfg,
  89. DWC2_HCFG_FSLSPCLKSEL_MASK,
  90. phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
  91. }
  92. /*
  93. * Flush a Tx FIFO.
  94. *
  95. * @param regs Programming view of DWC_otg controller.
  96. * @param num Tx FIFO to flush.
  97. */
  98. static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
  99. {
  100. int ret;
  101. writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
  102. &regs->grstctl);
  103. ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_TXFFLSH,
  104. false, 1000, false);
  105. if (ret)
  106. dev_info(dev, "%s: Timeout!\n", __func__);
  107. /* Wait for 3 PHY Clocks */
  108. udelay(1);
  109. }
  110. /*
  111. * Flush Rx FIFO.
  112. *
  113. * @param regs Programming view of DWC_otg controller.
  114. */
  115. static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
  116. {
  117. int ret;
  118. writel(DWC2_GRSTCTL_RXFFLSH, &regs->grstctl);
  119. ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_RXFFLSH,
  120. false, 1000, false);
  121. if (ret)
  122. dev_info(dev, "%s: Timeout!\n", __func__);
  123. /* Wait for 3 PHY Clocks */
  124. udelay(1);
  125. }
  126. /*
  127. * Do core a soft reset of the core. Be careful with this because it
  128. * resets all the internal state machines of the core.
  129. */
  130. static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
  131. {
  132. int ret;
  133. /* Wait for AHB master IDLE state. */
  134. ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_AHBIDLE,
  135. true, 1000, false);
  136. if (ret)
  137. dev_info(dev, "%s: Timeout!\n", __func__);
  138. /* Core Soft Reset */
  139. writel(DWC2_GRSTCTL_CSFTRST, &regs->grstctl);
  140. ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_CSFTRST,
  141. false, 1000, false);
  142. if (ret)
  143. dev_info(dev, "%s: Timeout!\n", __func__);
  144. /*
  145. * Wait for core to come out of reset.
  146. * NOTE: This long sleep is _very_ important, otherwise the core will
  147. * not stay in host mode after a connector ID change!
  148. */
  149. mdelay(100);
  150. }
  151. #if CONFIG_IS_ENABLED(DM_USB) && defined(CONFIG_DM_REGULATOR)
  152. static int dwc_vbus_supply_init(struct udevice *dev)
  153. {
  154. struct dwc2_priv *priv = dev_get_priv(dev);
  155. int ret;
  156. ret = device_get_supply_regulator(dev, "vbus-supply",
  157. &priv->vbus_supply);
  158. if (ret) {
  159. debug("%s: No vbus supply\n", dev->name);
  160. return 0;
  161. }
  162. ret = regulator_set_enable(priv->vbus_supply, true);
  163. if (ret) {
  164. dev_err(dev, "Error enabling vbus supply\n");
  165. return ret;
  166. }
  167. return 0;
  168. }
  169. static int dwc_vbus_supply_exit(struct udevice *dev)
  170. {
  171. struct dwc2_priv *priv = dev_get_priv(dev);
  172. int ret;
  173. if (priv->vbus_supply) {
  174. ret = regulator_set_enable(priv->vbus_supply, false);
  175. if (ret) {
  176. dev_err(dev, "Error disabling vbus supply\n");
  177. return ret;
  178. }
  179. }
  180. return 0;
  181. }
  182. #else
  183. static int dwc_vbus_supply_init(struct udevice *dev)
  184. {
  185. return 0;
  186. }
  187. #if CONFIG_IS_ENABLED(DM_USB)
  188. static int dwc_vbus_supply_exit(struct udevice *dev)
  189. {
  190. return 0;
  191. }
  192. #endif
  193. #endif
  194. /*
  195. * This function initializes the DWC_otg controller registers for
  196. * host mode.
  197. *
  198. * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
  199. * request queues. Host channels are reset to ensure that they are ready for
  200. * performing transfers.
  201. *
  202. * @param dev USB Device (NULL if driver model is not being used)
  203. * @param regs Programming view of DWC_otg controller
  204. *
  205. */
  206. static void dwc_otg_core_host_init(struct udevice *dev,
  207. struct dwc2_core_regs *regs)
  208. {
  209. uint32_t nptxfifosize = 0;
  210. uint32_t ptxfifosize = 0;
  211. uint32_t hprt0 = 0;
  212. int i, ret, num_channels;
  213. /* Restart the Phy Clock */
  214. writel(0, &regs->pcgcctl);
  215. /* Initialize Host Configuration Register */
  216. init_fslspclksel(regs);
  217. #ifdef CONFIG_DWC2_DFLT_SPEED_FULL
  218. setbits_le32(&regs->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
  219. #endif
  220. /* Configure data FIFO sizes */
  221. #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
  222. if (readl(&regs->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
  223. /* Rx FIFO */
  224. writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, &regs->grxfsiz);
  225. /* Non-periodic Tx FIFO */
  226. nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
  227. DWC2_FIFOSIZE_DEPTH_OFFSET;
  228. nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
  229. DWC2_FIFOSIZE_STARTADDR_OFFSET;
  230. writel(nptxfifosize, &regs->gnptxfsiz);
  231. /* Periodic Tx FIFO */
  232. ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
  233. DWC2_FIFOSIZE_DEPTH_OFFSET;
  234. ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
  235. CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
  236. DWC2_FIFOSIZE_STARTADDR_OFFSET;
  237. writel(ptxfifosize, &regs->hptxfsiz);
  238. }
  239. #endif
  240. /* Clear Host Set HNP Enable in the OTG Control Register */
  241. clrbits_le32(&regs->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
  242. /* Make sure the FIFOs are flushed. */
  243. dwc_otg_flush_tx_fifo(regs, 0x10); /* All Tx FIFOs */
  244. dwc_otg_flush_rx_fifo(regs);
  245. /* Flush out any leftover queued requests. */
  246. num_channels = readl(&regs->ghwcfg2);
  247. num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
  248. num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
  249. num_channels += 1;
  250. for (i = 0; i < num_channels; i++)
  251. clrsetbits_le32(&regs->hc_regs[i].hcchar,
  252. DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
  253. DWC2_HCCHAR_CHDIS);
  254. /* Halt all channels to put them into a known state. */
  255. for (i = 0; i < num_channels; i++) {
  256. clrsetbits_le32(&regs->hc_regs[i].hcchar,
  257. DWC2_HCCHAR_EPDIR,
  258. DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
  259. ret = wait_for_bit_le32(&regs->hc_regs[i].hcchar,
  260. DWC2_HCCHAR_CHEN, false, 1000, false);
  261. if (ret)
  262. dev_info("%s: Timeout!\n", __func__);
  263. }
  264. /* Turn on the vbus power. */
  265. if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
  266. hprt0 = readl(&regs->hprt0);
  267. hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
  268. hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
  269. if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
  270. hprt0 |= DWC2_HPRT0_PRTPWR;
  271. writel(hprt0, &regs->hprt0);
  272. }
  273. }
  274. if (dev)
  275. dwc_vbus_supply_init(dev);
  276. }
  277. /*
  278. * This function initializes the DWC_otg controller registers and
  279. * prepares the core for device mode or host mode operation.
  280. *
  281. * @param regs Programming view of the DWC_otg controller
  282. */
  283. static void dwc_otg_core_init(struct dwc2_priv *priv)
  284. {
  285. struct dwc2_core_regs *regs = priv->regs;
  286. uint32_t ahbcfg = 0;
  287. uint32_t usbcfg = 0;
  288. uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
  289. /* Common Initialization */
  290. usbcfg = readl(&regs->gusbcfg);
  291. /* Program the ULPI External VBUS bit if needed */
  292. if (priv->ext_vbus) {
  293. usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
  294. if (!priv->oc_disable) {
  295. usbcfg |= DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR |
  296. DWC2_GUSBCFG_INDICATOR_PASSTHROUGH;
  297. }
  298. } else {
  299. usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
  300. }
  301. /* Set external TS Dline pulsing */
  302. #ifdef CONFIG_DWC2_TS_DLINE
  303. usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
  304. #else
  305. usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
  306. #endif
  307. writel(usbcfg, &regs->gusbcfg);
  308. /* Reset the Controller */
  309. dwc_otg_core_reset(regs);
  310. /*
  311. * This programming sequence needs to happen in FS mode before
  312. * any other programming occurs
  313. */
  314. #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
  315. (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
  316. /* If FS mode with FS PHY */
  317. setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_PHYSEL);
  318. /* Reset after a PHY select */
  319. dwc_otg_core_reset(regs);
  320. /*
  321. * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
  322. * Also do this on HNP Dev/Host mode switches (done in dev_init
  323. * and host_init).
  324. */
  325. if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
  326. init_fslspclksel(regs);
  327. #ifdef CONFIG_DWC2_I2C_ENABLE
  328. /* Program GUSBCFG.OtgUtmifsSel to I2C */
  329. setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
  330. /* Program GI2CCTL.I2CEn */
  331. clrsetbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN |
  332. DWC2_GI2CCTL_I2CDEVADDR_MASK,
  333. 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
  334. setbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN);
  335. #endif
  336. #else
  337. /* High speed PHY. */
  338. /*
  339. * HS PHY parameters. These parameters are preserved during
  340. * soft reset so only program the first time. Do a soft reset
  341. * immediately after setting phyif.
  342. */
  343. usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
  344. usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
  345. if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */
  346. #ifdef CONFIG_DWC2_PHY_ULPI_DDR
  347. usbcfg |= DWC2_GUSBCFG_DDRSEL;
  348. #else
  349. usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
  350. #endif
  351. } else { /* UTMI+ interface */
  352. #if (CONFIG_DWC2_UTMI_WIDTH == 16)
  353. usbcfg |= DWC2_GUSBCFG_PHYIF;
  354. #endif
  355. }
  356. writel(usbcfg, &regs->gusbcfg);
  357. /* Reset after setting the PHY parameters */
  358. dwc_otg_core_reset(regs);
  359. #endif
  360. usbcfg = readl(&regs->gusbcfg);
  361. usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
  362. #ifdef CONFIG_DWC2_ULPI_FS_LS
  363. uint32_t hwcfg2 = readl(&regs->ghwcfg2);
  364. uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
  365. DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
  366. uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
  367. DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
  368. if (hval == 2 && fval == 1) {
  369. usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
  370. usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
  371. }
  372. #endif
  373. if (priv->hnp_srp_disable)
  374. usbcfg |= DWC2_GUSBCFG_FORCEHOSTMODE;
  375. writel(usbcfg, &regs->gusbcfg);
  376. /* Program the GAHBCFG Register. */
  377. switch (readl(&regs->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
  378. case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
  379. break;
  380. case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
  381. while (brst_sz > 1) {
  382. ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
  383. ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
  384. brst_sz >>= 1;
  385. }
  386. #ifdef CONFIG_DWC2_DMA_ENABLE
  387. ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
  388. #endif
  389. break;
  390. case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
  391. ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
  392. #ifdef CONFIG_DWC2_DMA_ENABLE
  393. ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
  394. #endif
  395. break;
  396. }
  397. writel(ahbcfg, &regs->gahbcfg);
  398. /* Program the capabilities in GUSBCFG Register */
  399. usbcfg = 0;
  400. if (!priv->hnp_srp_disable)
  401. usbcfg |= DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP;
  402. #ifdef CONFIG_DWC2_IC_USB_CAP
  403. usbcfg |= DWC2_GUSBCFG_IC_USB_CAP;
  404. #endif
  405. setbits_le32(&regs->gusbcfg, usbcfg);
  406. }
  407. /*
  408. * Prepares a host channel for transferring packets to/from a specific
  409. * endpoint. The HCCHARn register is set up with the characteristics specified
  410. * in _hc. Host channel interrupts that may need to be serviced while this
  411. * transfer is in progress are enabled.
  412. *
  413. * @param regs Programming view of DWC_otg controller
  414. * @param hc Information needed to initialize the host channel
  415. */
  416. static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
  417. struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num,
  418. uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet)
  419. {
  420. struct dwc2_hc_regs *hc_regs = &regs->hc_regs[hc_num];
  421. uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
  422. (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
  423. (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
  424. (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
  425. (max_packet << DWC2_HCCHAR_MPS_OFFSET);
  426. if (dev->speed == USB_SPEED_LOW)
  427. hcchar |= DWC2_HCCHAR_LSPDDEV;
  428. /*
  429. * Program the HCCHARn register with the endpoint characteristics
  430. * for the current transfer.
  431. */
  432. writel(hcchar, &hc_regs->hcchar);
  433. /* Program the HCSPLIT register, default to no SPLIT */
  434. writel(0, &hc_regs->hcsplt);
  435. }
  436. static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs,
  437. uint8_t hub_devnum, uint8_t hub_port)
  438. {
  439. uint32_t hcsplt = 0;
  440. hcsplt = DWC2_HCSPLT_SPLTENA;
  441. hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET;
  442. hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET;
  443. /* Program the HCSPLIT register for SPLITs */
  444. writel(hcsplt, &hc_regs->hcsplt);
  445. }
  446. /*
  447. * DWC2 to USB API interface
  448. */
  449. /* Direction: In ; Request: Status */
  450. static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs,
  451. struct usb_device *dev, void *buffer,
  452. int txlen, struct devrequest *cmd)
  453. {
  454. uint32_t hprt0 = 0;
  455. uint32_t port_status = 0;
  456. uint32_t port_change = 0;
  457. int len = 0;
  458. int stat = 0;
  459. switch (cmd->requesttype & ~USB_DIR_IN) {
  460. case 0:
  461. *(uint16_t *)buffer = cpu_to_le16(1);
  462. len = 2;
  463. break;
  464. case USB_RECIP_INTERFACE:
  465. case USB_RECIP_ENDPOINT:
  466. *(uint16_t *)buffer = cpu_to_le16(0);
  467. len = 2;
  468. break;
  469. case USB_TYPE_CLASS:
  470. *(uint32_t *)buffer = cpu_to_le32(0);
  471. len = 4;
  472. break;
  473. case USB_RECIP_OTHER | USB_TYPE_CLASS:
  474. hprt0 = readl(&regs->hprt0);
  475. if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
  476. port_status |= USB_PORT_STAT_CONNECTION;
  477. if (hprt0 & DWC2_HPRT0_PRTENA)
  478. port_status |= USB_PORT_STAT_ENABLE;
  479. if (hprt0 & DWC2_HPRT0_PRTSUSP)
  480. port_status |= USB_PORT_STAT_SUSPEND;
  481. if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
  482. port_status |= USB_PORT_STAT_OVERCURRENT;
  483. if (hprt0 & DWC2_HPRT0_PRTRST)
  484. port_status |= USB_PORT_STAT_RESET;
  485. if (hprt0 & DWC2_HPRT0_PRTPWR)
  486. port_status |= USB_PORT_STAT_POWER;
  487. if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW)
  488. port_status |= USB_PORT_STAT_LOW_SPEED;
  489. else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
  490. DWC2_HPRT0_PRTSPD_HIGH)
  491. port_status |= USB_PORT_STAT_HIGH_SPEED;
  492. if (hprt0 & DWC2_HPRT0_PRTENCHNG)
  493. port_change |= USB_PORT_STAT_C_ENABLE;
  494. if (hprt0 & DWC2_HPRT0_PRTCONNDET)
  495. port_change |= USB_PORT_STAT_C_CONNECTION;
  496. if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
  497. port_change |= USB_PORT_STAT_C_OVERCURRENT;
  498. *(uint32_t *)buffer = cpu_to_le32(port_status |
  499. (port_change << 16));
  500. len = 4;
  501. break;
  502. default:
  503. puts("unsupported root hub command\n");
  504. stat = USB_ST_STALLED;
  505. }
  506. dev->act_len = min(len, txlen);
  507. dev->status = stat;
  508. return stat;
  509. }
  510. /* Direction: In ; Request: Descriptor */
  511. static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
  512. void *buffer, int txlen,
  513. struct devrequest *cmd)
  514. {
  515. unsigned char data[32];
  516. uint32_t dsc;
  517. int len = 0;
  518. int stat = 0;
  519. uint16_t wValue = cpu_to_le16(cmd->value);
  520. uint16_t wLength = cpu_to_le16(cmd->length);
  521. switch (cmd->requesttype & ~USB_DIR_IN) {
  522. case 0:
  523. switch (wValue & 0xff00) {
  524. case 0x0100: /* device descriptor */
  525. len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
  526. memcpy(buffer, root_hub_dev_des, len);
  527. break;
  528. case 0x0200: /* configuration descriptor */
  529. len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
  530. memcpy(buffer, root_hub_config_des, len);
  531. break;
  532. case 0x0300: /* string descriptors */
  533. switch (wValue & 0xff) {
  534. case 0x00:
  535. len = min3(txlen, (int)sizeof(root_hub_str_index0),
  536. (int)wLength);
  537. memcpy(buffer, root_hub_str_index0, len);
  538. break;
  539. case 0x01:
  540. len = min3(txlen, (int)sizeof(root_hub_str_index1),
  541. (int)wLength);
  542. memcpy(buffer, root_hub_str_index1, len);
  543. break;
  544. }
  545. break;
  546. default:
  547. stat = USB_ST_STALLED;
  548. }
  549. break;
  550. case USB_TYPE_CLASS:
  551. /* Root port config, set 1 port and nothing else. */
  552. dsc = 0x00000001;
  553. data[0] = 9; /* min length; */
  554. data[1] = 0x29;
  555. data[2] = dsc & RH_A_NDP;
  556. data[3] = 0;
  557. if (dsc & RH_A_PSM)
  558. data[3] |= 0x1;
  559. if (dsc & RH_A_NOCP)
  560. data[3] |= 0x10;
  561. else if (dsc & RH_A_OCPM)
  562. data[3] |= 0x8;
  563. /* corresponds to data[4-7] */
  564. data[5] = (dsc & RH_A_POTPGT) >> 24;
  565. data[7] = dsc & RH_B_DR;
  566. if (data[2] < 7) {
  567. data[8] = 0xff;
  568. } else {
  569. data[0] += 2;
  570. data[8] = (dsc & RH_B_DR) >> 8;
  571. data[9] = 0xff;
  572. data[10] = data[9];
  573. }
  574. len = min3(txlen, (int)data[0], (int)wLength);
  575. memcpy(buffer, data, len);
  576. break;
  577. default:
  578. puts("unsupported root hub command\n");
  579. stat = USB_ST_STALLED;
  580. }
  581. dev->act_len = min(len, txlen);
  582. dev->status = stat;
  583. return stat;
  584. }
  585. /* Direction: In ; Request: Configuration */
  586. static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
  587. void *buffer, int txlen,
  588. struct devrequest *cmd)
  589. {
  590. int len = 0;
  591. int stat = 0;
  592. switch (cmd->requesttype & ~USB_DIR_IN) {
  593. case 0:
  594. *(uint8_t *)buffer = 0x01;
  595. len = 1;
  596. break;
  597. default:
  598. puts("unsupported root hub command\n");
  599. stat = USB_ST_STALLED;
  600. }
  601. dev->act_len = min(len, txlen);
  602. dev->status = stat;
  603. return stat;
  604. }
  605. /* Direction: In */
  606. static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv,
  607. struct usb_device *dev, void *buffer,
  608. int txlen, struct devrequest *cmd)
  609. {
  610. switch (cmd->request) {
  611. case USB_REQ_GET_STATUS:
  612. return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer,
  613. txlen, cmd);
  614. case USB_REQ_GET_DESCRIPTOR:
  615. return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
  616. txlen, cmd);
  617. case USB_REQ_GET_CONFIGURATION:
  618. return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
  619. txlen, cmd);
  620. default:
  621. puts("unsupported root hub command\n");
  622. return USB_ST_STALLED;
  623. }
  624. }
  625. /* Direction: Out */
  626. static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv,
  627. struct usb_device *dev,
  628. void *buffer, int txlen,
  629. struct devrequest *cmd)
  630. {
  631. struct dwc2_core_regs *regs = priv->regs;
  632. int len = 0;
  633. int stat = 0;
  634. uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
  635. uint16_t wValue = cpu_to_le16(cmd->value);
  636. switch (bmrtype_breq & ~USB_DIR_IN) {
  637. case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
  638. case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
  639. break;
  640. case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
  641. switch (wValue) {
  642. case USB_PORT_FEAT_C_CONNECTION:
  643. setbits_le32(&regs->hprt0, DWC2_HPRT0_PRTCONNDET);
  644. break;
  645. }
  646. break;
  647. case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
  648. switch (wValue) {
  649. case USB_PORT_FEAT_SUSPEND:
  650. break;
  651. case USB_PORT_FEAT_RESET:
  652. clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
  653. DWC2_HPRT0_PRTCONNDET |
  654. DWC2_HPRT0_PRTENCHNG |
  655. DWC2_HPRT0_PRTOVRCURRCHNG,
  656. DWC2_HPRT0_PRTRST);
  657. mdelay(50);
  658. clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTRST);
  659. break;
  660. case USB_PORT_FEAT_POWER:
  661. clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
  662. DWC2_HPRT0_PRTCONNDET |
  663. DWC2_HPRT0_PRTENCHNG |
  664. DWC2_HPRT0_PRTOVRCURRCHNG,
  665. DWC2_HPRT0_PRTRST);
  666. break;
  667. case USB_PORT_FEAT_ENABLE:
  668. break;
  669. }
  670. break;
  671. case (USB_REQ_SET_ADDRESS << 8):
  672. priv->root_hub_devnum = wValue;
  673. break;
  674. case (USB_REQ_SET_CONFIGURATION << 8):
  675. break;
  676. default:
  677. puts("unsupported root hub command\n");
  678. stat = USB_ST_STALLED;
  679. }
  680. len = min(len, txlen);
  681. dev->act_len = len;
  682. dev->status = stat;
  683. return stat;
  684. }
  685. static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev,
  686. unsigned long pipe, void *buffer, int txlen,
  687. struct devrequest *cmd)
  688. {
  689. int stat = 0;
  690. if (usb_pipeint(pipe)) {
  691. puts("Root-Hub submit IRQ: NOT implemented\n");
  692. return 0;
  693. }
  694. if (cmd->requesttype & USB_DIR_IN)
  695. stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd);
  696. else
  697. stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd);
  698. mdelay(1);
  699. return stat;
  700. }
  701. int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle)
  702. {
  703. int ret;
  704. uint32_t hcint, hctsiz;
  705. ret = wait_for_bit_le32(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true,
  706. 2000, false);
  707. if (ret)
  708. return ret;
  709. hcint = readl(&hc_regs->hcint);
  710. hctsiz = readl(&hc_regs->hctsiz);
  711. *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
  712. DWC2_HCTSIZ_XFERSIZE_OFFSET;
  713. *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
  714. debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub,
  715. *toggle);
  716. if (hcint & DWC2_HCINT_XFERCOMP)
  717. return 0;
  718. if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
  719. return -EAGAIN;
  720. debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
  721. return -EINVAL;
  722. }
  723. static int dwc2_eptype[] = {
  724. DWC2_HCCHAR_EPTYPE_ISOC,
  725. DWC2_HCCHAR_EPTYPE_INTR,
  726. DWC2_HCCHAR_EPTYPE_CONTROL,
  727. DWC2_HCCHAR_EPTYPE_BULK,
  728. };
  729. static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
  730. u8 *pid, int in, void *buffer, int num_packets,
  731. int xfer_len, int *actual_len, int odd_frame)
  732. {
  733. int ret = 0;
  734. uint32_t sub;
  735. debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
  736. *pid, xfer_len, num_packets);
  737. writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
  738. (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
  739. (*pid << DWC2_HCTSIZ_PID_OFFSET),
  740. &hc_regs->hctsiz);
  741. if (xfer_len) {
  742. if (in) {
  743. invalidate_dcache_range(
  744. (uintptr_t)aligned_buffer,
  745. (uintptr_t)aligned_buffer +
  746. roundup(xfer_len, ARCH_DMA_MINALIGN));
  747. } else {
  748. memcpy(aligned_buffer, buffer, xfer_len);
  749. flush_dcache_range(
  750. (uintptr_t)aligned_buffer,
  751. (uintptr_t)aligned_buffer +
  752. roundup(xfer_len, ARCH_DMA_MINALIGN));
  753. }
  754. }
  755. writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma);
  756. /* Clear old interrupt conditions for this host channel. */
  757. writel(0x3fff, &hc_regs->hcint);
  758. /* Set host channel enable after all other setup is complete. */
  759. clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
  760. DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS |
  761. DWC2_HCCHAR_ODDFRM,
  762. (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
  763. (odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) |
  764. DWC2_HCCHAR_CHEN);
  765. ret = wait_for_chhltd(hc_regs, &sub, pid);
  766. if (ret < 0)
  767. return ret;
  768. if (in) {
  769. xfer_len -= sub;
  770. invalidate_dcache_range((unsigned long)aligned_buffer,
  771. (unsigned long)aligned_buffer +
  772. roundup(xfer_len, ARCH_DMA_MINALIGN));
  773. memcpy(buffer, aligned_buffer, xfer_len);
  774. }
  775. *actual_len = xfer_len;
  776. return ret;
  777. }
  778. int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
  779. unsigned long pipe, u8 *pid, int in, void *buffer, int len)
  780. {
  781. struct dwc2_core_regs *regs = priv->regs;
  782. struct dwc2_hc_regs *hc_regs = &regs->hc_regs[DWC2_HC_CHANNEL];
  783. struct dwc2_host_regs *host_regs = &regs->host_regs;
  784. int devnum = usb_pipedevice(pipe);
  785. int ep = usb_pipeendpoint(pipe);
  786. int max = usb_maxpacket(dev, pipe);
  787. int eptype = dwc2_eptype[usb_pipetype(pipe)];
  788. int done = 0;
  789. int ret = 0;
  790. int do_split = 0;
  791. int complete_split = 0;
  792. uint32_t xfer_len;
  793. uint32_t num_packets;
  794. int stop_transfer = 0;
  795. uint32_t max_xfer_len;
  796. int ssplit_frame_num = 0;
  797. debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
  798. in, len);
  799. max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max;
  800. if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
  801. max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE;
  802. if (max_xfer_len > DWC2_DATA_BUF_SIZE)
  803. max_xfer_len = DWC2_DATA_BUF_SIZE;
  804. /* Make sure that max_xfer_len is a multiple of max packet size. */
  805. num_packets = max_xfer_len / max;
  806. max_xfer_len = num_packets * max;
  807. /* Initialize channel */
  808. dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
  809. eptype, max);
  810. /* Check if the target is a FS/LS device behind a HS hub */
  811. if (dev->speed != USB_SPEED_HIGH) {
  812. uint8_t hub_addr;
  813. uint8_t hub_port;
  814. uint32_t hprt0 = readl(&regs->hprt0);
  815. if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
  816. DWC2_HPRT0_PRTSPD_HIGH) {
  817. usb_find_usb2_hub_address_port(dev, &hub_addr,
  818. &hub_port);
  819. dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port);
  820. do_split = 1;
  821. num_packets = 1;
  822. max_xfer_len = max;
  823. }
  824. }
  825. do {
  826. int actual_len = 0;
  827. uint32_t hcint;
  828. int odd_frame = 0;
  829. xfer_len = len - done;
  830. if (xfer_len > max_xfer_len)
  831. xfer_len = max_xfer_len;
  832. else if (xfer_len > max)
  833. num_packets = (xfer_len + max - 1) / max;
  834. else
  835. num_packets = 1;
  836. if (complete_split)
  837. setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
  838. else if (do_split)
  839. clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
  840. if (eptype == DWC2_HCCHAR_EPTYPE_INTR) {
  841. int uframe_num = readl(&host_regs->hfnum);
  842. if (!(uframe_num & 0x1))
  843. odd_frame = 1;
  844. }
  845. ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid,
  846. in, (char *)buffer + done, num_packets,
  847. xfer_len, &actual_len, odd_frame);
  848. hcint = readl(&hc_regs->hcint);
  849. if (complete_split) {
  850. stop_transfer = 0;
  851. if (hcint & DWC2_HCINT_NYET) {
  852. ret = 0;
  853. int frame_num = DWC2_HFNUM_MAX_FRNUM &
  854. readl(&host_regs->hfnum);
  855. if (((frame_num - ssplit_frame_num) &
  856. DWC2_HFNUM_MAX_FRNUM) > 4)
  857. ret = -EAGAIN;
  858. } else
  859. complete_split = 0;
  860. } else if (do_split) {
  861. if (hcint & DWC2_HCINT_ACK) {
  862. ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM &
  863. readl(&host_regs->hfnum);
  864. ret = 0;
  865. complete_split = 1;
  866. }
  867. }
  868. if (ret)
  869. break;
  870. if (actual_len < xfer_len)
  871. stop_transfer = 1;
  872. done += actual_len;
  873. /* Transactions are done when when either all data is transferred or
  874. * there is a short transfer. In case of a SPLIT make sure the CSPLIT
  875. * is executed.
  876. */
  877. } while (((done < len) && !stop_transfer) || complete_split);
  878. writel(0, &hc_regs->hcintmsk);
  879. writel(0xFFFFFFFF, &hc_regs->hcint);
  880. dev->status = 0;
  881. dev->act_len = done;
  882. return ret;
  883. }
  884. /* U-Boot USB transmission interface */
  885. int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev,
  886. unsigned long pipe, void *buffer, int len)
  887. {
  888. int devnum = usb_pipedevice(pipe);
  889. int ep = usb_pipeendpoint(pipe);
  890. u8* pid;
  891. if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) {
  892. dev->status = 0;
  893. return -EINVAL;
  894. }
  895. if (usb_pipein(pipe))
  896. pid = &priv->in_data_toggle[devnum][ep];
  897. else
  898. pid = &priv->out_data_toggle[devnum][ep];
  899. return chunk_msg(priv, dev, pipe, pid, usb_pipein(pipe), buffer, len);
  900. }
  901. static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
  902. unsigned long pipe, void *buffer, int len,
  903. struct devrequest *setup)
  904. {
  905. int devnum = usb_pipedevice(pipe);
  906. int ret, act_len;
  907. u8 pid;
  908. /* For CONTROL endpoint pid should start with DATA1 */
  909. int status_direction;
  910. if (devnum == priv->root_hub_devnum) {
  911. dev->status = 0;
  912. dev->speed = USB_SPEED_HIGH;
  913. return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len,
  914. setup);
  915. }
  916. /* SETUP stage */
  917. pid = DWC2_HC_PID_SETUP;
  918. do {
  919. ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8);
  920. } while (ret == -EAGAIN);
  921. if (ret)
  922. return ret;
  923. /* DATA stage */
  924. act_len = 0;
  925. if (buffer) {
  926. pid = DWC2_HC_PID_DATA1;
  927. do {
  928. ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe),
  929. buffer, len);
  930. act_len += dev->act_len;
  931. buffer += dev->act_len;
  932. len -= dev->act_len;
  933. } while (ret == -EAGAIN);
  934. if (ret)
  935. return ret;
  936. status_direction = usb_pipeout(pipe);
  937. } else {
  938. /* No-data CONTROL always ends with an IN transaction */
  939. status_direction = 1;
  940. }
  941. /* STATUS stage */
  942. pid = DWC2_HC_PID_DATA1;
  943. do {
  944. ret = chunk_msg(priv, dev, pipe, &pid, status_direction,
  945. priv->status_buffer, 0);
  946. } while (ret == -EAGAIN);
  947. if (ret)
  948. return ret;
  949. dev->act_len = act_len;
  950. return 0;
  951. }
  952. int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev,
  953. unsigned long pipe, void *buffer, int len, int interval,
  954. bool nonblock)
  955. {
  956. unsigned long timeout;
  957. int ret;
  958. /* FIXME: what is interval? */
  959. timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
  960. for (;;) {
  961. if (get_timer(0) > timeout) {
  962. dev_err(dev, "Timeout poll on interrupt endpoint\n");
  963. return -ETIMEDOUT;
  964. }
  965. ret = _submit_bulk_msg(priv, dev, pipe, buffer, len);
  966. if ((ret != -EAGAIN) || nonblock)
  967. return ret;
  968. }
  969. }
  970. static int dwc2_reset(struct udevice *dev)
  971. {
  972. int ret;
  973. struct dwc2_priv *priv = dev_get_priv(dev);
  974. ret = reset_get_bulk(dev, &priv->resets);
  975. if (ret) {
  976. dev_warn(dev, "Can't get reset: %d\n", ret);
  977. /* Return 0 if error due to !CONFIG_DM_RESET and reset
  978. * DT property is not present.
  979. */
  980. if (ret == -ENOENT || ret == -ENOTSUPP)
  981. return 0;
  982. else
  983. return ret;
  984. }
  985. /* force reset to clear all IP register */
  986. reset_assert_bulk(&priv->resets);
  987. ret = reset_deassert_bulk(&priv->resets);
  988. if (ret) {
  989. reset_release_bulk(&priv->resets);
  990. dev_err(dev, "Failed to reset: %d\n", ret);
  991. return ret;
  992. }
  993. return 0;
  994. }
  995. static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv)
  996. {
  997. struct dwc2_core_regs *regs = priv->regs;
  998. uint32_t snpsid;
  999. int i, j;
  1000. int ret;
  1001. ret = dwc2_reset(dev);
  1002. if (ret)
  1003. return ret;
  1004. snpsid = readl(&regs->gsnpsid);
  1005. dev_info(dev, "Core Release: %x.%03x\n",
  1006. snpsid >> 12 & 0xf, snpsid & 0xfff);
  1007. if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
  1008. (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
  1009. dev_info(dev, "SNPSID invalid (not DWC2 OTG device): %08x\n",
  1010. snpsid);
  1011. return -ENODEV;
  1012. }
  1013. #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
  1014. priv->ext_vbus = 1;
  1015. #else
  1016. priv->ext_vbus = 0;
  1017. #endif
  1018. dwc_otg_core_init(priv);
  1019. dwc_otg_core_host_init(dev, regs);
  1020. clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
  1021. DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
  1022. DWC2_HPRT0_PRTOVRCURRCHNG,
  1023. DWC2_HPRT0_PRTRST);
  1024. mdelay(50);
  1025. clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
  1026. DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
  1027. DWC2_HPRT0_PRTRST);
  1028. for (i = 0; i < MAX_DEVICE; i++) {
  1029. for (j = 0; j < MAX_ENDPOINT; j++) {
  1030. priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0;
  1031. priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0;
  1032. }
  1033. }
  1034. /*
  1035. * Add a 1 second delay here. This gives the host controller
  1036. * a bit time before the comminucation with the USB devices
  1037. * is started (the bus is scanned) and fixes the USB detection
  1038. * problems with some problematic USB keys.
  1039. */
  1040. if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
  1041. mdelay(1000);
  1042. printf("USB DWC2\n");
  1043. return 0;
  1044. }
  1045. static void dwc2_uninit_common(struct dwc2_core_regs *regs)
  1046. {
  1047. /* Put everything in reset. */
  1048. clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
  1049. DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
  1050. DWC2_HPRT0_PRTOVRCURRCHNG,
  1051. DWC2_HPRT0_PRTRST);
  1052. }
  1053. #if !CONFIG_IS_ENABLED(DM_USB)
  1054. int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1055. int len, struct devrequest *setup)
  1056. {
  1057. return _submit_control_msg(&local, dev, pipe, buffer, len, setup);
  1058. }
  1059. int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1060. int len)
  1061. {
  1062. return _submit_bulk_msg(&local, dev, pipe, buffer, len);
  1063. }
  1064. int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1065. int len, int interval, bool nonblock)
  1066. {
  1067. return _submit_int_msg(&local, dev, pipe, buffer, len, interval,
  1068. nonblock);
  1069. }
  1070. /* U-Boot USB control interface */
  1071. int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
  1072. {
  1073. struct dwc2_priv *priv = &local;
  1074. memset(priv, '\0', sizeof(*priv));
  1075. priv->root_hub_devnum = 0;
  1076. priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
  1077. priv->aligned_buffer = aligned_buffer_addr;
  1078. priv->status_buffer = status_buffer_addr;
  1079. /* board-dependant init */
  1080. if (board_usb_init(index, USB_INIT_HOST))
  1081. return -1;
  1082. return dwc2_init_common(NULL, priv);
  1083. }
  1084. int usb_lowlevel_stop(int index)
  1085. {
  1086. dwc2_uninit_common(local.regs);
  1087. return 0;
  1088. }
  1089. #endif
  1090. #if CONFIG_IS_ENABLED(DM_USB)
  1091. static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev,
  1092. unsigned long pipe, void *buffer, int length,
  1093. struct devrequest *setup)
  1094. {
  1095. struct dwc2_priv *priv = dev_get_priv(dev);
  1096. debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
  1097. dev->name, udev, udev->dev->name, udev->portnr);
  1098. return _submit_control_msg(priv, udev, pipe, buffer, length, setup);
  1099. }
  1100. static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
  1101. unsigned long pipe, void *buffer, int length)
  1102. {
  1103. struct dwc2_priv *priv = dev_get_priv(dev);
  1104. debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
  1105. return _submit_bulk_msg(priv, udev, pipe, buffer, length);
  1106. }
  1107. static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev,
  1108. unsigned long pipe, void *buffer, int length,
  1109. int interval, bool nonblock)
  1110. {
  1111. struct dwc2_priv *priv = dev_get_priv(dev);
  1112. debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
  1113. return _submit_int_msg(priv, udev, pipe, buffer, length, interval,
  1114. nonblock);
  1115. }
  1116. static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
  1117. {
  1118. struct dwc2_priv *priv = dev_get_priv(dev);
  1119. fdt_addr_t addr;
  1120. addr = dev_read_addr(dev);
  1121. if (addr == FDT_ADDR_T_NONE)
  1122. return -EINVAL;
  1123. priv->regs = (struct dwc2_core_regs *)addr;
  1124. priv->oc_disable = dev_read_bool(dev, "disable-over-current");
  1125. priv->hnp_srp_disable = dev_read_bool(dev, "hnp-srp-disable");
  1126. return 0;
  1127. }
  1128. static int dwc2_setup_phy(struct udevice *dev)
  1129. {
  1130. struct dwc2_priv *priv = dev_get_priv(dev);
  1131. int ret;
  1132. ret = generic_phy_get_by_index(dev, 0, &priv->phy);
  1133. if (ret) {
  1134. if (ret == -ENOENT)
  1135. return 0; /* no PHY, nothing to do */
  1136. dev_err(dev, "Failed to get USB PHY: %d.\n", ret);
  1137. return ret;
  1138. }
  1139. ret = generic_phy_init(&priv->phy);
  1140. if (ret) {
  1141. dev_dbg(dev, "Failed to init USB PHY: %d.\n", ret);
  1142. return ret;
  1143. }
  1144. ret = generic_phy_power_on(&priv->phy);
  1145. if (ret) {
  1146. dev_dbg(dev, "Failed to power on USB PHY: %d.\n", ret);
  1147. generic_phy_exit(&priv->phy);
  1148. return ret;
  1149. }
  1150. return 0;
  1151. }
  1152. static int dwc2_shutdown_phy(struct udevice *dev)
  1153. {
  1154. struct dwc2_priv *priv = dev_get_priv(dev);
  1155. int ret;
  1156. /* PHY is not valid when generic_phy_get_by_index() = -ENOENT */
  1157. if (!generic_phy_valid(&priv->phy))
  1158. return 0; /* no PHY, nothing to do */
  1159. ret = generic_phy_power_off(&priv->phy);
  1160. if (ret) {
  1161. dev_dbg(dev, "Failed to power off USB PHY: %d.\n", ret);
  1162. return ret;
  1163. }
  1164. ret = generic_phy_exit(&priv->phy);
  1165. if (ret) {
  1166. dev_dbg(dev, "Failed to power off USB PHY: %d.\n", ret);
  1167. return ret;
  1168. }
  1169. return 0;
  1170. }
  1171. static int dwc2_clk_init(struct udevice *dev)
  1172. {
  1173. struct dwc2_priv *priv = dev_get_priv(dev);
  1174. int ret;
  1175. ret = clk_get_bulk(dev, &priv->clks);
  1176. if (ret == -ENOSYS || ret == -ENOENT)
  1177. return 0;
  1178. if (ret)
  1179. return ret;
  1180. ret = clk_enable_bulk(&priv->clks);
  1181. if (ret) {
  1182. clk_release_bulk(&priv->clks);
  1183. return ret;
  1184. }
  1185. return 0;
  1186. }
  1187. static int dwc2_usb_probe(struct udevice *dev)
  1188. {
  1189. struct dwc2_priv *priv = dev_get_priv(dev);
  1190. struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev);
  1191. int ret;
  1192. bus_priv->desc_before_addr = true;
  1193. ret = dwc2_clk_init(dev);
  1194. if (ret)
  1195. return ret;
  1196. ret = dwc2_setup_phy(dev);
  1197. if (ret)
  1198. return ret;
  1199. return dwc2_init_common(dev, priv);
  1200. }
  1201. static int dwc2_usb_remove(struct udevice *dev)
  1202. {
  1203. struct dwc2_priv *priv = dev_get_priv(dev);
  1204. int ret;
  1205. ret = dwc_vbus_supply_exit(dev);
  1206. if (ret)
  1207. return ret;
  1208. ret = dwc2_shutdown_phy(dev);
  1209. if (ret) {
  1210. dev_dbg(dev, "Failed to shutdown USB PHY: %d.\n", ret);
  1211. return ret;
  1212. }
  1213. dwc2_uninit_common(priv->regs);
  1214. reset_release_bulk(&priv->resets);
  1215. clk_disable_bulk(&priv->clks);
  1216. clk_release_bulk(&priv->clks);
  1217. return 0;
  1218. }
  1219. struct dm_usb_ops dwc2_usb_ops = {
  1220. .control = dwc2_submit_control_msg,
  1221. .bulk = dwc2_submit_bulk_msg,
  1222. .interrupt = dwc2_submit_int_msg,
  1223. };
  1224. static const struct udevice_id dwc2_usb_ids[] = {
  1225. { .compatible = "brcm,bcm2835-usb" },
  1226. { .compatible = "brcm,bcm2708-usb" },
  1227. { .compatible = "snps,dwc2" },
  1228. { }
  1229. };
  1230. U_BOOT_DRIVER(usb_dwc2) = {
  1231. .name = "dwc2_usb",
  1232. .id = UCLASS_USB,
  1233. .of_match = dwc2_usb_ids,
  1234. .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata,
  1235. .probe = dwc2_usb_probe,
  1236. .remove = dwc2_usb_remove,
  1237. .ops = &dwc2_usb_ops,
  1238. .priv_auto_alloc_size = sizeof(struct dwc2_priv),
  1239. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  1240. };
  1241. #endif