pcie_xilinx.c 5.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Xilinx AXI Bridge for PCI Express Driver
  4. *
  5. * Copyright (C) 2016 Imagination Technologies
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <pci.h>
  10. #include <asm/io.h>
  11. /**
  12. * struct xilinx_pcie - Xilinx PCIe controller state
  13. * @cfg_base: The base address of memory mapped configuration space
  14. */
  15. struct xilinx_pcie {
  16. void *cfg_base;
  17. };
  18. /* Register definitions */
  19. #define XILINX_PCIE_REG_PSCR 0x144
  20. #define XILINX_PCIE_REG_PSCR_LNKUP BIT(11)
  21. /**
  22. * pcie_xilinx_link_up() - Check whether the PCIe link is up
  23. * @pcie: Pointer to the PCI controller state
  24. *
  25. * Checks whether the PCIe link for the given device is up or down.
  26. *
  27. * Return: true if the link is up, else false
  28. */
  29. static bool pcie_xilinx_link_up(struct xilinx_pcie *pcie)
  30. {
  31. uint32_t pscr = __raw_readl(pcie->cfg_base + XILINX_PCIE_REG_PSCR);
  32. return pscr & XILINX_PCIE_REG_PSCR_LNKUP;
  33. }
  34. /**
  35. * pcie_xilinx_config_address() - Calculate the address of a config access
  36. * @udev: Pointer to the PCI bus
  37. * @bdf: Identifies the PCIe device to access
  38. * @offset: The offset into the device's configuration space
  39. * @paddress: Pointer to the pointer to write the calculates address to
  40. *
  41. * Calculates the address that should be accessed to perform a PCIe
  42. * configuration space access for a given device identified by the PCIe
  43. * controller device @pcie and the bus, device & function numbers in @bdf. If
  44. * access to the device is not valid then the function will return an error
  45. * code. Otherwise the address to access will be written to the pointer pointed
  46. * to by @paddress.
  47. *
  48. * Return: 0 on success, else -ENODEV
  49. */
  50. static int pcie_xilinx_config_address(const struct udevice *udev, pci_dev_t bdf,
  51. uint offset, void **paddress)
  52. {
  53. struct xilinx_pcie *pcie = dev_get_priv(udev);
  54. unsigned int bus = PCI_BUS(bdf);
  55. unsigned int dev = PCI_DEV(bdf);
  56. unsigned int func = PCI_FUNC(bdf);
  57. void *addr;
  58. if ((bus > 0) && !pcie_xilinx_link_up(pcie))
  59. return -ENODEV;
  60. /*
  61. * Busses 0 (host-PCIe bridge) & 1 (its immediate child) are
  62. * limited to a single device each.
  63. */
  64. if ((bus < 2) && (dev > 0))
  65. return -ENODEV;
  66. addr = pcie->cfg_base;
  67. addr += bus << 20;
  68. addr += dev << 15;
  69. addr += func << 12;
  70. addr += offset;
  71. *paddress = addr;
  72. return 0;
  73. }
  74. /**
  75. * pcie_xilinx_read_config() - Read from configuration space
  76. * @bus: Pointer to the PCI bus
  77. * @bdf: Identifies the PCIe device to access
  78. * @offset: The offset into the device's configuration space
  79. * @valuep: A pointer at which to store the read value
  80. * @size: Indicates the size of access to perform
  81. *
  82. * Read a value of size @size from offset @offset within the configuration
  83. * space of the device identified by the bus, device & function numbers in @bdf
  84. * on the PCI bus @bus.
  85. *
  86. * Return: 0 on success, else -ENODEV or -EINVAL
  87. */
  88. static int pcie_xilinx_read_config(const struct udevice *bus, pci_dev_t bdf,
  89. uint offset, ulong *valuep,
  90. enum pci_size_t size)
  91. {
  92. return pci_generic_mmap_read_config(bus, pcie_xilinx_config_address,
  93. bdf, offset, valuep, size);
  94. }
  95. /**
  96. * pcie_xilinx_write_config() - Write to configuration space
  97. * @bus: Pointer to the PCI bus
  98. * @bdf: Identifies the PCIe device to access
  99. * @offset: The offset into the device's configuration space
  100. * @value: The value to write
  101. * @size: Indicates the size of access to perform
  102. *
  103. * Write the value @value of size @size from offset @offset within the
  104. * configuration space of the device identified by the bus, device & function
  105. * numbers in @bdf on the PCI bus @bus.
  106. *
  107. * Return: 0 on success, else -ENODEV or -EINVAL
  108. */
  109. static int pcie_xilinx_write_config(struct udevice *bus, pci_dev_t bdf,
  110. uint offset, ulong value,
  111. enum pci_size_t size)
  112. {
  113. return pci_generic_mmap_write_config(bus, pcie_xilinx_config_address,
  114. bdf, offset, value, size);
  115. }
  116. /**
  117. * pcie_xilinx_ofdata_to_platdata() - Translate from DT to device state
  118. * @dev: A pointer to the device being operated on
  119. *
  120. * Translate relevant data from the device tree pertaining to device @dev into
  121. * state that the driver will later make use of. This state is stored in the
  122. * device's private data structure.
  123. *
  124. * Return: 0 on success, else -EINVAL
  125. */
  126. static int pcie_xilinx_ofdata_to_platdata(struct udevice *dev)
  127. {
  128. struct xilinx_pcie *pcie = dev_get_priv(dev);
  129. struct fdt_resource reg_res;
  130. DECLARE_GLOBAL_DATA_PTR;
  131. int err;
  132. err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg",
  133. 0, &reg_res);
  134. if (err < 0) {
  135. pr_err("\"reg\" resource not found\n");
  136. return err;
  137. }
  138. pcie->cfg_base = map_physmem(reg_res.start,
  139. fdt_resource_size(&reg_res),
  140. MAP_NOCACHE);
  141. return 0;
  142. }
  143. static const struct dm_pci_ops pcie_xilinx_ops = {
  144. .read_config = pcie_xilinx_read_config,
  145. .write_config = pcie_xilinx_write_config,
  146. };
  147. static const struct udevice_id pcie_xilinx_ids[] = {
  148. { .compatible = "xlnx,axi-pcie-host-1.00.a" },
  149. { }
  150. };
  151. U_BOOT_DRIVER(pcie_xilinx) = {
  152. .name = "pcie_xilinx",
  153. .id = UCLASS_PCI,
  154. .of_match = pcie_xilinx_ids,
  155. .ops = &pcie_xilinx_ops,
  156. .ofdata_to_platdata = pcie_xilinx_ofdata_to_platdata,
  157. .priv_auto_alloc_size = sizeof(struct xilinx_pcie),
  158. };