pcie_mediatek.c 6.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * MediaTek PCIe host controller driver.
  4. *
  5. * Copyright (c) 2017-2019 MediaTek Inc.
  6. * Author: Ryder Lee <ryder.lee@mediatek.com>
  7. * Honghui Zhang <honghui.zhang@mediatek.com>
  8. */
  9. #include <common.h>
  10. #include <clk.h>
  11. #include <dm.h>
  12. #include <generic-phy.h>
  13. #include <malloc.h>
  14. #include <pci.h>
  15. #include <reset.h>
  16. #include <asm/io.h>
  17. #include <dm/devres.h>
  18. #include <linux/iopoll.h>
  19. #include <linux/list.h>
  20. /* PCIe shared registers */
  21. #define PCIE_SYS_CFG 0x00
  22. #define PCIE_INT_ENABLE 0x0c
  23. #define PCIE_CFG_ADDR 0x20
  24. #define PCIE_CFG_DATA 0x24
  25. /* PCIe per port registers */
  26. #define PCIE_BAR0_SETUP 0x10
  27. #define PCIE_CLASS 0x34
  28. #define PCIE_LINK_STATUS 0x50
  29. #define PCIE_PORT_INT_EN(x) BIT(20 + (x))
  30. #define PCIE_PORT_PERST(x) BIT(1 + (x))
  31. #define PCIE_PORT_LINKUP BIT(0)
  32. #define PCIE_BAR_MAP_MAX GENMASK(31, 16)
  33. #define PCIE_BAR_ENABLE BIT(0)
  34. #define PCIE_REVISION_ID BIT(0)
  35. #define PCIE_CLASS_CODE (0x60400 << 8)
  36. #define PCIE_CONF_REG(regn) (((regn) & GENMASK(7, 2)) | \
  37. ((((regn) >> 8) & GENMASK(3, 0)) << 24))
  38. #define PCIE_CONF_ADDR(regn, bdf) \
  39. (PCIE_CONF_REG(regn) | (bdf))
  40. /* MediaTek specific configuration registers */
  41. #define PCIE_FTS_NUM 0x70c
  42. #define PCIE_FTS_NUM_MASK GENMASK(15, 8)
  43. #define PCIE_FTS_NUM_L0(x) ((x) & 0xff << 8)
  44. #define PCIE_FC_CREDIT 0x73c
  45. #define PCIE_FC_CREDIT_MASK (GENMASK(31, 31) | GENMASK(28, 16))
  46. #define PCIE_FC_CREDIT_VAL(x) ((x) << 16)
  47. struct mtk_pcie_port {
  48. void __iomem *base;
  49. struct list_head list;
  50. struct mtk_pcie *pcie;
  51. struct reset_ctl reset;
  52. struct clk sys_ck;
  53. struct phy phy;
  54. u32 slot;
  55. };
  56. struct mtk_pcie {
  57. void __iomem *base;
  58. struct clk free_ck;
  59. struct list_head ports;
  60. };
  61. static int mtk_pcie_config_address(const struct udevice *udev, pci_dev_t bdf,
  62. uint offset, void **paddress)
  63. {
  64. struct mtk_pcie *pcie = dev_get_priv(udev);
  65. writel(PCIE_CONF_ADDR(offset, bdf), pcie->base + PCIE_CFG_ADDR);
  66. *paddress = pcie->base + PCIE_CFG_DATA + (offset & 3);
  67. return 0;
  68. }
  69. static int mtk_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
  70. uint offset, ulong *valuep,
  71. enum pci_size_t size)
  72. {
  73. return pci_generic_mmap_read_config(bus, mtk_pcie_config_address,
  74. bdf, offset, valuep, size);
  75. }
  76. static int mtk_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
  77. uint offset, ulong value,
  78. enum pci_size_t size)
  79. {
  80. return pci_generic_mmap_write_config(bus, mtk_pcie_config_address,
  81. bdf, offset, value, size);
  82. }
  83. static const struct dm_pci_ops mtk_pcie_ops = {
  84. .read_config = mtk_pcie_read_config,
  85. .write_config = mtk_pcie_write_config,
  86. };
  87. static void mtk_pcie_port_free(struct mtk_pcie_port *port)
  88. {
  89. list_del(&port->list);
  90. free(port);
  91. }
  92. static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
  93. {
  94. struct mtk_pcie *pcie = port->pcie;
  95. u32 slot = PCI_DEV(port->slot << 11);
  96. u32 val;
  97. int err;
  98. /* assert port PERST_N */
  99. setbits_le32(pcie->base + PCIE_SYS_CFG, PCIE_PORT_PERST(port->slot));
  100. /* de-assert port PERST_N */
  101. clrbits_le32(pcie->base + PCIE_SYS_CFG, PCIE_PORT_PERST(port->slot));
  102. /* 100ms timeout value should be enough for Gen1/2 training */
  103. err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val,
  104. !!(val & PCIE_PORT_LINKUP), 100000);
  105. if (err)
  106. return -ETIMEDOUT;
  107. /* disable interrupt */
  108. clrbits_le32(pcie->base + PCIE_INT_ENABLE,
  109. PCIE_PORT_INT_EN(port->slot));
  110. /* map to all DDR region. We need to set it before cfg operation. */
  111. writel(PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
  112. port->base + PCIE_BAR0_SETUP);
  113. /* configure class code and revision ID */
  114. writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS);
  115. /* configure FC credit */
  116. writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, slot),
  117. pcie->base + PCIE_CFG_ADDR);
  118. clrsetbits_le32(pcie->base + PCIE_CFG_DATA, PCIE_FC_CREDIT_MASK,
  119. PCIE_FC_CREDIT_VAL(0x806c));
  120. /* configure RC FTS number to 250 when it leaves L0s */
  121. writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, slot), pcie->base + PCIE_CFG_ADDR);
  122. clrsetbits_le32(pcie->base + PCIE_CFG_DATA, PCIE_FTS_NUM_MASK,
  123. PCIE_FTS_NUM_L0(0x50));
  124. return 0;
  125. }
  126. static void mtk_pcie_enable_port(struct mtk_pcie_port *port)
  127. {
  128. int err;
  129. err = clk_enable(&port->sys_ck);
  130. if (err)
  131. goto exit;
  132. err = reset_assert(&port->reset);
  133. if (err)
  134. goto exit;
  135. err = reset_deassert(&port->reset);
  136. if (err)
  137. goto exit;
  138. err = generic_phy_init(&port->phy);
  139. if (err)
  140. goto exit;
  141. err = generic_phy_power_on(&port->phy);
  142. if (err)
  143. goto exit;
  144. if (!mtk_pcie_startup_port(port))
  145. return;
  146. pr_err("Port%d link down\n", port->slot);
  147. exit:
  148. mtk_pcie_port_free(port);
  149. }
  150. static int mtk_pcie_parse_port(struct udevice *dev, u32 slot)
  151. {
  152. struct mtk_pcie *pcie = dev_get_priv(dev);
  153. struct mtk_pcie_port *port;
  154. char name[10];
  155. int err;
  156. port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
  157. if (!port)
  158. return -ENOMEM;
  159. snprintf(name, sizeof(name), "port%d", slot);
  160. port->base = dev_remap_addr_name(dev, name);
  161. if (!port->base)
  162. return -ENOENT;
  163. snprintf(name, sizeof(name), "sys_ck%d", slot);
  164. err = clk_get_by_name(dev, name, &port->sys_ck);
  165. if (err)
  166. return err;
  167. err = reset_get_by_index(dev, slot, &port->reset);
  168. if (err)
  169. return err;
  170. err = generic_phy_get_by_index(dev, slot, &port->phy);
  171. if (err)
  172. return err;
  173. port->slot = slot;
  174. port->pcie = pcie;
  175. INIT_LIST_HEAD(&port->list);
  176. list_add_tail(&port->list, &pcie->ports);
  177. return 0;
  178. }
  179. static int mtk_pcie_probe(struct udevice *dev)
  180. {
  181. struct mtk_pcie *pcie = dev_get_priv(dev);
  182. struct mtk_pcie_port *port, *tmp;
  183. ofnode subnode;
  184. int err;
  185. INIT_LIST_HEAD(&pcie->ports);
  186. pcie->base = dev_remap_addr_name(dev, "subsys");
  187. if (!pcie->base)
  188. return -ENOENT;
  189. err = clk_get_by_name(dev, "free_ck", &pcie->free_ck);
  190. if (err)
  191. return err;
  192. /* enable top level clock */
  193. err = clk_enable(&pcie->free_ck);
  194. if (err)
  195. return err;
  196. dev_for_each_subnode(subnode, dev) {
  197. struct fdt_pci_addr addr;
  198. u32 slot = 0;
  199. if (!ofnode_is_available(subnode))
  200. continue;
  201. err = ofnode_read_pci_addr(subnode, 0, "reg", &addr);
  202. if (err)
  203. return err;
  204. slot = PCI_DEV(addr.phys_hi);
  205. err = mtk_pcie_parse_port(dev, slot);
  206. if (err)
  207. return err;
  208. }
  209. /* enable each port, and then check link status */
  210. list_for_each_entry_safe(port, tmp, &pcie->ports, list)
  211. mtk_pcie_enable_port(port);
  212. return 0;
  213. }
  214. static const struct udevice_id mtk_pcie_ids[] = {
  215. { .compatible = "mediatek,mt7623-pcie", },
  216. { }
  217. };
  218. U_BOOT_DRIVER(pcie_mediatek) = {
  219. .name = "pcie_mediatek",
  220. .id = UCLASS_PCI,
  221. .of_match = mtk_pcie_ids,
  222. .ops = &mtk_pcie_ops,
  223. .probe = mtk_pcie_probe,
  224. .priv_auto_alloc_size = sizeof(struct mtk_pcie),
  225. };