pcie_layerscape_gen4_fixup.c 6.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * Copyright 2018-2020 NXP
  4. *
  5. * PCIe Gen4 driver for NXP Layerscape SoCs
  6. * Author: Hou Zhiqiang <Minder.Hou@gmail.com>
  7. *
  8. */
  9. #include <common.h>
  10. #include <pci.h>
  11. #include <asm/arch/fsl_serdes.h>
  12. #include <asm/io.h>
  13. #include <errno.h>
  14. #ifdef CONFIG_OF_BOARD_SETUP
  15. #include <linux/libfdt.h>
  16. #include <fdt_support.h>
  17. #ifdef CONFIG_ARM
  18. #include <asm/arch/clock.h>
  19. #endif
  20. #include "pcie_layerscape_gen4.h"
  21. #include "pcie_layerscape_fixup_common.h"
  22. #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
  23. /*
  24. * Return next available LUT index.
  25. */
  26. static int ls_pcie_g4_next_lut_index(struct ls_pcie_g4 *pcie)
  27. {
  28. if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
  29. return pcie->next_lut_index++;
  30. return -ENOSPC; /* LUT is full */
  31. }
  32. /*
  33. * Program a single LUT entry
  34. */
  35. static void ls_pcie_g4_lut_set_mapping(struct ls_pcie_g4 *pcie, int index,
  36. u32 devid, u32 streamid)
  37. {
  38. /* leave mask as all zeroes, want to match all bits */
  39. lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
  40. lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
  41. }
  42. /*
  43. * An msi-map is a property to be added to the pci controller
  44. * node. It is a table, where each entry consists of 4 fields
  45. * e.g.:
  46. *
  47. * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
  48. * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
  49. */
  50. static void fdt_pcie_set_msi_map_entry_ls_gen4(void *blob,
  51. struct ls_pcie_g4 *pcie,
  52. u32 devid, u32 streamid)
  53. {
  54. u32 *prop;
  55. u32 phandle;
  56. int nodeoff;
  57. #ifdef CONFIG_FSL_PCIE_COMPAT
  58. nodeoff = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_COMPAT,
  59. pcie->ccsr_res.start);
  60. #else
  61. #error "No CONFIG_FSL_PCIE_COMPAT defined"
  62. #endif
  63. if (nodeoff < 0) {
  64. debug("%s: ERROR: failed to find pcie compatiable\n", __func__);
  65. return;
  66. }
  67. /* get phandle to MSI controller */
  68. prop = (u32 *)fdt_getprop(blob, nodeoff, "msi-parent", 0);
  69. if (!prop) {
  70. debug("\n%s: ERROR: missing msi-parent: PCIe%d\n",
  71. __func__, pcie->idx);
  72. return;
  73. }
  74. phandle = fdt32_to_cpu(*prop);
  75. /* set one msi-map row */
  76. fdt_appendprop_u32(blob, nodeoff, "msi-map", devid);
  77. fdt_appendprop_u32(blob, nodeoff, "msi-map", phandle);
  78. fdt_appendprop_u32(blob, nodeoff, "msi-map", streamid);
  79. fdt_appendprop_u32(blob, nodeoff, "msi-map", 1);
  80. }
  81. /*
  82. * An iommu-map is a property to be added to the pci controller
  83. * node. It is a table, where each entry consists of 4 fields
  84. * e.g.:
  85. *
  86. * iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
  87. * [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
  88. */
  89. static void fdt_pcie_set_iommu_map_entry_ls_gen4(void *blob,
  90. struct ls_pcie_g4 *pcie,
  91. u32 devid, u32 streamid)
  92. {
  93. u32 *prop;
  94. u32 iommu_map[4];
  95. int nodeoff;
  96. int lenp;
  97. #ifdef CONFIG_FSL_PCIE_COMPAT
  98. nodeoff = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_COMPAT,
  99. pcie->ccsr_res.start);
  100. #else
  101. #error "No CONFIG_FSL_PCIE_COMPAT defined"
  102. #endif
  103. if (nodeoff < 0) {
  104. debug("%s: ERROR: failed to find pcie compatiable\n", __func__);
  105. return;
  106. }
  107. /* get phandle to iommu controller */
  108. prop = fdt_getprop_w(blob, nodeoff, "iommu-map", &lenp);
  109. if (!prop) {
  110. debug("\n%s: ERROR: missing iommu-map: PCIe%d\n",
  111. __func__, pcie->idx);
  112. return;
  113. }
  114. /* set iommu-map row */
  115. iommu_map[0] = cpu_to_fdt32(devid);
  116. iommu_map[1] = *++prop;
  117. iommu_map[2] = cpu_to_fdt32(streamid);
  118. iommu_map[3] = cpu_to_fdt32(1);
  119. if (devid == 0)
  120. fdt_setprop_inplace(blob, nodeoff, "iommu-map", iommu_map, 16);
  121. else
  122. fdt_appendprop(blob, nodeoff, "iommu-map", iommu_map, 16);
  123. }
  124. static void fdt_fixup_pcie_ls_gen4(void *blob)
  125. {
  126. struct udevice *dev, *bus;
  127. struct ls_pcie_g4 *pcie;
  128. int streamid;
  129. int index;
  130. pci_dev_t bdf;
  131. /* Scan all known buses */
  132. for (pci_find_first_device(&dev); dev; pci_find_next_device(&dev)) {
  133. for (bus = dev; device_is_on_pci_bus(bus);)
  134. bus = bus->parent;
  135. pcie = dev_get_priv(bus);
  136. streamid = pcie_next_streamid(pcie->stream_id_cur, pcie->idx);
  137. if (streamid < 0) {
  138. debug("ERROR: no stream ids free\n");
  139. continue;
  140. } else {
  141. pcie->stream_id_cur++;
  142. }
  143. index = ls_pcie_g4_next_lut_index(pcie);
  144. if (index < 0) {
  145. debug("ERROR: no LUT indexes free\n");
  146. continue;
  147. }
  148. /* the DT fixup must be relative to the hose first_busno */
  149. bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
  150. /* map PCI b.d.f to streamID in LUT */
  151. ls_pcie_g4_lut_set_mapping(pcie, index, bdf >> 8, streamid);
  152. /* update msi-map in device tree */
  153. fdt_pcie_set_msi_map_entry_ls_gen4(blob, pcie, bdf >> 8,
  154. streamid);
  155. /* update iommu-map in device tree */
  156. fdt_pcie_set_iommu_map_entry_ls_gen4(blob, pcie, bdf >> 8,
  157. streamid);
  158. }
  159. }
  160. #endif
  161. static void ft_pcie_ep_layerscape_gen4_fix(void *blob, struct ls_pcie_g4 *pcie)
  162. {
  163. int off;
  164. off = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_EP_COMPAT,
  165. pcie->ccsr_res.start);
  166. if (off < 0) {
  167. debug("%s: ERROR: failed to find pcie compatiable\n",
  168. __func__);
  169. return;
  170. }
  171. if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL)
  172. fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
  173. else
  174. fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
  175. }
  176. static void ft_pcie_rc_layerscape_gen4_fix(void *blob, struct ls_pcie_g4 *pcie)
  177. {
  178. int off;
  179. #ifdef CONFIG_FSL_PCIE_COMPAT
  180. off = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_COMPAT,
  181. pcie->ccsr_res.start);
  182. #else
  183. #error "No CONFIG_FSL_PCIE_COMPAT defined"
  184. #endif
  185. if (off < 0) {
  186. debug("%s: ERROR: failed to find pcie compatiable\n", __func__);
  187. return;
  188. }
  189. if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
  190. fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
  191. else
  192. fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
  193. }
  194. static void ft_pcie_layerscape_gen4_setup(void *blob, struct ls_pcie_g4 *pcie)
  195. {
  196. ft_pcie_rc_layerscape_gen4_fix(blob, pcie);
  197. ft_pcie_ep_layerscape_gen4_fix(blob, pcie);
  198. }
  199. /* Fixup Kernel DT for PCIe */
  200. void ft_pci_setup_ls_gen4(void *blob, bd_t *bd)
  201. {
  202. struct ls_pcie_g4 *pcie;
  203. list_for_each_entry(pcie, &ls_pcie_g4_list, list)
  204. ft_pcie_layerscape_gen4_setup(blob, pcie);
  205. #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
  206. fdt_fixup_pcie_ls_gen4(blob);
  207. #endif
  208. }
  209. #else /* !CONFIG_OF_BOARD_SETUP */
  210. void ft_pci_setup_ls_gen4(void *blob, bd_t *bd)
  211. {
  212. }
  213. #endif