pcie_layerscape.c 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2017-2019 NXP
  4. * Copyright 2014-2015 Freescale Semiconductor, Inc.
  5. * Layerscape PCIe driver
  6. */
  7. #include <common.h>
  8. #include <asm/arch/fsl_serdes.h>
  9. #include <pci.h>
  10. #include <asm/io.h>
  11. #include <errno.h>
  12. #include <malloc.h>
  13. #include <dm.h>
  14. #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
  15. defined(CONFIG_ARM)
  16. #include <asm/arch/clock.h>
  17. #endif
  18. #include "pcie_layerscape.h"
  19. DECLARE_GLOBAL_DATA_PTR;
  20. LIST_HEAD(ls_pcie_list);
  21. static unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset)
  22. {
  23. return in_le32(pcie->dbi + offset);
  24. }
  25. static void dbi_writel(struct ls_pcie *pcie, unsigned int value,
  26. unsigned int offset)
  27. {
  28. out_le32(pcie->dbi + offset, value);
  29. }
  30. static unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset)
  31. {
  32. if (pcie->big_endian)
  33. return in_be32(pcie->ctrl + offset);
  34. else
  35. return in_le32(pcie->ctrl + offset);
  36. }
  37. static void ctrl_writel(struct ls_pcie *pcie, unsigned int value,
  38. unsigned int offset)
  39. {
  40. if (pcie->big_endian)
  41. out_be32(pcie->ctrl + offset, value);
  42. else
  43. out_le32(pcie->ctrl + offset, value);
  44. }
  45. static int ls_pcie_ltssm(struct ls_pcie *pcie)
  46. {
  47. u32 state;
  48. uint svr;
  49. svr = get_svr();
  50. if (((svr >> SVR_VAR_PER_SHIFT) & SVR_LS102XA_MASK) == SVR_LS102XA) {
  51. state = ctrl_readl(pcie, LS1021_PEXMSCPORTSR(pcie->idx));
  52. state = (state >> LS1021_LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
  53. } else {
  54. state = ctrl_readl(pcie, PCIE_PF_DBG) & LTSSM_STATE_MASK;
  55. }
  56. return state;
  57. }
  58. static int ls_pcie_link_up(struct ls_pcie *pcie)
  59. {
  60. int ltssm;
  61. ltssm = ls_pcie_ltssm(pcie);
  62. if (ltssm < LTSSM_PCIE_L0)
  63. return 0;
  64. return 1;
  65. }
  66. static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev)
  67. {
  68. dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
  69. PCIE_ATU_VIEWPORT);
  70. dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET);
  71. }
  72. static void ls_pcie_cfg1_set_busdev(struct ls_pcie *pcie, u32 busdev)
  73. {
  74. dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
  75. PCIE_ATU_VIEWPORT);
  76. dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET);
  77. }
  78. static void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
  79. u64 phys, u64 bus_addr, pci_size_t size)
  80. {
  81. dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | idx, PCIE_ATU_VIEWPORT);
  82. dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_BASE);
  83. dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_BASE);
  84. dbi_writel(pcie, (u32)phys + size - 1, PCIE_ATU_LIMIT);
  85. dbi_writel(pcie, (u32)bus_addr, PCIE_ATU_LOWER_TARGET);
  86. dbi_writel(pcie, bus_addr >> 32, PCIE_ATU_UPPER_TARGET);
  87. dbi_writel(pcie, type, PCIE_ATU_CR1);
  88. dbi_writel(pcie, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
  89. }
  90. /* Use bar match mode and MEM type as default */
  91. static void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, int idx,
  92. int bar, u64 phys)
  93. {
  94. dbi_writel(pcie, PCIE_ATU_REGION_INBOUND | idx, PCIE_ATU_VIEWPORT);
  95. dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_TARGET);
  96. dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_TARGET);
  97. dbi_writel(pcie, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
  98. dbi_writel(pcie, PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE |
  99. PCIE_ATU_BAR_NUM(bar), PCIE_ATU_CR2);
  100. }
  101. static void ls_pcie_dump_atu(struct ls_pcie *pcie)
  102. {
  103. int i;
  104. for (i = 0; i < PCIE_ATU_REGION_NUM; i++) {
  105. dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | i,
  106. PCIE_ATU_VIEWPORT);
  107. debug("iATU%d:\n", i);
  108. debug("\tLOWER PHYS 0x%08x\n",
  109. dbi_readl(pcie, PCIE_ATU_LOWER_BASE));
  110. debug("\tUPPER PHYS 0x%08x\n",
  111. dbi_readl(pcie, PCIE_ATU_UPPER_BASE));
  112. debug("\tLOWER BUS 0x%08x\n",
  113. dbi_readl(pcie, PCIE_ATU_LOWER_TARGET));
  114. debug("\tUPPER BUS 0x%08x\n",
  115. dbi_readl(pcie, PCIE_ATU_UPPER_TARGET));
  116. debug("\tLIMIT 0x%08x\n",
  117. readl(pcie->dbi + PCIE_ATU_LIMIT));
  118. debug("\tCR1 0x%08x\n",
  119. dbi_readl(pcie, PCIE_ATU_CR1));
  120. debug("\tCR2 0x%08x\n",
  121. dbi_readl(pcie, PCIE_ATU_CR2));
  122. }
  123. }
  124. static void ls_pcie_setup_atu(struct ls_pcie *pcie)
  125. {
  126. struct pci_region *io, *mem, *pref;
  127. unsigned long long offset = 0;
  128. int idx = 0;
  129. uint svr;
  130. svr = get_svr();
  131. if (((svr >> SVR_VAR_PER_SHIFT) & SVR_LS102XA_MASK) == SVR_LS102XA) {
  132. offset = LS1021_PCIE_SPACE_OFFSET +
  133. LS1021_PCIE_SPACE_SIZE * pcie->idx;
  134. }
  135. /* ATU 0 : OUTBOUND : CFG0 */
  136. ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0,
  137. PCIE_ATU_TYPE_CFG0,
  138. pcie->cfg_res.start + offset,
  139. 0,
  140. fdt_resource_size(&pcie->cfg_res) / 2);
  141. /* ATU 1 : OUTBOUND : CFG1 */
  142. ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1,
  143. PCIE_ATU_TYPE_CFG1,
  144. pcie->cfg_res.start + offset +
  145. fdt_resource_size(&pcie->cfg_res) / 2,
  146. 0,
  147. fdt_resource_size(&pcie->cfg_res) / 2);
  148. pci_get_regions(pcie->bus, &io, &mem, &pref);
  149. idx = PCIE_ATU_REGION_INDEX1 + 1;
  150. /* Fix the pcie memory map for LS2088A series SoCs */
  151. svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
  152. if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
  153. svr == SVR_LS2048A || svr == SVR_LS2044A ||
  154. svr == SVR_LS2081A || svr == SVR_LS2041A) {
  155. if (io)
  156. io->phys_start = (io->phys_start &
  157. (PCIE_PHYS_SIZE - 1)) +
  158. LS2088A_PCIE1_PHYS_ADDR +
  159. LS2088A_PCIE_PHYS_SIZE * pcie->idx;
  160. if (mem)
  161. mem->phys_start = (mem->phys_start &
  162. (PCIE_PHYS_SIZE - 1)) +
  163. LS2088A_PCIE1_PHYS_ADDR +
  164. LS2088A_PCIE_PHYS_SIZE * pcie->idx;
  165. if (pref)
  166. pref->phys_start = (pref->phys_start &
  167. (PCIE_PHYS_SIZE - 1)) +
  168. LS2088A_PCIE1_PHYS_ADDR +
  169. LS2088A_PCIE_PHYS_SIZE * pcie->idx;
  170. }
  171. if (io)
  172. /* ATU : OUTBOUND : IO */
  173. ls_pcie_atu_outbound_set(pcie, idx++,
  174. PCIE_ATU_TYPE_IO,
  175. io->phys_start + offset,
  176. io->bus_start,
  177. io->size);
  178. if (mem)
  179. /* ATU : OUTBOUND : MEM */
  180. ls_pcie_atu_outbound_set(pcie, idx++,
  181. PCIE_ATU_TYPE_MEM,
  182. mem->phys_start + offset,
  183. mem->bus_start,
  184. mem->size);
  185. if (pref)
  186. /* ATU : OUTBOUND : pref */
  187. ls_pcie_atu_outbound_set(pcie, idx++,
  188. PCIE_ATU_TYPE_MEM,
  189. pref->phys_start + offset,
  190. pref->bus_start,
  191. pref->size);
  192. ls_pcie_dump_atu(pcie);
  193. }
  194. /* Return 0 if the address is valid, -errno if not valid */
  195. static int ls_pcie_addr_valid(struct ls_pcie *pcie, pci_dev_t bdf)
  196. {
  197. struct udevice *bus = pcie->bus;
  198. if (pcie->mode == PCI_HEADER_TYPE_NORMAL)
  199. return -ENODEV;
  200. if (!pcie->enabled)
  201. return -ENXIO;
  202. if (PCI_BUS(bdf) < bus->seq)
  203. return -EINVAL;
  204. if ((PCI_BUS(bdf) > bus->seq) && (!ls_pcie_link_up(pcie)))
  205. return -EINVAL;
  206. if (PCI_BUS(bdf) <= (bus->seq + 1) && (PCI_DEV(bdf) > 0))
  207. return -EINVAL;
  208. return 0;
  209. }
  210. int ls_pcie_conf_address(const struct udevice *bus, pci_dev_t bdf,
  211. uint offset, void **paddress)
  212. {
  213. struct ls_pcie *pcie = dev_get_priv(bus);
  214. u32 busdev;
  215. if (ls_pcie_addr_valid(pcie, bdf))
  216. return -EINVAL;
  217. if (PCI_BUS(bdf) == bus->seq) {
  218. *paddress = pcie->dbi + offset;
  219. return 0;
  220. }
  221. busdev = PCIE_ATU_BUS(PCI_BUS(bdf) - bus->seq) |
  222. PCIE_ATU_DEV(PCI_DEV(bdf)) |
  223. PCIE_ATU_FUNC(PCI_FUNC(bdf));
  224. if (PCI_BUS(bdf) == bus->seq + 1) {
  225. ls_pcie_cfg0_set_busdev(pcie, busdev);
  226. *paddress = pcie->cfg0 + offset;
  227. } else {
  228. ls_pcie_cfg1_set_busdev(pcie, busdev);
  229. *paddress = pcie->cfg1 + offset;
  230. }
  231. return 0;
  232. }
  233. static int ls_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
  234. uint offset, ulong *valuep,
  235. enum pci_size_t size)
  236. {
  237. return pci_generic_mmap_read_config(bus, ls_pcie_conf_address,
  238. bdf, offset, valuep, size);
  239. }
  240. static int ls_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
  241. uint offset, ulong value,
  242. enum pci_size_t size)
  243. {
  244. return pci_generic_mmap_write_config(bus, ls_pcie_conf_address,
  245. bdf, offset, value, size);
  246. }
  247. /* Clear multi-function bit */
  248. static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
  249. {
  250. writeb(PCI_HEADER_TYPE_BRIDGE, pcie->dbi + PCI_HEADER_TYPE);
  251. }
  252. /* Fix class value */
  253. static void ls_pcie_fix_class(struct ls_pcie *pcie)
  254. {
  255. writew(PCI_CLASS_BRIDGE_PCI, pcie->dbi + PCI_CLASS_DEVICE);
  256. }
  257. /* Drop MSG TLP except for Vendor MSG */
  258. static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
  259. {
  260. u32 val;
  261. val = dbi_readl(pcie, PCIE_STRFMR1);
  262. val &= 0xDFFFFFFF;
  263. dbi_writel(pcie, val, PCIE_STRFMR1);
  264. }
  265. /* Disable all bars in RC mode */
  266. static void ls_pcie_disable_bars(struct ls_pcie *pcie)
  267. {
  268. dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_0);
  269. dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_1);
  270. dbi_writel(pcie, 0xfffffffe, PCIE_CS2_OFFSET + PCI_ROM_ADDRESS1);
  271. }
  272. static void ls_pcie_setup_ctrl(struct ls_pcie *pcie)
  273. {
  274. ls_pcie_setup_atu(pcie);
  275. dbi_writel(pcie, 1, PCIE_DBI_RO_WR_EN);
  276. ls_pcie_fix_class(pcie);
  277. ls_pcie_clear_multifunction(pcie);
  278. ls_pcie_drop_msg_tlp(pcie);
  279. dbi_writel(pcie, 0, PCIE_DBI_RO_WR_EN);
  280. ls_pcie_disable_bars(pcie);
  281. pcie->stream_id_cur = 0;
  282. }
  283. static void ls_pcie_ep_setup_atu(struct ls_pcie *pcie)
  284. {
  285. u64 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE;
  286. /* ATU 0 : INBOUND : map BAR0 */
  287. ls_pcie_atu_inbound_set(pcie, 0, 0, phys);
  288. /* ATU 1 : INBOUND : map BAR1 */
  289. phys += PCIE_BAR1_SIZE;
  290. ls_pcie_atu_inbound_set(pcie, 1, 1, phys);
  291. /* ATU 2 : INBOUND : map BAR2 */
  292. phys += PCIE_BAR2_SIZE;
  293. ls_pcie_atu_inbound_set(pcie, 2, 2, phys);
  294. /* ATU 3 : INBOUND : map BAR4 */
  295. phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR4_SIZE;
  296. ls_pcie_atu_inbound_set(pcie, 3, 4, phys);
  297. /* ATU 0 : OUTBOUND : map MEM */
  298. ls_pcie_atu_outbound_set(pcie, 0,
  299. PCIE_ATU_TYPE_MEM,
  300. pcie->cfg_res.start,
  301. 0,
  302. CONFIG_SYS_PCI_MEMORY_SIZE);
  303. }
  304. /* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */
  305. static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size)
  306. {
  307. /* The least inbound window is 4KiB */
  308. if (size < 4 * 1024)
  309. return;
  310. switch (bar) {
  311. case 0:
  312. writel(size - 1, bar_base + PCI_BASE_ADDRESS_0);
  313. break;
  314. case 1:
  315. writel(size - 1, bar_base + PCI_BASE_ADDRESS_1);
  316. break;
  317. case 2:
  318. writel(size - 1, bar_base + PCI_BASE_ADDRESS_2);
  319. writel(0, bar_base + PCI_BASE_ADDRESS_3);
  320. break;
  321. case 4:
  322. writel(size - 1, bar_base + PCI_BASE_ADDRESS_4);
  323. writel(0, bar_base + PCI_BASE_ADDRESS_5);
  324. break;
  325. default:
  326. break;
  327. }
  328. }
  329. static void ls_pcie_ep_setup_bars(void *bar_base)
  330. {
  331. /* BAR0 - 32bit - 4K configuration */
  332. ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE);
  333. /* BAR1 - 32bit - 8K MSIX*/
  334. ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE);
  335. /* BAR2 - 64bit - 4K MEM desciptor */
  336. ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE);
  337. /* BAR4 - 64bit - 1M MEM*/
  338. ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE);
  339. }
  340. static void ls_pcie_ep_enable_cfg(struct ls_pcie *pcie)
  341. {
  342. u32 config;
  343. config = ctrl_readl(pcie, PCIE_PF_CONFIG);
  344. config |= PCIE_CONFIG_READY;
  345. ctrl_writel(pcie, config, PCIE_PF_CONFIG);
  346. }
  347. static void ls_pcie_setup_ep(struct ls_pcie *pcie)
  348. {
  349. u32 sriov;
  350. sriov = readl(pcie->dbi + PCIE_SRIOV);
  351. if (PCI_EXT_CAP_ID(sriov) == PCI_EXT_CAP_ID_SRIOV) {
  352. int pf, vf;
  353. for (pf = 0; pf < PCIE_PF_NUM; pf++) {
  354. for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
  355. ctrl_writel(pcie, PCIE_LCTRL0_VAL(pf, vf),
  356. PCIE_PF_VF_CTRL);
  357. ls_pcie_ep_setup_bars(pcie->dbi);
  358. ls_pcie_ep_setup_atu(pcie);
  359. }
  360. }
  361. /* Disable CFG2 */
  362. ctrl_writel(pcie, 0, PCIE_PF_VF_CTRL);
  363. } else {
  364. ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE);
  365. ls_pcie_ep_setup_atu(pcie);
  366. }
  367. ls_pcie_ep_enable_cfg(pcie);
  368. }
  369. static int ls_pcie_probe(struct udevice *dev)
  370. {
  371. struct ls_pcie *pcie = dev_get_priv(dev);
  372. const void *fdt = gd->fdt_blob;
  373. int node = dev_of_offset(dev);
  374. u16 link_sta;
  375. uint svr;
  376. int ret;
  377. fdt_size_t cfg_size;
  378. pcie->bus = dev;
  379. ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
  380. "dbi", &pcie->dbi_res);
  381. if (ret) {
  382. printf("ls-pcie: resource \"dbi\" not found\n");
  383. return ret;
  384. }
  385. pcie->idx = (pcie->dbi_res.start - PCIE_SYS_BASE_ADDR) / PCIE_CCSR_SIZE;
  386. list_add(&pcie->list, &ls_pcie_list);
  387. pcie->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx));
  388. if (!pcie->enabled) {
  389. printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
  390. return 0;
  391. }
  392. pcie->dbi = map_physmem(pcie->dbi_res.start,
  393. fdt_resource_size(&pcie->dbi_res),
  394. MAP_NOCACHE);
  395. ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
  396. "lut", &pcie->lut_res);
  397. if (!ret)
  398. pcie->lut = map_physmem(pcie->lut_res.start,
  399. fdt_resource_size(&pcie->lut_res),
  400. MAP_NOCACHE);
  401. ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
  402. "ctrl", &pcie->ctrl_res);
  403. if (!ret)
  404. pcie->ctrl = map_physmem(pcie->ctrl_res.start,
  405. fdt_resource_size(&pcie->ctrl_res),
  406. MAP_NOCACHE);
  407. if (!pcie->ctrl)
  408. pcie->ctrl = pcie->lut;
  409. if (!pcie->ctrl) {
  410. printf("%s: NOT find CTRL\n", dev->name);
  411. return -1;
  412. }
  413. ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
  414. "config", &pcie->cfg_res);
  415. if (ret) {
  416. printf("%s: resource \"config\" not found\n", dev->name);
  417. return ret;
  418. }
  419. /*
  420. * Fix the pcie memory map address and PF control registers address
  421. * for LS2088A series SoCs
  422. */
  423. svr = get_svr();
  424. svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
  425. if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
  426. svr == SVR_LS2048A || svr == SVR_LS2044A ||
  427. svr == SVR_LS2081A || svr == SVR_LS2041A) {
  428. cfg_size = fdt_resource_size(&pcie->cfg_res);
  429. pcie->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
  430. LS2088A_PCIE_PHYS_SIZE * pcie->idx;
  431. pcie->cfg_res.end = pcie->cfg_res.start + cfg_size;
  432. pcie->ctrl = pcie->lut + 0x40000;
  433. }
  434. pcie->cfg0 = map_physmem(pcie->cfg_res.start,
  435. fdt_resource_size(&pcie->cfg_res),
  436. MAP_NOCACHE);
  437. pcie->cfg1 = pcie->cfg0 + fdt_resource_size(&pcie->cfg_res) / 2;
  438. pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian");
  439. debug("%s dbi:%lx lut:%lx ctrl:0x%lx cfg0:0x%lx, big-endian:%d\n",
  440. dev->name, (unsigned long)pcie->dbi, (unsigned long)pcie->lut,
  441. (unsigned long)pcie->ctrl, (unsigned long)pcie->cfg0,
  442. pcie->big_endian);
  443. pcie->mode = readb(pcie->dbi + PCI_HEADER_TYPE) & 0x7f;
  444. if (pcie->mode == PCI_HEADER_TYPE_NORMAL) {
  445. printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint");
  446. ls_pcie_setup_ep(pcie);
  447. } else {
  448. printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex");
  449. ls_pcie_setup_ctrl(pcie);
  450. }
  451. if (!ls_pcie_link_up(pcie)) {
  452. /* Let the user know there's no PCIe link */
  453. printf(": no link\n");
  454. return 0;
  455. }
  456. /* Print the negotiated PCIe link width */
  457. link_sta = readw(pcie->dbi + PCIE_LINK_STA);
  458. printf(": x%d gen%d\n", (link_sta & PCIE_LINK_WIDTH_MASK) >> 4,
  459. link_sta & PCIE_LINK_SPEED_MASK);
  460. return 0;
  461. }
  462. static const struct dm_pci_ops ls_pcie_ops = {
  463. .read_config = ls_pcie_read_config,
  464. .write_config = ls_pcie_write_config,
  465. };
  466. static const struct udevice_id ls_pcie_ids[] = {
  467. { .compatible = "fsl,ls-pcie" },
  468. { }
  469. };
  470. U_BOOT_DRIVER(pci_layerscape) = {
  471. .name = "pci_layerscape",
  472. .id = UCLASS_PCI,
  473. .of_match = ls_pcie_ids,
  474. .ops = &ls_pcie_ops,
  475. .probe = ls_pcie_probe,
  476. .priv_auto_alloc_size = sizeof(struct ls_pcie),
  477. };