pcie_imx.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Freescale i.MX6 PCI Express Root-Complex driver
  4. *
  5. * Copyright (C) 2013 Marek Vasut <marex@denx.de>
  6. *
  7. * Based on upstream Linux kernel driver:
  8. * pci-imx6.c: Sean Cross <xobs@kosagi.com>
  9. * pcie-designware.c: Jingoo Han <jg1.han@samsung.com>
  10. */
  11. #include <common.h>
  12. #include <init.h>
  13. #include <malloc.h>
  14. #include <pci.h>
  15. #include <asm/arch/clock.h>
  16. #include <asm/arch/iomux.h>
  17. #include <asm/arch/crm_regs.h>
  18. #include <asm/gpio.h>
  19. #include <asm/io.h>
  20. #include <dm.h>
  21. #include <linux/sizes.h>
  22. #include <errno.h>
  23. #include <asm/arch/sys_proto.h>
  24. #define PCI_ACCESS_READ 0
  25. #define PCI_ACCESS_WRITE 1
  26. #ifdef CONFIG_MX6SX
  27. #define MX6_DBI_ADDR 0x08ffc000
  28. #define MX6_IO_ADDR 0x08000000
  29. #define MX6_MEM_ADDR 0x08100000
  30. #define MX6_ROOT_ADDR 0x08f00000
  31. #else
  32. #define MX6_DBI_ADDR 0x01ffc000
  33. #define MX6_IO_ADDR 0x01000000
  34. #define MX6_MEM_ADDR 0x01100000
  35. #define MX6_ROOT_ADDR 0x01f00000
  36. #endif
  37. #define MX6_DBI_SIZE 0x4000
  38. #define MX6_IO_SIZE 0x100000
  39. #define MX6_MEM_SIZE 0xe00000
  40. #define MX6_ROOT_SIZE 0xfc000
  41. /* PCIe Port Logic registers (memory-mapped) */
  42. #define PL_OFFSET 0x700
  43. #define PCIE_PL_PFLR (PL_OFFSET + 0x08)
  44. #define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16)
  45. #define PCIE_PL_PFLR_FORCE_LINK (1 << 15)
  46. #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
  47. #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
  48. #define PCIE_PHY_DEBUG_R1_LINK_UP (1 << 4)
  49. #define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (1 << 29)
  50. #define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
  51. #define PCIE_PHY_CTRL_DATA_LOC 0
  52. #define PCIE_PHY_CTRL_CAP_ADR_LOC 16
  53. #define PCIE_PHY_CTRL_CAP_DAT_LOC 17
  54. #define PCIE_PHY_CTRL_WR_LOC 18
  55. #define PCIE_PHY_CTRL_RD_LOC 19
  56. #define PCIE_PHY_STAT (PL_OFFSET + 0x110)
  57. #define PCIE_PHY_STAT_DATA_LOC 0
  58. #define PCIE_PHY_STAT_ACK_LOC 16
  59. /* PHY registers (not memory-mapped) */
  60. #define PCIE_PHY_RX_ASIC_OUT 0x100D
  61. #define PHY_RX_OVRD_IN_LO 0x1005
  62. #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
  63. #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
  64. #define PCIE_PHY_PUP_REQ (1 << 7)
  65. /* iATU registers */
  66. #define PCIE_ATU_VIEWPORT 0x900
  67. #define PCIE_ATU_REGION_INBOUND (0x1 << 31)
  68. #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
  69. #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
  70. #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
  71. #define PCIE_ATU_CR1 0x904
  72. #define PCIE_ATU_TYPE_MEM (0x0 << 0)
  73. #define PCIE_ATU_TYPE_IO (0x2 << 0)
  74. #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
  75. #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
  76. #define PCIE_ATU_CR2 0x908
  77. #define PCIE_ATU_ENABLE (0x1 << 31)
  78. #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
  79. #define PCIE_ATU_LOWER_BASE 0x90C
  80. #define PCIE_ATU_UPPER_BASE 0x910
  81. #define PCIE_ATU_LIMIT 0x914
  82. #define PCIE_ATU_LOWER_TARGET 0x918
  83. #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
  84. #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
  85. #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
  86. #define PCIE_ATU_UPPER_TARGET 0x91C
  87. struct imx_pcie_priv {
  88. void __iomem *dbi_base;
  89. void __iomem *cfg_base;
  90. };
  91. /*
  92. * PHY access functions
  93. */
  94. static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
  95. {
  96. u32 val;
  97. u32 max_iterations = 10;
  98. u32 wait_counter = 0;
  99. do {
  100. val = readl(dbi_base + PCIE_PHY_STAT);
  101. val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
  102. wait_counter++;
  103. if (val == exp_val)
  104. return 0;
  105. udelay(1);
  106. } while (wait_counter < max_iterations);
  107. return -ETIMEDOUT;
  108. }
  109. static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
  110. {
  111. u32 val;
  112. int ret;
  113. val = addr << PCIE_PHY_CTRL_DATA_LOC;
  114. writel(val, dbi_base + PCIE_PHY_CTRL);
  115. val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
  116. writel(val, dbi_base + PCIE_PHY_CTRL);
  117. ret = pcie_phy_poll_ack(dbi_base, 1);
  118. if (ret)
  119. return ret;
  120. val = addr << PCIE_PHY_CTRL_DATA_LOC;
  121. writel(val, dbi_base + PCIE_PHY_CTRL);
  122. ret = pcie_phy_poll_ack(dbi_base, 0);
  123. if (ret)
  124. return ret;
  125. return 0;
  126. }
  127. /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
  128. static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data)
  129. {
  130. u32 val, phy_ctl;
  131. int ret;
  132. ret = pcie_phy_wait_ack(dbi_base, addr);
  133. if (ret)
  134. return ret;
  135. /* assert Read signal */
  136. phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
  137. writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);
  138. ret = pcie_phy_poll_ack(dbi_base, 1);
  139. if (ret)
  140. return ret;
  141. val = readl(dbi_base + PCIE_PHY_STAT);
  142. *data = val & 0xffff;
  143. /* deassert Read signal */
  144. writel(0x00, dbi_base + PCIE_PHY_CTRL);
  145. ret = pcie_phy_poll_ack(dbi_base, 0);
  146. if (ret)
  147. return ret;
  148. return 0;
  149. }
  150. static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
  151. {
  152. u32 var;
  153. int ret;
  154. /* write addr */
  155. /* cap addr */
  156. ret = pcie_phy_wait_ack(dbi_base, addr);
  157. if (ret)
  158. return ret;
  159. var = data << PCIE_PHY_CTRL_DATA_LOC;
  160. writel(var, dbi_base + PCIE_PHY_CTRL);
  161. /* capture data */
  162. var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
  163. writel(var, dbi_base + PCIE_PHY_CTRL);
  164. ret = pcie_phy_poll_ack(dbi_base, 1);
  165. if (ret)
  166. return ret;
  167. /* deassert cap data */
  168. var = data << PCIE_PHY_CTRL_DATA_LOC;
  169. writel(var, dbi_base + PCIE_PHY_CTRL);
  170. /* wait for ack de-assertion */
  171. ret = pcie_phy_poll_ack(dbi_base, 0);
  172. if (ret)
  173. return ret;
  174. /* assert wr signal */
  175. var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
  176. writel(var, dbi_base + PCIE_PHY_CTRL);
  177. /* wait for ack */
  178. ret = pcie_phy_poll_ack(dbi_base, 1);
  179. if (ret)
  180. return ret;
  181. /* deassert wr signal */
  182. var = data << PCIE_PHY_CTRL_DATA_LOC;
  183. writel(var, dbi_base + PCIE_PHY_CTRL);
  184. /* wait for ack de-assertion */
  185. ret = pcie_phy_poll_ack(dbi_base, 0);
  186. if (ret)
  187. return ret;
  188. writel(0x0, dbi_base + PCIE_PHY_CTRL);
  189. return 0;
  190. }
  191. static int imx6_pcie_link_up(struct imx_pcie_priv *priv)
  192. {
  193. u32 rc, ltssm;
  194. int rx_valid, temp;
  195. /* link is debug bit 36, debug register 1 starts at bit 32 */
  196. rc = readl(priv->dbi_base + PCIE_PHY_DEBUG_R1);
  197. if ((rc & PCIE_PHY_DEBUG_R1_LINK_UP) &&
  198. !(rc & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING))
  199. return -EAGAIN;
  200. /*
  201. * From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
  202. * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
  203. * If (MAC/LTSSM.state == Recovery.RcvrLock)
  204. * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
  205. * to gen2 is stuck
  206. */
  207. pcie_phy_read(priv->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
  208. ltssm = readl(priv->dbi_base + PCIE_PHY_DEBUG_R0) & 0x3F;
  209. if (rx_valid & 0x01)
  210. return 0;
  211. if (ltssm != 0x0d)
  212. return 0;
  213. printf("transition to gen2 is stuck, reset PHY!\n");
  214. pcie_phy_read(priv->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
  215. temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
  216. pcie_phy_write(priv->dbi_base, PHY_RX_OVRD_IN_LO, temp);
  217. udelay(3000);
  218. pcie_phy_read(priv->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
  219. temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
  220. pcie_phy_write(priv->dbi_base, PHY_RX_OVRD_IN_LO, temp);
  221. return 0;
  222. }
  223. /*
  224. * iATU region setup
  225. */
  226. static int imx_pcie_regions_setup(struct imx_pcie_priv *priv)
  227. {
  228. /*
  229. * i.MX6 defines 16MB in the AXI address map for PCIe.
  230. *
  231. * That address space excepted the pcie registers is
  232. * split and defined into different regions by iATU,
  233. * with sizes and offsets as follows:
  234. *
  235. * 0x0100_0000 --- 0x010F_FFFF 1MB IORESOURCE_IO
  236. * 0x0110_0000 --- 0x01EF_FFFF 14MB IORESOURCE_MEM
  237. * 0x01F0_0000 --- 0x01FF_FFFF 1MB Cfg + Registers
  238. */
  239. /* CMD reg:I/O space, MEM space, and Bus Master Enable */
  240. setbits_le32(priv->dbi_base + PCI_COMMAND,
  241. PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
  242. /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */
  243. setbits_le32(priv->dbi_base + PCI_CLASS_REVISION,
  244. PCI_CLASS_BRIDGE_PCI << 16);
  245. /* Region #0 is used for Outbound CFG space access. */
  246. writel(0, priv->dbi_base + PCIE_ATU_VIEWPORT);
  247. writel(lower_32_bits((uintptr_t)priv->cfg_base),
  248. priv->dbi_base + PCIE_ATU_LOWER_BASE);
  249. writel(upper_32_bits((uintptr_t)priv->cfg_base),
  250. priv->dbi_base + PCIE_ATU_UPPER_BASE);
  251. writel(lower_32_bits((uintptr_t)priv->cfg_base + MX6_ROOT_SIZE),
  252. priv->dbi_base + PCIE_ATU_LIMIT);
  253. writel(0, priv->dbi_base + PCIE_ATU_LOWER_TARGET);
  254. writel(0, priv->dbi_base + PCIE_ATU_UPPER_TARGET);
  255. writel(PCIE_ATU_TYPE_CFG0, priv->dbi_base + PCIE_ATU_CR1);
  256. writel(PCIE_ATU_ENABLE, priv->dbi_base + PCIE_ATU_CR2);
  257. return 0;
  258. }
  259. /*
  260. * PCI Express accessors
  261. */
  262. static void __iomem *get_bus_address(struct imx_pcie_priv *priv,
  263. pci_dev_t d, int where)
  264. {
  265. void __iomem *va_address;
  266. /* Reconfigure Region #0 */
  267. writel(0, priv->dbi_base + PCIE_ATU_VIEWPORT);
  268. if (PCI_BUS(d) < 2)
  269. writel(PCIE_ATU_TYPE_CFG0, priv->dbi_base + PCIE_ATU_CR1);
  270. else
  271. writel(PCIE_ATU_TYPE_CFG1, priv->dbi_base + PCIE_ATU_CR1);
  272. if (PCI_BUS(d) == 0) {
  273. va_address = priv->dbi_base;
  274. } else {
  275. writel(d << 8, priv->dbi_base + PCIE_ATU_LOWER_TARGET);
  276. va_address = priv->cfg_base;
  277. }
  278. va_address += (where & ~0x3);
  279. return va_address;
  280. }
  281. static int imx_pcie_addr_valid(pci_dev_t d)
  282. {
  283. if ((PCI_BUS(d) == 0) && (PCI_DEV(d) > 1))
  284. return -EINVAL;
  285. if ((PCI_BUS(d) == 1) && (PCI_DEV(d) > 0))
  286. return -EINVAL;
  287. return 0;
  288. }
  289. /*
  290. * Replace the original ARM DABT handler with a simple jump-back one.
  291. *
  292. * The problem here is that if we have a PCIe bridge attached to this PCIe
  293. * controller, but no PCIe device is connected to the bridges' downstream
  294. * port, the attempt to read/write from/to the config space will produce
  295. * a DABT. This is a behavior of the controller and can not be disabled
  296. * unfortuatelly.
  297. *
  298. * To work around the problem, we backup the current DABT handler address
  299. * and replace it with our own DABT handler, which only bounces right back
  300. * into the code.
  301. */
  302. static void imx_pcie_fix_dabt_handler(bool set)
  303. {
  304. extern uint32_t *_data_abort;
  305. uint32_t *data_abort_addr = (uint32_t *)&_data_abort;
  306. static const uint32_t data_abort_bounce_handler = 0xe25ef004;
  307. uint32_t data_abort_bounce_addr = (uint32_t)&data_abort_bounce_handler;
  308. static uint32_t data_abort_backup;
  309. if (set) {
  310. data_abort_backup = *data_abort_addr;
  311. *data_abort_addr = data_abort_bounce_addr;
  312. } else {
  313. *data_abort_addr = data_abort_backup;
  314. }
  315. }
  316. static int imx_pcie_read_cfg(struct imx_pcie_priv *priv, pci_dev_t d,
  317. int where, u32 *val)
  318. {
  319. void __iomem *va_address;
  320. int ret;
  321. ret = imx_pcie_addr_valid(d);
  322. if (ret) {
  323. *val = 0xffffffff;
  324. return 0;
  325. }
  326. va_address = get_bus_address(priv, d, where);
  327. /*
  328. * Read the PCIe config space. We must replace the DABT handler
  329. * here in case we got data abort from the PCIe controller, see
  330. * imx_pcie_fix_dabt_handler() description. Note that writing the
  331. * "val" with valid value is also imperative here as in case we
  332. * did got DABT, the val would contain random value.
  333. */
  334. imx_pcie_fix_dabt_handler(true);
  335. writel(0xffffffff, val);
  336. *val = readl(va_address);
  337. imx_pcie_fix_dabt_handler(false);
  338. return 0;
  339. }
  340. static int imx_pcie_write_cfg(struct imx_pcie_priv *priv, pci_dev_t d,
  341. int where, u32 val)
  342. {
  343. void __iomem *va_address = NULL;
  344. int ret;
  345. ret = imx_pcie_addr_valid(d);
  346. if (ret)
  347. return ret;
  348. va_address = get_bus_address(priv, d, where);
  349. /*
  350. * Write the PCIe config space. We must replace the DABT handler
  351. * here in case we got data abort from the PCIe controller, see
  352. * imx_pcie_fix_dabt_handler() description.
  353. */
  354. imx_pcie_fix_dabt_handler(true);
  355. writel(val, va_address);
  356. imx_pcie_fix_dabt_handler(false);
  357. return 0;
  358. }
  359. /*
  360. * Initial bus setup
  361. */
  362. static int imx6_pcie_assert_core_reset(struct imx_pcie_priv *priv,
  363. bool prepare_for_boot)
  364. {
  365. struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  366. if (is_mx6dqp())
  367. setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
  368. #if defined(CONFIG_MX6SX)
  369. struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
  370. /* SSP_EN is not used on MX6SX anymore */
  371. setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
  372. /* Force PCIe PHY reset */
  373. setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
  374. /* Power up PCIe PHY */
  375. setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
  376. #else
  377. /*
  378. * If the bootloader already enabled the link we need some special
  379. * handling to get the core back into a state where it is safe to
  380. * touch it for configuration. As there is no dedicated reset signal
  381. * wired up for MX6QDL, we need to manually force LTSSM into "detect"
  382. * state before completely disabling LTSSM, which is a prerequisite
  383. * for core configuration.
  384. *
  385. * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong
  386. * indication that the bootloader activated the link.
  387. */
  388. if (is_mx6dq() && prepare_for_boot) {
  389. u32 val, gpr1, gpr12;
  390. gpr1 = readl(&iomuxc_regs->gpr[1]);
  391. gpr12 = readl(&iomuxc_regs->gpr[12]);
  392. if ((gpr1 & IOMUXC_GPR1_PCIE_REF_CLK_EN) &&
  393. (gpr12 & IOMUXC_GPR12_PCIE_CTL_2)) {
  394. val = readl(priv->dbi_base + PCIE_PL_PFLR);
  395. val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
  396. val |= PCIE_PL_PFLR_FORCE_LINK;
  397. imx_pcie_fix_dabt_handler(true);
  398. writel(val, priv->dbi_base + PCIE_PL_PFLR);
  399. imx_pcie_fix_dabt_handler(false);
  400. gpr12 &= ~IOMUXC_GPR12_PCIE_CTL_2;
  401. writel(val, &iomuxc_regs->gpr[12]);
  402. }
  403. }
  404. setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
  405. clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
  406. #endif
  407. return 0;
  408. }
  409. static int imx6_pcie_init_phy(void)
  410. {
  411. struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  412. clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
  413. clrsetbits_le32(&iomuxc_regs->gpr[12],
  414. IOMUXC_GPR12_DEVICE_TYPE_MASK,
  415. IOMUXC_GPR12_DEVICE_TYPE_RC);
  416. clrsetbits_le32(&iomuxc_regs->gpr[12],
  417. IOMUXC_GPR12_LOS_LEVEL_MASK,
  418. IOMUXC_GPR12_LOS_LEVEL_9);
  419. #ifdef CONFIG_MX6SX
  420. clrsetbits_le32(&iomuxc_regs->gpr[12],
  421. IOMUXC_GPR12_RX_EQ_MASK,
  422. IOMUXC_GPR12_RX_EQ_2);
  423. #endif
  424. writel((0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET) |
  425. (0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET) |
  426. (20 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET) |
  427. (127 << IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET) |
  428. (127 << IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET),
  429. &iomuxc_regs->gpr[8]);
  430. return 0;
  431. }
  432. __weak int imx6_pcie_toggle_power(void)
  433. {
  434. #ifdef CONFIG_PCIE_IMX_POWER_GPIO
  435. gpio_request(CONFIG_PCIE_IMX_POWER_GPIO, "pcie_power");
  436. gpio_direction_output(CONFIG_PCIE_IMX_POWER_GPIO, 0);
  437. mdelay(20);
  438. gpio_set_value(CONFIG_PCIE_IMX_POWER_GPIO, 1);
  439. mdelay(20);
  440. gpio_free(CONFIG_PCIE_IMX_POWER_GPIO);
  441. #endif
  442. return 0;
  443. }
  444. __weak int imx6_pcie_toggle_reset(void)
  445. {
  446. /*
  447. * See 'PCI EXPRESS BASE SPECIFICATION, REV 3.0, SECTION 6.6.1'
  448. * for detailed understanding of the PCIe CR reset logic.
  449. *
  450. * The PCIe #PERST reset line _MUST_ be connected, otherwise your
  451. * design does not conform to the specification. You must wait at
  452. * least 20 ms after de-asserting the #PERST so the EP device can
  453. * do self-initialisation.
  454. *
  455. * In case your #PERST pin is connected to a plain GPIO pin of the
  456. * CPU, you can define CONFIG_PCIE_IMX_PERST_GPIO in your board's
  457. * configuration file and the condition below will handle the rest
  458. * of the reset toggling.
  459. *
  460. * In case your #PERST toggling logic is more complex, for example
  461. * connected via CPLD or somesuch, you can override this function
  462. * in your board file and implement reset logic as needed. You must
  463. * not forget to wait at least 20 ms after de-asserting #PERST in
  464. * this case either though.
  465. *
  466. * In case your #PERST line of the PCIe EP device is not connected
  467. * at all, your design is broken and you should fix your design,
  468. * otherwise you will observe problems like for example the link
  469. * not coming up after rebooting the system back from running Linux
  470. * that uses the PCIe as well OR the PCIe link might not come up in
  471. * Linux at all in the first place since it's in some non-reset
  472. * state due to being previously used in U-Boot.
  473. */
  474. #ifdef CONFIG_PCIE_IMX_PERST_GPIO
  475. gpio_request(CONFIG_PCIE_IMX_PERST_GPIO, "pcie_reset");
  476. gpio_direction_output(CONFIG_PCIE_IMX_PERST_GPIO, 0);
  477. mdelay(20);
  478. gpio_set_value(CONFIG_PCIE_IMX_PERST_GPIO, 1);
  479. mdelay(20);
  480. gpio_free(CONFIG_PCIE_IMX_PERST_GPIO);
  481. #else
  482. puts("WARNING: Make sure the PCIe #PERST line is connected!\n");
  483. #endif
  484. return 0;
  485. }
  486. static int imx6_pcie_deassert_core_reset(void)
  487. {
  488. struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  489. imx6_pcie_toggle_power();
  490. enable_pcie_clock();
  491. if (is_mx6dqp())
  492. clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
  493. /*
  494. * Wait for the clock to settle a bit, when the clock are sourced
  495. * from the CPU, we need about 30 ms to settle.
  496. */
  497. mdelay(50);
  498. #if defined(CONFIG_MX6SX)
  499. /* SSP_EN is not used on MX6SX anymore */
  500. clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
  501. /* Clear PCIe PHY reset bit */
  502. clrbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
  503. #else
  504. /* Enable PCIe */
  505. clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
  506. setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
  507. #endif
  508. imx6_pcie_toggle_reset();
  509. return 0;
  510. }
  511. static int imx_pcie_link_up(struct imx_pcie_priv *priv)
  512. {
  513. struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  514. uint32_t tmp;
  515. int count = 0;
  516. imx6_pcie_assert_core_reset(priv, false);
  517. imx6_pcie_init_phy();
  518. imx6_pcie_deassert_core_reset();
  519. imx_pcie_regions_setup(priv);
  520. /*
  521. * By default, the subordinate is set equally to the secondary
  522. * bus (0x01) when the RC boots.
  523. * This means that theoretically, only bus 1 is reachable from the RC.
  524. * Force the PCIe RC subordinate to 0xff, otherwise no downstream
  525. * devices will be detected if the enumeration is applied strictly.
  526. */
  527. tmp = readl(priv->dbi_base + 0x18);
  528. tmp |= (0xff << 16);
  529. writel(tmp, priv->dbi_base + 0x18);
  530. /*
  531. * FIXME: Force the PCIe RC to Gen1 operation
  532. * The RC must be forced into Gen1 mode before bringing the link
  533. * up, otherwise no downstream devices are detected. After the
  534. * link is up, a managed Gen1->Gen2 transition can be initiated.
  535. */
  536. tmp = readl(priv->dbi_base + 0x7c);
  537. tmp &= ~0xf;
  538. tmp |= 0x1;
  539. writel(tmp, priv->dbi_base + 0x7c);
  540. /* LTSSM enable, starting link. */
  541. setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
  542. while (!imx6_pcie_link_up(priv)) {
  543. udelay(10);
  544. count++;
  545. if (count >= 4000) {
  546. #ifdef CONFIG_PCI_SCAN_SHOW
  547. puts("PCI: pcie phy link never came up\n");
  548. #endif
  549. debug("DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
  550. readl(priv->dbi_base + PCIE_PHY_DEBUG_R0),
  551. readl(priv->dbi_base + PCIE_PHY_DEBUG_R1));
  552. return -EINVAL;
  553. }
  554. }
  555. return 0;
  556. }
  557. #if !CONFIG_IS_ENABLED(DM_PCI)
  558. static struct imx_pcie_priv imx_pcie_priv = {
  559. .dbi_base = (void __iomem *)MX6_DBI_ADDR,
  560. .cfg_base = (void __iomem *)MX6_ROOT_ADDR,
  561. };
  562. static struct imx_pcie_priv *priv = &imx_pcie_priv;
  563. static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
  564. int where, u32 *val)
  565. {
  566. struct imx_pcie_priv *priv = hose->priv_data;
  567. return imx_pcie_read_cfg(priv, d, where, val);
  568. }
  569. static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
  570. int where, u32 val)
  571. {
  572. struct imx_pcie_priv *priv = hose->priv_data;
  573. return imx_pcie_write_cfg(priv, d, where, val);
  574. }
  575. void imx_pcie_init(void)
  576. {
  577. /* Static instance of the controller. */
  578. static struct pci_controller pcc;
  579. struct pci_controller *hose = &pcc;
  580. int ret;
  581. memset(&pcc, 0, sizeof(pcc));
  582. hose->priv_data = priv;
  583. /* PCI I/O space */
  584. pci_set_region(&hose->regions[0],
  585. MX6_IO_ADDR, MX6_IO_ADDR,
  586. MX6_IO_SIZE, PCI_REGION_IO);
  587. /* PCI memory space */
  588. pci_set_region(&hose->regions[1],
  589. MX6_MEM_ADDR, MX6_MEM_ADDR,
  590. MX6_MEM_SIZE, PCI_REGION_MEM);
  591. /* System memory space */
  592. pci_set_region(&hose->regions[2],
  593. MMDC0_ARB_BASE_ADDR, MMDC0_ARB_BASE_ADDR,
  594. 0xefffffff, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  595. hose->region_count = 3;
  596. pci_set_ops(hose,
  597. pci_hose_read_config_byte_via_dword,
  598. pci_hose_read_config_word_via_dword,
  599. imx_pcie_read_config,
  600. pci_hose_write_config_byte_via_dword,
  601. pci_hose_write_config_word_via_dword,
  602. imx_pcie_write_config);
  603. /* Start the controller. */
  604. ret = imx_pcie_link_up(priv);
  605. if (!ret) {
  606. pci_register_hose(hose);
  607. hose->last_busno = pci_hose_scan(hose);
  608. }
  609. }
  610. void imx_pcie_remove(void)
  611. {
  612. imx6_pcie_assert_core_reset(priv, true);
  613. }
  614. /* Probe function. */
  615. void pci_init_board(void)
  616. {
  617. imx_pcie_init();
  618. }
  619. #else
  620. static int imx_pcie_dm_read_config(const struct udevice *dev, pci_dev_t bdf,
  621. uint offset, ulong *value,
  622. enum pci_size_t size)
  623. {
  624. struct imx_pcie_priv *priv = dev_get_priv(dev);
  625. u32 tmpval;
  626. int ret;
  627. ret = imx_pcie_read_cfg(priv, bdf, offset, &tmpval);
  628. if (ret)
  629. return ret;
  630. *value = pci_conv_32_to_size(tmpval, offset, size);
  631. return 0;
  632. }
  633. static int imx_pcie_dm_write_config(struct udevice *dev, pci_dev_t bdf,
  634. uint offset, ulong value,
  635. enum pci_size_t size)
  636. {
  637. struct imx_pcie_priv *priv = dev_get_priv(dev);
  638. u32 tmpval, newval;
  639. int ret;
  640. ret = imx_pcie_read_cfg(priv, bdf, offset, &tmpval);
  641. if (ret)
  642. return ret;
  643. newval = pci_conv_size_to_32(tmpval, value, offset, size);
  644. return imx_pcie_write_cfg(priv, bdf, offset, newval);
  645. }
  646. static int imx_pcie_dm_probe(struct udevice *dev)
  647. {
  648. struct imx_pcie_priv *priv = dev_get_priv(dev);
  649. return imx_pcie_link_up(priv);
  650. }
  651. static int imx_pcie_dm_remove(struct udevice *dev)
  652. {
  653. struct imx_pcie_priv *priv = dev_get_priv(dev);
  654. imx6_pcie_assert_core_reset(priv, true);
  655. return 0;
  656. }
  657. static int imx_pcie_ofdata_to_platdata(struct udevice *dev)
  658. {
  659. struct imx_pcie_priv *priv = dev_get_priv(dev);
  660. priv->dbi_base = (void __iomem *)devfdt_get_addr_index(dev, 0);
  661. priv->cfg_base = (void __iomem *)devfdt_get_addr_index(dev, 1);
  662. if (!priv->dbi_base || !priv->cfg_base)
  663. return -EINVAL;
  664. return 0;
  665. }
  666. static const struct dm_pci_ops imx_pcie_ops = {
  667. .read_config = imx_pcie_dm_read_config,
  668. .write_config = imx_pcie_dm_write_config,
  669. };
  670. static const struct udevice_id imx_pcie_ids[] = {
  671. { .compatible = "fsl,imx6q-pcie" },
  672. { .compatible = "fsl,imx6sx-pcie" },
  673. { }
  674. };
  675. U_BOOT_DRIVER(imx_pcie) = {
  676. .name = "imx_pcie",
  677. .id = UCLASS_PCI,
  678. .of_match = imx_pcie_ids,
  679. .ops = &imx_pcie_ops,
  680. .probe = imx_pcie_dm_probe,
  681. .remove = imx_pcie_dm_remove,
  682. .ofdata_to_platdata = imx_pcie_ofdata_to_platdata,
  683. .priv_auto_alloc_size = sizeof(struct imx_pcie_priv),
  684. .flags = DM_FLAG_OS_PREPARE,
  685. };
  686. #endif