pcie_fsl.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * Copyright 2019 NXP
  4. *
  5. * PCIe DM U-Boot driver for Freescale PowerPC SoCs
  6. * Author: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <malloc.h>
  11. #include <mapmem.h>
  12. #include <pci.h>
  13. #include <asm/fsl_pci.h>
  14. #include <asm/fsl_serdes.h>
  15. #include <asm/io.h>
  16. #include "pcie_fsl.h"
  17. #include <dm/device_compat.h>
  18. LIST_HEAD(fsl_pcie_list);
  19. static int fsl_pcie_link_up(struct fsl_pcie *pcie);
  20. static int fsl_pcie_addr_valid(struct fsl_pcie *pcie, pci_dev_t bdf)
  21. {
  22. struct udevice *bus = pcie->bus;
  23. if (!pcie->enabled)
  24. return -ENXIO;
  25. if (PCI_BUS(bdf) < bus->seq)
  26. return -EINVAL;
  27. if (PCI_BUS(bdf) > bus->seq && (!fsl_pcie_link_up(pcie) || pcie->mode))
  28. return -EINVAL;
  29. if (PCI_BUS(bdf) == bus->seq && (PCI_DEV(bdf) > 0 || PCI_FUNC(bdf) > 0))
  30. return -EINVAL;
  31. if (PCI_BUS(bdf) == (bus->seq + 1) && (PCI_DEV(bdf) > 0))
  32. return -EINVAL;
  33. return 0;
  34. }
  35. static int fsl_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
  36. uint offset, ulong *valuep,
  37. enum pci_size_t size)
  38. {
  39. struct fsl_pcie *pcie = dev_get_priv(bus);
  40. ccsr_fsl_pci_t *regs = pcie->regs;
  41. u32 val;
  42. if (fsl_pcie_addr_valid(pcie, bdf)) {
  43. *valuep = pci_get_ff(size);
  44. return 0;
  45. }
  46. bdf = bdf - PCI_BDF(bus->seq, 0, 0);
  47. val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
  48. out_be32(&regs->cfg_addr, val);
  49. sync();
  50. switch (size) {
  51. case PCI_SIZE_8:
  52. *valuep = in_8((u8 *)&regs->cfg_data + (offset & 3));
  53. break;
  54. case PCI_SIZE_16:
  55. *valuep = in_le16((u16 *)((u8 *)&regs->cfg_data +
  56. (offset & 2)));
  57. break;
  58. case PCI_SIZE_32:
  59. *valuep = in_le32(&regs->cfg_data);
  60. break;
  61. }
  62. return 0;
  63. }
  64. static int fsl_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
  65. uint offset, ulong value,
  66. enum pci_size_t size)
  67. {
  68. struct fsl_pcie *pcie = dev_get_priv(bus);
  69. ccsr_fsl_pci_t *regs = pcie->regs;
  70. u32 val;
  71. u8 val_8;
  72. u16 val_16;
  73. u32 val_32;
  74. if (fsl_pcie_addr_valid(pcie, bdf))
  75. return 0;
  76. bdf = bdf - PCI_BDF(bus->seq, 0, 0);
  77. val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
  78. out_be32(&regs->cfg_addr, val);
  79. sync();
  80. switch (size) {
  81. case PCI_SIZE_8:
  82. val_8 = value;
  83. out_8((u8 *)&regs->cfg_data + (offset & 3), val_8);
  84. break;
  85. case PCI_SIZE_16:
  86. val_16 = value;
  87. out_le16((u16 *)((u8 *)&regs->cfg_data + (offset & 2)), val_16);
  88. break;
  89. case PCI_SIZE_32:
  90. val_32 = value;
  91. out_le32(&regs->cfg_data, val_32);
  92. break;
  93. }
  94. return 0;
  95. }
  96. static int fsl_pcie_hose_read_config(struct fsl_pcie *pcie, uint offset,
  97. ulong *valuep, enum pci_size_t size)
  98. {
  99. int ret;
  100. struct udevice *bus = pcie->bus;
  101. ret = fsl_pcie_read_config(bus, PCI_BDF(bus->seq, 0, 0),
  102. offset, valuep, size);
  103. return ret;
  104. }
  105. static int fsl_pcie_hose_write_config(struct fsl_pcie *pcie, uint offset,
  106. ulong value, enum pci_size_t size)
  107. {
  108. struct udevice *bus = pcie->bus;
  109. return fsl_pcie_write_config(bus, PCI_BDF(bus->seq, 0, 0),
  110. offset, value, size);
  111. }
  112. static int fsl_pcie_hose_read_config_byte(struct fsl_pcie *pcie, uint offset,
  113. u8 *valuep)
  114. {
  115. ulong val;
  116. int ret;
  117. ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_8);
  118. *valuep = val;
  119. return ret;
  120. }
  121. static int fsl_pcie_hose_read_config_word(struct fsl_pcie *pcie, uint offset,
  122. u16 *valuep)
  123. {
  124. ulong val;
  125. int ret;
  126. ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_16);
  127. *valuep = val;
  128. return ret;
  129. }
  130. static int fsl_pcie_hose_read_config_dword(struct fsl_pcie *pcie, uint offset,
  131. u32 *valuep)
  132. {
  133. ulong val;
  134. int ret;
  135. ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_32);
  136. *valuep = val;
  137. return ret;
  138. }
  139. static int fsl_pcie_hose_write_config_byte(struct fsl_pcie *pcie, uint offset,
  140. u8 value)
  141. {
  142. return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_8);
  143. }
  144. static int fsl_pcie_hose_write_config_word(struct fsl_pcie *pcie, uint offset,
  145. u16 value)
  146. {
  147. return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_16);
  148. }
  149. static int fsl_pcie_hose_write_config_dword(struct fsl_pcie *pcie, uint offset,
  150. u32 value)
  151. {
  152. return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_32);
  153. }
  154. static int fsl_pcie_link_up(struct fsl_pcie *pcie)
  155. {
  156. ccsr_fsl_pci_t *regs = pcie->regs;
  157. u16 ltssm;
  158. if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
  159. ltssm = (in_be32(&regs->pex_csr0)
  160. & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
  161. return ltssm == LTSSM_L0_REV3;
  162. }
  163. fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, &ltssm);
  164. return ltssm == LTSSM_L0;
  165. }
  166. static bool fsl_pcie_is_agent(struct fsl_pcie *pcie)
  167. {
  168. u8 header_type;
  169. fsl_pcie_hose_read_config_byte(pcie, PCI_HEADER_TYPE, &header_type);
  170. return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
  171. }
  172. static int fsl_pcie_setup_law(struct fsl_pcie *pcie)
  173. {
  174. struct pci_region *io, *mem, *pref;
  175. pci_get_regions(pcie->bus, &io, &mem, &pref);
  176. if (mem)
  177. set_next_law(mem->phys_start,
  178. law_size_bits(mem->size),
  179. pcie->law_trgt_if);
  180. if (io)
  181. set_next_law(io->phys_start,
  182. law_size_bits(io->size),
  183. pcie->law_trgt_if);
  184. return 0;
  185. }
  186. static void fsl_pcie_config_ready(struct fsl_pcie *pcie)
  187. {
  188. ccsr_fsl_pci_t *regs = pcie->regs;
  189. if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
  190. setbits_be32(&regs->config, FSL_PCIE_V3_CFG_RDY);
  191. return;
  192. }
  193. fsl_pcie_hose_write_config_byte(pcie, FSL_PCIE_CFG_RDY, 0x1);
  194. }
  195. static int fsl_pcie_setup_outbound_win(struct fsl_pcie *pcie, int idx,
  196. int type, u64 phys, u64 bus_addr,
  197. pci_size_t size)
  198. {
  199. ccsr_fsl_pci_t *regs = pcie->regs;
  200. pot_t *po = &regs->pot[idx];
  201. u32 war, sz;
  202. if (idx < 0)
  203. return -EINVAL;
  204. out_be32(&po->powbar, phys >> 12);
  205. out_be32(&po->potar, bus_addr >> 12);
  206. #ifdef CONFIG_SYS_PCI_64BIT
  207. out_be32(&po->potear, bus_addr >> 44);
  208. #else
  209. out_be32(&po->potear, 0);
  210. #endif
  211. sz = (__ilog2_u64((u64)size) - 1);
  212. war = POWAR_EN | sz;
  213. if (type == PCI_REGION_IO)
  214. war |= POWAR_IO_READ | POWAR_IO_WRITE;
  215. else
  216. war |= POWAR_MEM_READ | POWAR_MEM_WRITE;
  217. out_be32(&po->powar, war);
  218. return 0;
  219. }
  220. static int fsl_pcie_setup_inbound_win(struct fsl_pcie *pcie, int idx,
  221. bool pf, u64 phys, u64 bus_addr,
  222. pci_size_t size)
  223. {
  224. ccsr_fsl_pci_t *regs = pcie->regs;
  225. pit_t *pi = &regs->pit[idx];
  226. u32 sz = (__ilog2_u64(size) - 1);
  227. u32 flag = PIWAR_LOCAL;
  228. if (idx < 0)
  229. return -EINVAL;
  230. out_be32(&pi->pitar, phys >> 12);
  231. out_be32(&pi->piwbar, bus_addr >> 12);
  232. #ifdef CONFIG_SYS_PCI_64BIT
  233. out_be32(&pi->piwbear, bus_addr >> 44);
  234. #else
  235. out_be32(&pi->piwbear, 0);
  236. #endif
  237. #ifdef CONFIG_SYS_FSL_ERRATUM_A005434
  238. flag = 0;
  239. #endif
  240. flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
  241. if (pf)
  242. flag |= PIWAR_PF;
  243. out_be32(&pi->piwar, flag | sz);
  244. return 0;
  245. }
  246. static int fsl_pcie_setup_outbound_wins(struct fsl_pcie *pcie)
  247. {
  248. struct pci_region *io, *mem, *pref;
  249. int idx = 1; /* skip 0 */
  250. pci_get_regions(pcie->bus, &io, &mem, &pref);
  251. if (io)
  252. /* ATU : OUTBOUND : IO */
  253. fsl_pcie_setup_outbound_win(pcie, idx++,
  254. PCI_REGION_IO,
  255. io->phys_start,
  256. io->bus_start,
  257. io->size);
  258. if (mem)
  259. /* ATU : OUTBOUND : MEM */
  260. fsl_pcie_setup_outbound_win(pcie, idx++,
  261. PCI_REGION_MEM,
  262. mem->phys_start,
  263. mem->bus_start,
  264. mem->size);
  265. return 0;
  266. }
  267. static int fsl_pcie_setup_inbound_wins(struct fsl_pcie *pcie)
  268. {
  269. phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
  270. pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
  271. u64 sz = min((u64)gd->ram_size, (1ull << 32));
  272. pci_size_t pci_sz;
  273. int idx;
  274. if (pcie->block_rev >= PEX_IP_BLK_REV_2_2)
  275. idx = 2;
  276. else
  277. idx = 3;
  278. pci_sz = 1ull << __ilog2_u64(sz);
  279. dev_dbg(pcie->bus, "R0 bus_start: %llx phys_start: %llx size: %llx\n",
  280. (u64)bus_start, (u64)phys_start, (u64)sz);
  281. /* if we aren't an exact power of two match, pci_sz is smaller
  282. * round it up to the next power of two. We report the actual
  283. * size to pci region tracking.
  284. */
  285. if (pci_sz != sz)
  286. sz = 2ull << __ilog2_u64(sz);
  287. fsl_pcie_setup_inbound_win(pcie, idx--, true,
  288. CONFIG_SYS_PCI_MEMORY_PHYS,
  289. CONFIG_SYS_PCI_MEMORY_BUS, sz);
  290. #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
  291. /*
  292. * On 64-bit capable systems, set up a mapping for all of DRAM
  293. * in high pci address space.
  294. */
  295. pci_sz = 1ull << __ilog2_u64(gd->ram_size);
  296. /* round up to the next largest power of two */
  297. if (gd->ram_size > pci_sz)
  298. pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
  299. dev_dbg(pcie->bus, "R64 bus_start: %llx phys_start: %llx size: %llx\n",
  300. (u64)CONFIG_SYS_PCI64_MEMORY_BUS,
  301. (u64)CONFIG_SYS_PCI_MEMORY_PHYS, (u64)pci_sz);
  302. fsl_pcie_setup_inbound_win(pcie, idx--, true,
  303. CONFIG_SYS_PCI_MEMORY_PHYS,
  304. CONFIG_SYS_PCI64_MEMORY_BUS, pci_sz);
  305. #endif
  306. return 0;
  307. }
  308. static int fsl_pcie_init_atmu(struct fsl_pcie *pcie)
  309. {
  310. fsl_pcie_setup_outbound_wins(pcie);
  311. fsl_pcie_setup_inbound_wins(pcie);
  312. return 0;
  313. }
  314. static int fsl_pcie_init_port(struct fsl_pcie *pcie)
  315. {
  316. ccsr_fsl_pci_t *regs = pcie->regs;
  317. u32 val_32;
  318. u16 val_16;
  319. fsl_pcie_init_atmu(pcie);
  320. #ifdef CONFIG_FSL_PCIE_DISABLE_ASPM
  321. val_32 = 0;
  322. fsl_pcie_hose_read_config_dword(pcie, PCI_LCR, &val_32);
  323. val_32 &= ~0x03;
  324. fsl_pcie_hose_write_config_dword(pcie, PCI_LCR, val_32);
  325. udelay(1);
  326. #endif
  327. #ifdef CONFIG_FSL_PCIE_RESET
  328. u16 ltssm;
  329. int i;
  330. if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
  331. /* assert PCIe reset */
  332. setbits_be32(&regs->pdb_stat, 0x08000000);
  333. (void)in_be32(&regs->pdb_stat);
  334. udelay(1000);
  335. /* clear PCIe reset */
  336. clrbits_be32(&regs->pdb_stat, 0x08000000);
  337. asm("sync;isync");
  338. for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
  339. udelay(1000);
  340. } else {
  341. fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, &ltssm);
  342. if (ltssm == 1) {
  343. /* assert PCIe reset */
  344. setbits_be32(&regs->pdb_stat, 0x08000000);
  345. (void)in_be32(&regs->pdb_stat);
  346. udelay(100);
  347. /* clear PCIe reset */
  348. clrbits_be32(&regs->pdb_stat, 0x08000000);
  349. asm("sync;isync");
  350. for (i = 0; i < 100 &&
  351. !fsl_pcie_link_up(pcie); i++)
  352. udelay(1000);
  353. }
  354. }
  355. #endif
  356. #ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
  357. if (!fsl_pcie_link_up(pcie)) {
  358. serdes_corenet_t *srds_regs;
  359. srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
  360. val_32 = in_be32(&srds_regs->srdspccr0);
  361. if ((val_32 >> 28) == 3) {
  362. int i;
  363. out_be32(&srds_regs->srdspccr0, 2 << 28);
  364. setbits_be32(&regs->pdb_stat, 0x08000000);
  365. in_be32(&regs->pdb_stat);
  366. udelay(100);
  367. clrbits_be32(&regs->pdb_stat, 0x08000000);
  368. asm("sync;isync");
  369. for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
  370. udelay(1000);
  371. }
  372. }
  373. #endif
  374. /*
  375. * The Read-Only Write Enable bit defaults to 1 instead of 0.
  376. * Set to 0 to protect the read-only registers.
  377. */
  378. #ifdef CONFIG_SYS_FSL_ERRATUM_A007815
  379. clrbits_be32(&regs->dbi_ro_wr_en, 0x01);
  380. #endif
  381. /*
  382. * Enable All Error Interrupts except
  383. * - Master abort (pci)
  384. * - Master PERR (pci)
  385. * - ICCA (PCIe)
  386. */
  387. out_be32(&regs->peer, ~0x20140);
  388. /* set URR, FER, NFER (but not CER) */
  389. fsl_pcie_hose_read_config_dword(pcie, PCI_DCR, &val_32);
  390. val_32 |= 0xf000e;
  391. fsl_pcie_hose_write_config_dword(pcie, PCI_DCR, val_32);
  392. /* Clear all error indications */
  393. out_be32(&regs->pme_msg_det, 0xffffffff);
  394. out_be32(&regs->pme_msg_int_en, 0xffffffff);
  395. out_be32(&regs->pedr, 0xffffffff);
  396. fsl_pcie_hose_read_config_word(pcie, PCI_DSR, &val_16);
  397. if (val_16)
  398. fsl_pcie_hose_write_config_word(pcie, PCI_DSR, 0xffff);
  399. fsl_pcie_hose_read_config_word(pcie, PCI_SEC_STATUS, &val_16);
  400. if (val_16)
  401. fsl_pcie_hose_write_config_word(pcie, PCI_SEC_STATUS, 0xffff);
  402. return 0;
  403. }
  404. static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie)
  405. {
  406. ccsr_fsl_pci_t *regs = pcie->regs;
  407. u32 classcode_reg;
  408. u32 val;
  409. if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
  410. classcode_reg = PCI_CLASS_REVISION;
  411. setbits_be32(&regs->dbi_ro_wr_en, 0x01);
  412. } else {
  413. classcode_reg = CSR_CLASSCODE;
  414. }
  415. fsl_pcie_hose_read_config_dword(pcie, classcode_reg, &val);
  416. val &= 0xff;
  417. val |= PCI_CLASS_BRIDGE_PCI << 16;
  418. fsl_pcie_hose_write_config_dword(pcie, classcode_reg, val);
  419. if (pcie->block_rev >= PEX_IP_BLK_REV_3_0)
  420. clrbits_be32(&regs->dbi_ro_wr_en, 0x01);
  421. return 0;
  422. }
  423. static int fsl_pcie_init_rc(struct fsl_pcie *pcie)
  424. {
  425. return fsl_pcie_fixup_classcode(pcie);
  426. }
  427. static int fsl_pcie_init_ep(struct fsl_pcie *pcie)
  428. {
  429. fsl_pcie_config_ready(pcie);
  430. return 0;
  431. }
  432. static int fsl_pcie_probe(struct udevice *dev)
  433. {
  434. struct fsl_pcie *pcie = dev_get_priv(dev);
  435. ccsr_fsl_pci_t *regs = pcie->regs;
  436. u16 val_16;
  437. pcie->bus = dev;
  438. pcie->block_rev = in_be32(&regs->block_rev1);
  439. list_add(&pcie->list, &fsl_pcie_list);
  440. pcie->enabled = is_serdes_configured(PCIE1 + pcie->idx);
  441. if (!pcie->enabled) {
  442. printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
  443. return 0;
  444. }
  445. fsl_pcie_setup_law(pcie);
  446. pcie->mode = fsl_pcie_is_agent(pcie);
  447. fsl_pcie_init_port(pcie);
  448. printf("PCIe%d: %s ", pcie->idx, dev->name);
  449. if (pcie->mode) {
  450. printf("Endpoint");
  451. fsl_pcie_init_ep(pcie);
  452. } else {
  453. printf("Root Complex");
  454. fsl_pcie_init_rc(pcie);
  455. }
  456. if (!fsl_pcie_link_up(pcie)) {
  457. printf(": %s\n", pcie->mode ? "undetermined link" : "no link");
  458. return 0;
  459. }
  460. fsl_pcie_hose_read_config_word(pcie, PCI_LSR, &val_16);
  461. printf(": x%d gen%d\n", (val_16 & 0x3f0) >> 4, (val_16 & 0xf));
  462. return 0;
  463. }
  464. static int fsl_pcie_ofdata_to_platdata(struct udevice *dev)
  465. {
  466. struct fsl_pcie *pcie = dev_get_priv(dev);
  467. struct fsl_pcie_data *info;
  468. int ret;
  469. pcie->regs = dev_remap_addr(dev);
  470. if (!pcie->regs) {
  471. pr_err("\"reg\" resource not found\n");
  472. return -EINVAL;
  473. }
  474. ret = dev_read_u32(dev, "law_trgt_if", &pcie->law_trgt_if);
  475. if (ret < 0) {
  476. pr_err("\"law_trgt_if\" not found\n");
  477. return ret;
  478. }
  479. info = (struct fsl_pcie_data *)dev_get_driver_data(dev);
  480. pcie->info = info;
  481. pcie->idx = abs((u32)(dev_read_addr(dev) & info->block_offset_mask) -
  482. info->block_offset) / info->stride;
  483. return 0;
  484. }
  485. static const struct dm_pci_ops fsl_pcie_ops = {
  486. .read_config = fsl_pcie_read_config,
  487. .write_config = fsl_pcie_write_config,
  488. };
  489. static struct fsl_pcie_data p1_p2_data = {
  490. .block_offset = 0xa000,
  491. .block_offset_mask = 0xffff,
  492. .stride = 0x1000,
  493. };
  494. static struct fsl_pcie_data p2041_data = {
  495. .block_offset = 0x200000,
  496. .block_offset_mask = 0x3fffff,
  497. .stride = 0x1000,
  498. };
  499. static struct fsl_pcie_data t2080_data = {
  500. .block_offset = 0x240000,
  501. .block_offset_mask = 0x3fffff,
  502. .stride = 0x10000,
  503. };
  504. static const struct udevice_id fsl_pcie_ids[] = {
  505. { .compatible = "fsl,pcie-mpc8548", .data = (ulong)&p1_p2_data },
  506. { .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data },
  507. { .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data },
  508. { .compatible = "fsl,pcie-p3041", .data = (ulong)&p2041_data },
  509. { .compatible = "fsl,pcie-p4080", .data = (ulong)&p2041_data },
  510. { .compatible = "fsl,pcie-p5040", .data = (ulong)&p2041_data },
  511. { .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data },
  512. { .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data },
  513. { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data },
  514. { .compatible = "fsl,pcie-t4240", .data = (ulong)&t2080_data },
  515. { }
  516. };
  517. U_BOOT_DRIVER(fsl_pcie) = {
  518. .name = "fsl_pcie",
  519. .id = UCLASS_PCI,
  520. .of_match = fsl_pcie_ids,
  521. .ops = &fsl_pcie_ops,
  522. .ofdata_to_platdata = fsl_pcie_ofdata_to_platdata,
  523. .probe = fsl_pcie_probe,
  524. .priv_auto_alloc_size = sizeof(struct fsl_pcie),
  525. };