pcie_dw_ti.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Texas Instruments, Inc
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <pci.h>
  8. #include <generic-phy.h>
  9. #include <power-domain.h>
  10. #include <regmap.h>
  11. #include <syscon.h>
  12. #include <asm/io.h>
  13. #include <asm-generic/gpio.h>
  14. #include <dm/device_compat.h>
  15. #include <linux/err.h>
  16. DECLARE_GLOBAL_DATA_PTR;
  17. #define PCIE_VENDORID_MASK GENMASK(15, 0)
  18. #define PCIE_DEVICEID_SHIFT 16
  19. /* PCI DBICS registers */
  20. #define PCIE_CONFIG_BAR0 0x10
  21. #define PCIE_LINK_STATUS_REG 0x80
  22. #define PCIE_LINK_STATUS_SPEED_OFF 16
  23. #define PCIE_LINK_STATUS_SPEED_MASK (0xf << PCIE_LINK_STATUS_SPEED_OFF)
  24. #define PCIE_LINK_STATUS_WIDTH_OFF 20
  25. #define PCIE_LINK_STATUS_WIDTH_MASK (0xf << PCIE_LINK_STATUS_WIDTH_OFF)
  26. #define PCIE_LINK_CAPABILITY 0x7c
  27. #define PCIE_LINK_CTL_2 0xa0
  28. #define TARGET_LINK_SPEED_MASK 0xf
  29. #define LINK_SPEED_GEN_1 0x1
  30. #define LINK_SPEED_GEN_2 0x2
  31. #define LINK_SPEED_GEN_3 0x3
  32. #define PCIE_MISC_CONTROL_1_OFF 0x8bc
  33. #define PCIE_DBI_RO_WR_EN BIT(0)
  34. #define PLR_OFFSET 0x700
  35. #define PCIE_PORT_DEBUG0 (PLR_OFFSET + 0x28)
  36. #define PORT_LOGIC_LTSSM_STATE_MASK 0x1f
  37. #define PORT_LOGIC_LTSSM_STATE_L0 0x11
  38. #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80c
  39. #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
  40. #define PCIE_LINK_UP_TIMEOUT_MS 100
  41. /*
  42. * iATU Unroll-specific register definitions
  43. * From 4.80 core version the address translation will be made by unroll.
  44. * The registers are offset from atu_base
  45. */
  46. #define PCIE_ATU_UNR_REGION_CTRL1 0x00
  47. #define PCIE_ATU_UNR_REGION_CTRL2 0x04
  48. #define PCIE_ATU_UNR_LOWER_BASE 0x08
  49. #define PCIE_ATU_UNR_UPPER_BASE 0x0c
  50. #define PCIE_ATU_UNR_LIMIT 0x10
  51. #define PCIE_ATU_UNR_LOWER_TARGET 0x14
  52. #define PCIE_ATU_UNR_UPPER_TARGET 0x18
  53. #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
  54. #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
  55. #define PCIE_ATU_TYPE_MEM (0x0 << 0)
  56. #define PCIE_ATU_TYPE_IO (0x2 << 0)
  57. #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
  58. #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
  59. #define PCIE_ATU_ENABLE (0x1 << 31)
  60. #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
  61. #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
  62. #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
  63. #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
  64. /* Register address builder */
  65. #define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) ((region) << 9)
  66. /* Offsets from App base */
  67. #define PCIE_CMD_STATUS 0x04
  68. #define LTSSM_EN_VAL BIT(0)
  69. /* Parameters for the waiting for iATU enabled routine */
  70. #define LINK_WAIT_MAX_IATU_RETRIES 5
  71. #define LINK_WAIT_IATU 10000
  72. #define AM654_PCIE_DEV_TYPE_MASK 0x3
  73. #define EP 0x0
  74. #define LEG_EP 0x1
  75. #define RC 0x2
  76. /**
  77. * struct pcie_dw_ti - TI DW PCIe controller state
  78. *
  79. * @app_base: The base address of application register space
  80. * @dbics_base: The base address of dbics register space
  81. * @cfg_base: The base address of configuration space
  82. * @atu_base: The base address of ATU space
  83. * @cfg_size: The size of the configuration space which is needed
  84. * as it gets written into the PCIE_ATU_LIMIT register
  85. * @first_busno: This driver supports multiple PCIe controllers.
  86. * first_busno stores the bus number of the PCIe root-port
  87. * number which may vary depending on the PCIe setup
  88. * (PEX switches etc).
  89. */
  90. struct pcie_dw_ti {
  91. void *app_base;
  92. void *dbi_base;
  93. void *cfg_base;
  94. void *atu_base;
  95. fdt_size_t cfg_size;
  96. int first_busno;
  97. struct udevice *dev;
  98. /* IO and MEM PCI regions */
  99. struct pci_region io;
  100. struct pci_region mem;
  101. };
  102. enum dw_pcie_device_mode {
  103. DW_PCIE_UNKNOWN_TYPE,
  104. DW_PCIE_EP_TYPE,
  105. DW_PCIE_LEG_EP_TYPE,
  106. DW_PCIE_RC_TYPE,
  107. };
  108. static int pcie_dw_get_link_speed(struct pcie_dw_ti *pci)
  109. {
  110. return (readl(pci->dbi_base + PCIE_LINK_STATUS_REG) &
  111. PCIE_LINK_STATUS_SPEED_MASK) >> PCIE_LINK_STATUS_SPEED_OFF;
  112. }
  113. static int pcie_dw_get_link_width(struct pcie_dw_ti *pci)
  114. {
  115. return (readl(pci->dbi_base + PCIE_LINK_STATUS_REG) &
  116. PCIE_LINK_STATUS_WIDTH_MASK) >> PCIE_LINK_STATUS_WIDTH_OFF;
  117. }
  118. static void dw_pcie_writel_ob_unroll(struct pcie_dw_ti *pci, u32 index, u32 reg,
  119. u32 val)
  120. {
  121. u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
  122. void __iomem *base = pci->atu_base;
  123. writel(val, base + offset + reg);
  124. }
  125. static u32 dw_pcie_readl_ob_unroll(struct pcie_dw_ti *pci, u32 index, u32 reg)
  126. {
  127. u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
  128. void __iomem *base = pci->atu_base;
  129. return readl(base + offset + reg);
  130. }
  131. /**
  132. * pcie_dw_prog_outbound_atu_unroll() - Configure ATU for outbound accesses
  133. *
  134. * @pcie: Pointer to the PCI controller state
  135. * @index: ATU region index
  136. * @type: ATU accsess type
  137. * @cpu_addr: the physical address for the translation entry
  138. * @pci_addr: the pcie bus address for the translation entry
  139. * @size: the size of the translation entry
  140. */
  141. static void pcie_dw_prog_outbound_atu_unroll(struct pcie_dw_ti *pci, int index,
  142. int type, u64 cpu_addr,
  143. u64 pci_addr, u32 size)
  144. {
  145. u32 retries, val;
  146. debug("ATU programmed with: index: %d, type: %d, cpu addr: %8llx, pci addr: %8llx, size: %8x\n",
  147. index, type, cpu_addr, pci_addr, size);
  148. dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE,
  149. lower_32_bits(cpu_addr));
  150. dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE,
  151. upper_32_bits(cpu_addr));
  152. dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT,
  153. lower_32_bits(cpu_addr + size - 1));
  154. dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
  155. lower_32_bits(pci_addr));
  156. dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
  157. upper_32_bits(pci_addr));
  158. dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1,
  159. type);
  160. dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
  161. PCIE_ATU_ENABLE);
  162. /*
  163. * Make sure ATU enable takes effect before any subsequent config
  164. * and I/O accesses.
  165. */
  166. for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
  167. val = dw_pcie_readl_ob_unroll(pci, index,
  168. PCIE_ATU_UNR_REGION_CTRL2);
  169. if (val & PCIE_ATU_ENABLE)
  170. return;
  171. udelay(LINK_WAIT_IATU);
  172. }
  173. dev_err(pci->dev, "outbound iATU is not being enabled\n");
  174. }
  175. /**
  176. * set_cfg_address() - Configure the PCIe controller config space access
  177. *
  178. * @pcie: Pointer to the PCI controller state
  179. * @d: PCI device to access
  180. * @where: Offset in the configuration space
  181. *
  182. * Configures the PCIe controller to access the configuration space of
  183. * a specific PCIe device and returns the address to use for this
  184. * access.
  185. *
  186. * Return: Address that can be used to access the configation space
  187. * of the requested device / offset
  188. */
  189. static uintptr_t set_cfg_address(struct pcie_dw_ti *pcie,
  190. pci_dev_t d, uint where)
  191. {
  192. int bus = PCI_BUS(d) - pcie->first_busno;
  193. uintptr_t va_address;
  194. u32 atu_type;
  195. /* Use dbi_base for own configuration read and write */
  196. if (!bus) {
  197. va_address = (uintptr_t)pcie->dbi_base;
  198. goto out;
  199. }
  200. if (bus == 1)
  201. /* For local bus, change TLP Type field to 4. */
  202. atu_type = PCIE_ATU_TYPE_CFG0;
  203. else
  204. /* Otherwise, change TLP Type field to 5. */
  205. atu_type = PCIE_ATU_TYPE_CFG1;
  206. /*
  207. * Not accessing root port configuration space?
  208. * Region #0 is used for Outbound CFG space access.
  209. * Direction = Outbound
  210. * Region Index = 0
  211. */
  212. d = PCI_MASK_BUS(d);
  213. d = PCI_ADD_BUS(bus, d);
  214. pcie_dw_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1,
  215. atu_type, (u64)pcie->cfg_base,
  216. d << 8, pcie->cfg_size);
  217. va_address = (uintptr_t)pcie->cfg_base;
  218. out:
  219. va_address += where & ~0x3;
  220. return va_address;
  221. }
  222. /**
  223. * pcie_dw_addr_valid() - Check for valid bus address
  224. *
  225. * @d: The PCI device to access
  226. * @first_busno: Bus number of the PCIe controller root complex
  227. *
  228. * Return 1 (true) if the PCI device can be accessed by this controller.
  229. *
  230. * Return: 1 on valid, 0 on invalid
  231. */
  232. static int pcie_dw_addr_valid(pci_dev_t d, int first_busno)
  233. {
  234. if ((PCI_BUS(d) == first_busno) && (PCI_DEV(d) > 0))
  235. return 0;
  236. if ((PCI_BUS(d) == first_busno + 1) && (PCI_DEV(d) > 0))
  237. return 0;
  238. return 1;
  239. }
  240. /**
  241. * pcie_dw_ti_read_config() - Read from configuration space
  242. *
  243. * @bus: Pointer to the PCI bus
  244. * @bdf: Identifies the PCIe device to access
  245. * @offset: The offset into the device's configuration space
  246. * @valuep: A pointer at which to store the read value
  247. * @size: Indicates the size of access to perform
  248. *
  249. * Read a value of size @size from offset @offset within the configuration
  250. * space of the device identified by the bus, device & function numbers in @bdf
  251. * on the PCI bus @bus.
  252. *
  253. * Return: 0 on success
  254. */
  255. static int pcie_dw_ti_read_config(const struct udevice *bus, pci_dev_t bdf,
  256. uint offset, ulong *valuep,
  257. enum pci_size_t size)
  258. {
  259. struct pcie_dw_ti *pcie = dev_get_priv(bus);
  260. uintptr_t va_address;
  261. ulong value;
  262. debug("PCIE CFG read: bdf=%2x:%2x:%2x ",
  263. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
  264. if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {
  265. debug("- out of range\n");
  266. *valuep = pci_get_ff(size);
  267. return 0;
  268. }
  269. va_address = set_cfg_address(pcie, bdf, offset);
  270. value = readl(va_address);
  271. debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
  272. *valuep = pci_conv_32_to_size(value, offset, size);
  273. pcie_dw_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1,
  274. PCIE_ATU_TYPE_IO, pcie->io.phys_start,
  275. pcie->io.bus_start, pcie->io.size);
  276. return 0;
  277. }
  278. /**
  279. * pcie_dw_ti_write_config() - Write to configuration space
  280. *
  281. * @bus: Pointer to the PCI bus
  282. * @bdf: Identifies the PCIe device to access
  283. * @offset: The offset into the device's configuration space
  284. * @value: The value to write
  285. * @size: Indicates the size of access to perform
  286. *
  287. * Write the value @value of size @size from offset @offset within the
  288. * configuration space of the device identified by the bus, device & function
  289. * numbers in @bdf on the PCI bus @bus.
  290. *
  291. * Return: 0 on success
  292. */
  293. static int pcie_dw_ti_write_config(struct udevice *bus, pci_dev_t bdf,
  294. uint offset, ulong value,
  295. enum pci_size_t size)
  296. {
  297. struct pcie_dw_ti *pcie = dev_get_priv(bus);
  298. uintptr_t va_address;
  299. ulong old;
  300. debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
  301. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
  302. debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
  303. if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {
  304. debug("- out of range\n");
  305. return 0;
  306. }
  307. va_address = set_cfg_address(pcie, bdf, offset);
  308. old = readl(va_address);
  309. value = pci_conv_size_to_32(old, value, offset, size);
  310. writel(value, va_address);
  311. pcie_dw_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1,
  312. PCIE_ATU_TYPE_IO, pcie->io.phys_start,
  313. pcie->io.bus_start, pcie->io.size);
  314. return 0;
  315. }
  316. static inline void dw_pcie_dbi_write_enable(struct pcie_dw_ti *pci, bool en)
  317. {
  318. u32 val;
  319. val = readl(pci->dbi_base + PCIE_MISC_CONTROL_1_OFF);
  320. if (en)
  321. val |= PCIE_DBI_RO_WR_EN;
  322. else
  323. val &= ~PCIE_DBI_RO_WR_EN;
  324. writel(val, pci->dbi_base + PCIE_MISC_CONTROL_1_OFF);
  325. }
  326. /**
  327. * pcie_dw_configure() - Configure link capabilities and speed
  328. *
  329. * @regs_base: A pointer to the PCIe controller registers
  330. * @cap_speed: The capabilities and speed to configure
  331. *
  332. * Configure the link capabilities and speed in the PCIe root complex.
  333. */
  334. static void pcie_dw_configure(struct pcie_dw_ti *pci, u32 cap_speed)
  335. {
  336. u32 val;
  337. dw_pcie_dbi_write_enable(pci, true);
  338. val = readl(pci->dbi_base + PCIE_LINK_CAPABILITY);
  339. val &= ~TARGET_LINK_SPEED_MASK;
  340. val |= cap_speed;
  341. writel(val, pci->dbi_base + PCIE_LINK_CAPABILITY);
  342. val = readl(pci->dbi_base + PCIE_LINK_CTL_2);
  343. val &= ~TARGET_LINK_SPEED_MASK;
  344. val |= cap_speed;
  345. writel(val, pci->dbi_base + PCIE_LINK_CTL_2);
  346. dw_pcie_dbi_write_enable(pci, false);
  347. }
  348. /**
  349. * is_link_up() - Return the link state
  350. *
  351. * @regs_base: A pointer to the PCIe DBICS registers
  352. *
  353. * Return: 1 (true) for active line and 0 (false) for no link
  354. */
  355. static int is_link_up(struct pcie_dw_ti *pci)
  356. {
  357. u32 val;
  358. val = readl(pci->dbi_base + PCIE_PORT_DEBUG0);
  359. val &= PORT_LOGIC_LTSSM_STATE_MASK;
  360. return (val == PORT_LOGIC_LTSSM_STATE_L0);
  361. }
  362. /**
  363. * wait_link_up() - Wait for the link to come up
  364. *
  365. * @regs_base: A pointer to the PCIe controller registers
  366. *
  367. * Return: 1 (true) for active line and 0 (false) for no link (timeout)
  368. */
  369. static int wait_link_up(struct pcie_dw_ti *pci)
  370. {
  371. unsigned long timeout;
  372. timeout = get_timer(0) + PCIE_LINK_UP_TIMEOUT_MS;
  373. while (!is_link_up(pci)) {
  374. if (get_timer(0) > timeout)
  375. return 0;
  376. };
  377. return 1;
  378. }
  379. static int pcie_dw_ti_pcie_link_up(struct pcie_dw_ti *pci, u32 cap_speed)
  380. {
  381. u32 val;
  382. if (is_link_up(pci)) {
  383. printf("PCI Link already up before configuration!\n");
  384. return 1;
  385. }
  386. /* DW pre link configurations */
  387. pcie_dw_configure(pci, cap_speed);
  388. /* Initiate link training */
  389. val = readl(pci->app_base + PCIE_CMD_STATUS);
  390. val |= LTSSM_EN_VAL;
  391. writel(val, pci->app_base + PCIE_CMD_STATUS);
  392. /* Check that link was established */
  393. if (!wait_link_up(pci))
  394. return 0;
  395. /*
  396. * Link can be established in Gen 1. still need to wait
  397. * till MAC nagaotiation is completed
  398. */
  399. udelay(100);
  400. return 1;
  401. }
  402. /**
  403. * pcie_dw_setup_host() - Setup the PCIe controller for RC opertaion
  404. *
  405. * @pcie: Pointer to the PCI controller state
  406. *
  407. * Configure the host BARs of the PCIe controller root port so that
  408. * PCI(e) devices may access the system memory.
  409. */
  410. static void pcie_dw_setup_host(struct pcie_dw_ti *pci)
  411. {
  412. u32 val;
  413. /* setup RC BARs */
  414. writel(PCI_BASE_ADDRESS_MEM_TYPE_64,
  415. pci->dbi_base + PCI_BASE_ADDRESS_0);
  416. writel(0x0, pci->dbi_base + PCI_BASE_ADDRESS_1);
  417. /* setup interrupt pins */
  418. dw_pcie_dbi_write_enable(pci, true);
  419. val = readl(pci->dbi_base + PCI_INTERRUPT_LINE);
  420. val &= 0xffff00ff;
  421. val |= 0x00000100;
  422. writel(val, pci->dbi_base + PCI_INTERRUPT_LINE);
  423. dw_pcie_dbi_write_enable(pci, false);
  424. /* setup bus numbers */
  425. val = readl(pci->dbi_base + PCI_PRIMARY_BUS);
  426. val &= 0xff000000;
  427. val |= 0x00ff0100;
  428. writel(val, pci->dbi_base + PCI_PRIMARY_BUS);
  429. /* setup command register */
  430. val = readl(pci->dbi_base + PCI_COMMAND);
  431. val &= 0xffff0000;
  432. val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
  433. PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
  434. writel(val, pci->dbi_base + PCI_COMMAND);
  435. /* Enable write permission for the DBI read-only register */
  436. dw_pcie_dbi_write_enable(pci, true);
  437. /* program correct class for RC */
  438. writew(PCI_CLASS_BRIDGE_PCI, pci->dbi_base + PCI_CLASS_DEVICE);
  439. /* Better disable write permission right after the update */
  440. dw_pcie_dbi_write_enable(pci, false);
  441. val = readl(pci->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
  442. val |= PORT_LOGIC_SPEED_CHANGE;
  443. writel(val, pci->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
  444. }
  445. static int pcie_am654_set_mode(struct pcie_dw_ti *pci,
  446. enum dw_pcie_device_mode mode)
  447. {
  448. struct regmap *syscon;
  449. u32 val;
  450. u32 mask;
  451. int ret;
  452. syscon = syscon_regmap_lookup_by_phandle(pci->dev,
  453. "ti,syscon-pcie-mode");
  454. if (IS_ERR(syscon))
  455. return 0;
  456. mask = AM654_PCIE_DEV_TYPE_MASK;
  457. switch (mode) {
  458. case DW_PCIE_RC_TYPE:
  459. val = RC;
  460. break;
  461. case DW_PCIE_EP_TYPE:
  462. val = EP;
  463. break;
  464. default:
  465. dev_err(pci->dev, "INVALID device type %d\n", mode);
  466. return -EINVAL;
  467. }
  468. ret = regmap_update_bits(syscon, 0, mask, val);
  469. if (ret) {
  470. dev_err(pci->dev, "failed to set pcie mode\n");
  471. return ret;
  472. }
  473. return 0;
  474. }
  475. static int pcie_dw_init_id(struct pcie_dw_ti *pci)
  476. {
  477. struct regmap *devctrl_regs;
  478. unsigned int id;
  479. int ret;
  480. devctrl_regs = syscon_regmap_lookup_by_phandle(pci->dev,
  481. "ti,syscon-pcie-id");
  482. if (IS_ERR(devctrl_regs))
  483. return PTR_ERR(devctrl_regs);
  484. ret = regmap_read(devctrl_regs, 0, &id);
  485. if (ret)
  486. return ret;
  487. dw_pcie_dbi_write_enable(pci, true);
  488. writew(id & PCIE_VENDORID_MASK, pci->dbi_base + PCI_VENDOR_ID);
  489. writew(id >> PCIE_DEVICEID_SHIFT, pci->dbi_base + PCI_DEVICE_ID);
  490. dw_pcie_dbi_write_enable(pci, false);
  491. return 0;
  492. }
  493. /**
  494. * pcie_dw_ti_probe() - Probe the PCIe bus for active link
  495. *
  496. * @dev: A pointer to the device being operated on
  497. *
  498. * Probe for an active link on the PCIe bus and configure the controller
  499. * to enable this port.
  500. *
  501. * Return: 0 on success, else -ENODEV
  502. */
  503. static int pcie_dw_ti_probe(struct udevice *dev)
  504. {
  505. struct pcie_dw_ti *pci = dev_get_priv(dev);
  506. struct udevice *ctlr = pci_get_controller(dev);
  507. struct pci_controller *hose = dev_get_uclass_priv(ctlr);
  508. struct power_domain pci_pwrdmn;
  509. struct phy phy0, phy1;
  510. int ret;
  511. ret = power_domain_get_by_index(dev, &pci_pwrdmn, 0);
  512. if (ret) {
  513. dev_err(dev, "failed to get power domain\n");
  514. return ret;
  515. }
  516. ret = power_domain_on(&pci_pwrdmn);
  517. if (ret) {
  518. dev_err(dev, "Power domain on failed\n");
  519. return ret;
  520. }
  521. ret = generic_phy_get_by_name(dev, "pcie-phy0", &phy0);
  522. if (ret) {
  523. dev_err(dev, "Unable to get phy0");
  524. return ret;
  525. }
  526. generic_phy_reset(&phy0);
  527. generic_phy_init(&phy0);
  528. generic_phy_power_on(&phy0);
  529. ret = generic_phy_get_by_name(dev, "pcie-phy1", &phy1);
  530. if (ret) {
  531. dev_err(dev, "Unable to get phy1");
  532. return ret;
  533. }
  534. generic_phy_reset(&phy1);
  535. generic_phy_init(&phy1);
  536. generic_phy_power_on(&phy1);
  537. pci->first_busno = dev->seq;
  538. pci->dev = dev;
  539. pcie_dw_setup_host(pci);
  540. pcie_dw_init_id(pci);
  541. if (device_is_compatible(dev, "ti,am654-pcie-rc"))
  542. pcie_am654_set_mode(pci, DW_PCIE_RC_TYPE);
  543. if (!pcie_dw_ti_pcie_link_up(pci, LINK_SPEED_GEN_2)) {
  544. printf("PCIE-%d: Link down\n", dev->seq);
  545. return -ENODEV;
  546. }
  547. printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", dev->seq,
  548. pcie_dw_get_link_speed(pci),
  549. pcie_dw_get_link_width(pci),
  550. hose->first_busno);
  551. /* Store the IO and MEM windows settings for future use by the ATU */
  552. pci->io.phys_start = hose->regions[0].phys_start; /* IO base */
  553. pci->io.bus_start = hose->regions[0].bus_start; /* IO_bus_addr */
  554. pci->io.size = hose->regions[0].size; /* IO size */
  555. pci->mem.phys_start = hose->regions[1].phys_start; /* MEM base */
  556. pci->mem.bus_start = hose->regions[1].bus_start; /* MEM_bus_addr */
  557. pci->mem.size = hose->regions[1].size; /* MEM size */
  558. pcie_dw_prog_outbound_atu_unroll(pci, PCIE_ATU_REGION_INDEX0,
  559. PCIE_ATU_TYPE_MEM,
  560. pci->mem.phys_start,
  561. pci->mem.bus_start, pci->mem.size);
  562. return 0;
  563. }
  564. /**
  565. * pcie_dw_ti_ofdata_to_platdata() - Translate from DT to device state
  566. *
  567. * @dev: A pointer to the device being operated on
  568. *
  569. * Translate relevant data from the device tree pertaining to device @dev into
  570. * state that the driver will later make use of. This state is stored in the
  571. * device's private data structure.
  572. *
  573. * Return: 0 on success, else -EINVAL
  574. */
  575. static int pcie_dw_ti_ofdata_to_platdata(struct udevice *dev)
  576. {
  577. struct pcie_dw_ti *pcie = dev_get_priv(dev);
  578. /* Get the controller base address */
  579. pcie->dbi_base = (void *)dev_read_addr_name(dev, "dbics");
  580. if ((fdt_addr_t)pcie->dbi_base == FDT_ADDR_T_NONE)
  581. return -EINVAL;
  582. /* Get the config space base address and size */
  583. pcie->cfg_base = (void *)dev_read_addr_size_name(dev, "config",
  584. &pcie->cfg_size);
  585. if ((fdt_addr_t)pcie->cfg_base == FDT_ADDR_T_NONE)
  586. return -EINVAL;
  587. /* Get the iATU base address and size */
  588. pcie->atu_base = (void *)dev_read_addr_name(dev, "atu");
  589. if ((fdt_addr_t)pcie->atu_base == FDT_ADDR_T_NONE)
  590. return -EINVAL;
  591. /* Get the app base address and size */
  592. pcie->app_base = (void *)dev_read_addr_name(dev, "app");
  593. if ((fdt_addr_t)pcie->app_base == FDT_ADDR_T_NONE)
  594. return -EINVAL;
  595. return 0;
  596. }
  597. static const struct dm_pci_ops pcie_dw_ti_ops = {
  598. .read_config = pcie_dw_ti_read_config,
  599. .write_config = pcie_dw_ti_write_config,
  600. };
  601. static const struct udevice_id pcie_dw_ti_ids[] = {
  602. { .compatible = "ti,am654-pcie-rc" },
  603. { }
  604. };
  605. U_BOOT_DRIVER(pcie_dw_ti) = {
  606. .name = "pcie_dw_ti",
  607. .id = UCLASS_PCI,
  608. .of_match = pcie_dw_ti_ids,
  609. .ops = &pcie_dw_ti_ops,
  610. .ofdata_to_platdata = pcie_dw_ti_ofdata_to_platdata,
  611. .probe = pcie_dw_ti_probe,
  612. .priv_auto_alloc_size = sizeof(struct pcie_dw_ti),
  613. };