pci_sh7780.c 2.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * SH7780 PCI Controller (PCIC) for U-Boot.
  4. * (C) Dustin McIntire (dustin@sensoria.com)
  5. * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
  6. * (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
  7. */
  8. #include <common.h>
  9. #include <pci.h>
  10. #include <asm/processor.h>
  11. #include <asm/pci.h>
  12. #include <asm/io.h>
  13. #define SH7780_VENDOR_ID 0x1912
  14. #define SH7780_DEVICE_ID 0x0002
  15. #define SH7780_PCICR_PREFIX 0xA5000000
  16. #define SH7780_PCICR_PFCS 0x00000800
  17. #define SH7780_PCICR_FTO 0x00000400
  18. #define SH7780_PCICR_PFE 0x00000200
  19. #define SH7780_PCICR_TBS 0x00000100
  20. #define SH7780_PCICR_ARBM 0x00000040
  21. #define SH7780_PCICR_IOCS 0x00000004
  22. #define SH7780_PCICR_PRST 0x00000002
  23. #define SH7780_PCICR_CFIN 0x00000001
  24. #define p4_in(addr) (*(vu_long *)addr)
  25. #define p4_out(data, addr) (*(vu_long *)addr) = (data)
  26. #define p4_inw(addr) (*(vu_short *)addr)
  27. #define p4_outw(data, addr) (*(vu_short *)addr) = (data)
  28. int pci_sh4_read_config_dword(struct pci_controller *hose,
  29. pci_dev_t dev, int offset, u32 *value)
  30. {
  31. u32 par_data = 0x80000000 | dev;
  32. p4_out(par_data | (offset & 0xfc), SH7780_PCIPAR);
  33. *value = p4_in(SH7780_PCIPDR);
  34. return 0;
  35. }
  36. int pci_sh4_write_config_dword(struct pci_controller *hose,
  37. pci_dev_t dev, int offset, u32 value)
  38. {
  39. u32 par_data = 0x80000000 | dev;
  40. p4_out(par_data | (offset & 0xfc), SH7780_PCIPAR);
  41. p4_out(value, SH7780_PCIPDR);
  42. return 0;
  43. }
  44. int pci_sh7780_init(struct pci_controller *hose)
  45. {
  46. p4_out(0x01, SH7780_PCIECR);
  47. if (p4_inw(SH7780_PCIVID) != SH7780_VENDOR_ID
  48. && p4_inw(SH7780_PCIDID) != SH7780_DEVICE_ID) {
  49. printf("PCI: Unknown PCI host bridge.\n");
  50. return -1;
  51. }
  52. printf("PCI: SH7780 PCI host bridge found.\n");
  53. /* Toggle PCI reset pin */
  54. p4_out((SH7780_PCICR_PREFIX | SH7780_PCICR_PRST), SH7780_PCICR);
  55. udelay(100000);
  56. p4_out(SH7780_PCICR_PREFIX, SH7780_PCICR);
  57. p4_outw(0x0047, SH7780_PCICMD);
  58. p4_out(CONFIG_SH7780_PCI_LSR, SH7780_PCILSR0);
  59. p4_out(CONFIG_SH7780_PCI_LAR, SH7780_PCILAR0);
  60. p4_out(0x00000000, SH7780_PCILSR1);
  61. p4_out(0, SH7780_PCILAR1);
  62. p4_out(CONFIG_SH7780_PCI_BAR, SH7780_PCIMBAR0);
  63. p4_out(0x00000000, SH7780_PCIMBAR1);
  64. p4_out(0xFD000000, SH7780_PCIMBR0);
  65. p4_out(0x00FC0000, SH7780_PCIMBMR0);
  66. /* if use Operand Cache then enable PCICSCR Soonp bits. */
  67. p4_out(0x08000000, SH7780_PCICSAR0);
  68. p4_out(0x0000001B, SH7780_PCICSCR0); /* Snoop bit :On */
  69. p4_out((SH7780_PCICR_PREFIX | SH7780_PCICR_CFIN | SH7780_PCICR_ARBM
  70. | SH7780_PCICR_FTO | SH7780_PCICR_PFCS | SH7780_PCICR_PFE),
  71. SH7780_PCICR);
  72. pci_sh4_init(hose);
  73. return 0;
  74. }