pci_mvebu.c 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * PCIe driver for Marvell MVEBU SoCs
  4. *
  5. * Based on Barebox drivers/pci/pci-mvebu.c
  6. *
  7. * Ported to U-Boot by:
  8. * Anton Schubert <anton.schubert@gmx.de>
  9. * Stefan Roese <sr@denx.de>
  10. */
  11. #include <common.h>
  12. #include <dm.h>
  13. #include <malloc.h>
  14. #include <dm/device-internal.h>
  15. #include <dm/lists.h>
  16. #include <dm/of_access.h>
  17. #include <pci.h>
  18. #include <asm/io.h>
  19. #include <asm/arch/cpu.h>
  20. #include <asm/arch/soc.h>
  21. #include <linux/errno.h>
  22. #include <linux/ioport.h>
  23. #include <linux/mbus.h>
  24. DECLARE_GLOBAL_DATA_PTR;
  25. /* PCIe unit register offsets */
  26. #define SELECT(x, n) ((x >> n) & 1UL)
  27. #define PCIE_DEV_ID_OFF 0x0000
  28. #define PCIE_CMD_OFF 0x0004
  29. #define PCIE_DEV_REV_OFF 0x0008
  30. #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
  31. #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
  32. #define PCIE_CAPAB_OFF 0x0060
  33. #define PCIE_CTRL_STAT_OFF 0x0068
  34. #define PCIE_HEADER_LOG_4_OFF 0x0128
  35. #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
  36. #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
  37. #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
  38. #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
  39. #define PCIE_WIN5_CTRL_OFF 0x1880
  40. #define PCIE_WIN5_BASE_OFF 0x1884
  41. #define PCIE_WIN5_REMAP_OFF 0x188c
  42. #define PCIE_CONF_ADDR_OFF 0x18f8
  43. #define PCIE_CONF_ADDR_EN BIT(31)
  44. #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
  45. #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
  46. #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
  47. #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
  48. #define PCIE_CONF_ADDR(dev, reg) \
  49. (PCIE_CONF_BUS(PCI_BUS(dev)) | PCIE_CONF_DEV(PCI_DEV(dev)) | \
  50. PCIE_CONF_FUNC(PCI_FUNC(dev)) | PCIE_CONF_REG(reg) | \
  51. PCIE_CONF_ADDR_EN)
  52. #define PCIE_CONF_DATA_OFF 0x18fc
  53. #define PCIE_MASK_OFF 0x1910
  54. #define PCIE_MASK_ENABLE_INTS (0xf << 24)
  55. #define PCIE_CTRL_OFF 0x1a00
  56. #define PCIE_CTRL_X1_MODE BIT(0)
  57. #define PCIE_STAT_OFF 0x1a04
  58. #define PCIE_STAT_BUS (0xff << 8)
  59. #define PCIE_STAT_DEV (0x1f << 16)
  60. #define PCIE_STAT_LINK_DOWN BIT(0)
  61. #define PCIE_DEBUG_CTRL 0x1a60
  62. #define PCIE_DEBUG_SOFT_RESET BIT(20)
  63. struct mvebu_pcie {
  64. struct pci_controller hose;
  65. void __iomem *base;
  66. void __iomem *membase;
  67. struct resource mem;
  68. void __iomem *iobase;
  69. u32 port;
  70. u32 lane;
  71. int devfn;
  72. u32 lane_mask;
  73. pci_dev_t dev;
  74. char name[16];
  75. unsigned int mem_target;
  76. unsigned int mem_attr;
  77. };
  78. /*
  79. * MVEBU PCIe controller needs MEMORY and I/O BARs to be mapped
  80. * into SoCs address space. Each controller will map 128M of MEM
  81. * and 64K of I/O space when registered.
  82. */
  83. static void __iomem *mvebu_pcie_membase = (void __iomem *)MBUS_PCI_MEM_BASE;
  84. #define PCIE_MEM_SIZE (128 << 20)
  85. static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie)
  86. {
  87. u32 val;
  88. val = readl(pcie->base + PCIE_STAT_OFF);
  89. return !(val & PCIE_STAT_LINK_DOWN);
  90. }
  91. static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie *pcie, int busno)
  92. {
  93. u32 stat;
  94. stat = readl(pcie->base + PCIE_STAT_OFF);
  95. stat &= ~PCIE_STAT_BUS;
  96. stat |= busno << 8;
  97. writel(stat, pcie->base + PCIE_STAT_OFF);
  98. }
  99. static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie *pcie, int devno)
  100. {
  101. u32 stat;
  102. stat = readl(pcie->base + PCIE_STAT_OFF);
  103. stat &= ~PCIE_STAT_DEV;
  104. stat |= devno << 16;
  105. writel(stat, pcie->base + PCIE_STAT_OFF);
  106. }
  107. static int mvebu_pcie_get_local_bus_nr(struct mvebu_pcie *pcie)
  108. {
  109. u32 stat;
  110. stat = readl(pcie->base + PCIE_STAT_OFF);
  111. return (stat & PCIE_STAT_BUS) >> 8;
  112. }
  113. static int mvebu_pcie_get_local_dev_nr(struct mvebu_pcie *pcie)
  114. {
  115. u32 stat;
  116. stat = readl(pcie->base + PCIE_STAT_OFF);
  117. return (stat & PCIE_STAT_DEV) >> 16;
  118. }
  119. static inline struct mvebu_pcie *hose_to_pcie(struct pci_controller *hose)
  120. {
  121. return container_of(hose, struct mvebu_pcie, hose);
  122. }
  123. static int mvebu_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
  124. uint offset, ulong *valuep,
  125. enum pci_size_t size)
  126. {
  127. struct mvebu_pcie *pcie = dev_get_platdata(bus);
  128. int local_bus = PCI_BUS(pcie->dev);
  129. int local_dev = PCI_DEV(pcie->dev);
  130. u32 reg;
  131. u32 data;
  132. debug("PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
  133. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
  134. /* Only allow one other device besides the local one on the local bus */
  135. if (PCI_BUS(bdf) == local_bus && PCI_DEV(bdf) != local_dev) {
  136. if (local_dev == 0 && PCI_DEV(bdf) != 1) {
  137. debug("- out of range\n");
  138. /*
  139. * If local dev is 0, the first other dev can
  140. * only be 1
  141. */
  142. *valuep = pci_get_ff(size);
  143. return 0;
  144. } else if (local_dev != 0 && PCI_DEV(bdf) != 0) {
  145. debug("- out of range\n");
  146. /*
  147. * If local dev is not 0, the first other dev can
  148. * only be 0
  149. */
  150. *valuep = pci_get_ff(size);
  151. return 0;
  152. }
  153. }
  154. /* write address */
  155. reg = PCIE_CONF_ADDR(bdf, offset);
  156. writel(reg, pcie->base + PCIE_CONF_ADDR_OFF);
  157. data = readl(pcie->base + PCIE_CONF_DATA_OFF);
  158. debug("(addr,val)=(0x%04x, 0x%08x)\n", offset, data);
  159. *valuep = pci_conv_32_to_size(data, offset, size);
  160. return 0;
  161. }
  162. static int mvebu_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
  163. uint offset, ulong value,
  164. enum pci_size_t size)
  165. {
  166. struct mvebu_pcie *pcie = dev_get_platdata(bus);
  167. int local_bus = PCI_BUS(pcie->dev);
  168. int local_dev = PCI_DEV(pcie->dev);
  169. u32 data;
  170. debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
  171. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
  172. debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
  173. /* Only allow one other device besides the local one on the local bus */
  174. if (PCI_BUS(bdf) == local_bus && PCI_DEV(bdf) != local_dev) {
  175. if (local_dev == 0 && PCI_DEV(bdf) != 1) {
  176. /*
  177. * If local dev is 0, the first other dev can
  178. * only be 1
  179. */
  180. return 0;
  181. } else if (local_dev != 0 && PCI_DEV(bdf) != 0) {
  182. /*
  183. * If local dev is not 0, the first other dev can
  184. * only be 0
  185. */
  186. return 0;
  187. }
  188. }
  189. writel(PCIE_CONF_ADDR(bdf, offset), pcie->base + PCIE_CONF_ADDR_OFF);
  190. data = pci_conv_size_to_32(0, value, offset, size);
  191. writel(data, pcie->base + PCIE_CONF_DATA_OFF);
  192. return 0;
  193. }
  194. /*
  195. * Setup PCIE BARs and Address Decode Wins:
  196. * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
  197. * WIN[0-3] -> DRAM bank[0-3]
  198. */
  199. static void mvebu_pcie_setup_wins(struct mvebu_pcie *pcie)
  200. {
  201. const struct mbus_dram_target_info *dram = mvebu_mbus_dram_info();
  202. u32 size;
  203. int i;
  204. /* First, disable and clear BARs and windows. */
  205. for (i = 1; i < 3; i++) {
  206. writel(0, pcie->base + PCIE_BAR_CTRL_OFF(i));
  207. writel(0, pcie->base + PCIE_BAR_LO_OFF(i));
  208. writel(0, pcie->base + PCIE_BAR_HI_OFF(i));
  209. }
  210. for (i = 0; i < 5; i++) {
  211. writel(0, pcie->base + PCIE_WIN04_CTRL_OFF(i));
  212. writel(0, pcie->base + PCIE_WIN04_BASE_OFF(i));
  213. writel(0, pcie->base + PCIE_WIN04_REMAP_OFF(i));
  214. }
  215. writel(0, pcie->base + PCIE_WIN5_CTRL_OFF);
  216. writel(0, pcie->base + PCIE_WIN5_BASE_OFF);
  217. writel(0, pcie->base + PCIE_WIN5_REMAP_OFF);
  218. /* Setup windows for DDR banks. Count total DDR size on the fly. */
  219. size = 0;
  220. for (i = 0; i < dram->num_cs; i++) {
  221. const struct mbus_dram_window *cs = dram->cs + i;
  222. writel(cs->base & 0xffff0000,
  223. pcie->base + PCIE_WIN04_BASE_OFF(i));
  224. writel(0, pcie->base + PCIE_WIN04_REMAP_OFF(i));
  225. writel(((cs->size - 1) & 0xffff0000) |
  226. (cs->mbus_attr << 8) |
  227. (dram->mbus_dram_target_id << 4) | 1,
  228. pcie->base + PCIE_WIN04_CTRL_OFF(i));
  229. size += cs->size;
  230. }
  231. /* Round up 'size' to the nearest power of two. */
  232. if ((size & (size - 1)) != 0)
  233. size = 1 << fls(size);
  234. /* Setup BAR[1] to all DRAM banks. */
  235. writel(dram->cs[0].base | 0xc, pcie->base + PCIE_BAR_LO_OFF(1));
  236. writel(0, pcie->base + PCIE_BAR_HI_OFF(1));
  237. writel(((size - 1) & 0xffff0000) | 0x1,
  238. pcie->base + PCIE_BAR_CTRL_OFF(1));
  239. }
  240. static int mvebu_pcie_probe(struct udevice *dev)
  241. {
  242. struct mvebu_pcie *pcie = dev_get_platdata(dev);
  243. struct udevice *ctlr = pci_get_controller(dev);
  244. struct pci_controller *hose = dev_get_uclass_priv(ctlr);
  245. static int bus;
  246. u32 reg;
  247. debug("%s: PCIe %d.%d - up, base %08x\n", __func__,
  248. pcie->port, pcie->lane, (u32)pcie->base);
  249. /* Read Id info and local bus/dev */
  250. debug("direct conf read %08x, local bus %d, local dev %d\n",
  251. readl(pcie->base), mvebu_pcie_get_local_bus_nr(pcie),
  252. mvebu_pcie_get_local_dev_nr(pcie));
  253. mvebu_pcie_set_local_bus_nr(pcie, bus);
  254. mvebu_pcie_set_local_dev_nr(pcie, 0);
  255. pcie->dev = PCI_BDF(bus, 0, 0);
  256. pcie->mem.start = (u32)mvebu_pcie_membase;
  257. pcie->mem.end = pcie->mem.start + PCIE_MEM_SIZE - 1;
  258. mvebu_pcie_membase += PCIE_MEM_SIZE;
  259. if (mvebu_mbus_add_window_by_id(pcie->mem_target, pcie->mem_attr,
  260. (phys_addr_t)pcie->mem.start,
  261. PCIE_MEM_SIZE)) {
  262. printf("PCIe unable to add mbus window for mem at %08x+%08x\n",
  263. (u32)pcie->mem.start, PCIE_MEM_SIZE);
  264. }
  265. /* Setup windows and configure host bridge */
  266. mvebu_pcie_setup_wins(pcie);
  267. /* Master + slave enable. */
  268. reg = readl(pcie->base + PCIE_CMD_OFF);
  269. reg |= PCI_COMMAND_MEMORY;
  270. reg |= PCI_COMMAND_MASTER;
  271. reg |= BIT(10); /* disable interrupts */
  272. writel(reg, pcie->base + PCIE_CMD_OFF);
  273. /* PCI memory space */
  274. pci_set_region(hose->regions + 0, pcie->mem.start,
  275. pcie->mem.start, PCIE_MEM_SIZE, PCI_REGION_MEM);
  276. pci_set_region(hose->regions + 1,
  277. 0, 0,
  278. gd->ram_size,
  279. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  280. hose->region_count = 2;
  281. /* Set BAR0 to internal registers */
  282. writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0));
  283. writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
  284. bus++;
  285. return 0;
  286. }
  287. static int mvebu_pcie_port_parse_dt(ofnode node, struct mvebu_pcie *pcie)
  288. {
  289. const u32 *addr;
  290. int len;
  291. addr = ofnode_get_property(node, "assigned-addresses", &len);
  292. if (!addr) {
  293. pr_err("property \"assigned-addresses\" not found");
  294. return -FDT_ERR_NOTFOUND;
  295. }
  296. pcie->base = (void *)(fdt32_to_cpu(addr[2]) + SOC_REGS_PHY_BASE);
  297. return 0;
  298. }
  299. #define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
  300. #define DT_TYPE_IO 0x1
  301. #define DT_TYPE_MEM32 0x2
  302. #define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
  303. #define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF)
  304. static int mvebu_get_tgt_attr(ofnode node, int devfn,
  305. unsigned long type,
  306. unsigned int *tgt,
  307. unsigned int *attr)
  308. {
  309. const int na = 3, ns = 2;
  310. const __be32 *range;
  311. int rlen, nranges, rangesz, pna, i;
  312. *tgt = -1;
  313. *attr = -1;
  314. range = ofnode_get_property(node, "ranges", &rlen);
  315. if (!range)
  316. return -EINVAL;
  317. /*
  318. * Linux uses of_n_addr_cells() to get the number of address cells
  319. * here. Currently this function is only available in U-Boot when
  320. * CONFIG_OF_LIVE is enabled. Until this is enabled for MVEBU in
  321. * general, lets't hardcode the "pna" value in the U-Boot code.
  322. */
  323. pna = 2; /* hardcoded for now because of lack of of_n_addr_cells() */
  324. rangesz = pna + na + ns;
  325. nranges = rlen / sizeof(__be32) / rangesz;
  326. for (i = 0; i < nranges; i++, range += rangesz) {
  327. u32 flags = of_read_number(range, 1);
  328. u32 slot = of_read_number(range + 1, 1);
  329. u64 cpuaddr = of_read_number(range + na, pna);
  330. unsigned long rtype;
  331. if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO)
  332. rtype = IORESOURCE_IO;
  333. else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
  334. rtype = IORESOURCE_MEM;
  335. else
  336. continue;
  337. /*
  338. * The Linux code used PCI_SLOT() here, which expects devfn
  339. * in bits 7..0. PCI_DEV() in U-Boot is similar to PCI_SLOT(),
  340. * only expects devfn in 15..8, where its saved in this driver.
  341. */
  342. if (slot == PCI_DEV(devfn) && type == rtype) {
  343. *tgt = DT_CPUADDR_TO_TARGET(cpuaddr);
  344. *attr = DT_CPUADDR_TO_ATTR(cpuaddr);
  345. return 0;
  346. }
  347. }
  348. return -ENOENT;
  349. }
  350. static int mvebu_pcie_ofdata_to_platdata(struct udevice *dev)
  351. {
  352. struct mvebu_pcie *pcie = dev_get_platdata(dev);
  353. int ret = 0;
  354. /* Get port number, lane number and memory target / attr */
  355. if (ofnode_read_u32(dev_ofnode(dev), "marvell,pcie-port",
  356. &pcie->port)) {
  357. ret = -ENODEV;
  358. goto err;
  359. }
  360. if (ofnode_read_u32(dev_ofnode(dev), "marvell,pcie-lane", &pcie->lane))
  361. pcie->lane = 0;
  362. sprintf(pcie->name, "pcie%d.%d", pcie->port, pcie->lane);
  363. /* pci_get_devfn() returns devfn in bits 15..8, see PCI_DEV usage */
  364. pcie->devfn = pci_get_devfn(dev);
  365. if (pcie->devfn < 0) {
  366. ret = -ENODEV;
  367. goto err;
  368. }
  369. ret = mvebu_get_tgt_attr(dev_ofnode(dev->parent), pcie->devfn,
  370. IORESOURCE_MEM,
  371. &pcie->mem_target, &pcie->mem_attr);
  372. if (ret < 0) {
  373. printf("%s: cannot get tgt/attr for mem window\n", pcie->name);
  374. goto err;
  375. }
  376. /* Parse PCIe controller register base from DT */
  377. ret = mvebu_pcie_port_parse_dt(dev_ofnode(dev), pcie);
  378. if (ret < 0)
  379. goto err;
  380. /* Check link and skip ports that have no link */
  381. if (!mvebu_pcie_link_up(pcie)) {
  382. debug("%s: %s - down\n", __func__, pcie->name);
  383. ret = -ENODEV;
  384. goto err;
  385. }
  386. return 0;
  387. err:
  388. return ret;
  389. }
  390. static const struct dm_pci_ops mvebu_pcie_ops = {
  391. .read_config = mvebu_pcie_read_config,
  392. .write_config = mvebu_pcie_write_config,
  393. };
  394. static struct driver pcie_mvebu_drv = {
  395. .name = "pcie_mvebu",
  396. .id = UCLASS_PCI,
  397. .ops = &mvebu_pcie_ops,
  398. .probe = mvebu_pcie_probe,
  399. .ofdata_to_platdata = mvebu_pcie_ofdata_to_platdata,
  400. .platdata_auto_alloc_size = sizeof(struct mvebu_pcie),
  401. };
  402. /*
  403. * Use a MISC device to bind the n instances (child nodes) of the
  404. * PCIe base controller in UCLASS_PCI.
  405. */
  406. static int mvebu_pcie_bind(struct udevice *parent)
  407. {
  408. struct mvebu_pcie *pcie;
  409. struct uclass_driver *drv;
  410. struct udevice *dev;
  411. ofnode subnode;
  412. /* Lookup eth driver */
  413. drv = lists_uclass_lookup(UCLASS_PCI);
  414. if (!drv) {
  415. puts("Cannot find PCI driver\n");
  416. return -ENOENT;
  417. }
  418. ofnode_for_each_subnode(subnode, dev_ofnode(parent)) {
  419. if (!ofnode_is_available(subnode))
  420. continue;
  421. pcie = calloc(1, sizeof(*pcie));
  422. if (!pcie)
  423. return -ENOMEM;
  424. /* Create child device UCLASS_PCI and bind it */
  425. device_bind_ofnode(parent, &pcie_mvebu_drv, pcie->name, pcie,
  426. subnode, &dev);
  427. }
  428. return 0;
  429. }
  430. static const struct udevice_id mvebu_pcie_ids[] = {
  431. { .compatible = "marvell,armada-xp-pcie" },
  432. { .compatible = "marvell,armada-370-pcie" },
  433. { }
  434. };
  435. U_BOOT_DRIVER(pcie_mvebu_base) = {
  436. .name = "pcie_mvebu_base",
  437. .id = UCLASS_MISC,
  438. .of_match = mvebu_pcie_ids,
  439. .bind = mvebu_pcie_bind,
  440. };