pci_msc01.c 3.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013 Imagination Technologies
  4. * Author: Paul Burton <paul.burton@mips.com>
  5. */
  6. #include <common.h>
  7. #include <msc01.h>
  8. #include <pci.h>
  9. #include <pci_msc01.h>
  10. #include <asm/io.h>
  11. #define PCI_ACCESS_READ 0
  12. #define PCI_ACCESS_WRITE 1
  13. struct msc01_pci_controller {
  14. struct pci_controller hose;
  15. void *base;
  16. };
  17. static inline struct msc01_pci_controller *
  18. hose_to_msc01(struct pci_controller *hose)
  19. {
  20. return container_of(hose, struct msc01_pci_controller, hose);
  21. }
  22. static int msc01_config_access(struct msc01_pci_controller *msc01,
  23. unsigned char access_type, pci_dev_t bdf,
  24. int where, u32 *data)
  25. {
  26. const u32 aborts = MSC01_PCI_INTSTAT_MA_MSK | MSC01_PCI_INTSTAT_TA_MSK;
  27. void *intstat = msc01->base + MSC01_PCI_INTSTAT_OFS;
  28. void *cfgdata = msc01->base + MSC01_PCI_CFGDATA_OFS;
  29. unsigned int bus = PCI_BUS(bdf);
  30. unsigned int dev = PCI_DEV(bdf);
  31. unsigned int devfn = PCI_DEV(bdf) << 3 | PCI_FUNC(bdf);
  32. /* clear abort status */
  33. __raw_writel(aborts, intstat);
  34. /* setup address */
  35. __raw_writel((bus << MSC01_PCI_CFGADDR_BNUM_SHF) |
  36. (dev << MSC01_PCI_CFGADDR_DNUM_SHF) |
  37. (devfn << MSC01_PCI_CFGADDR_FNUM_SHF) |
  38. ((where / 4) << MSC01_PCI_CFGADDR_RNUM_SHF),
  39. msc01->base + MSC01_PCI_CFGADDR_OFS);
  40. /* perform access */
  41. if (access_type == PCI_ACCESS_WRITE)
  42. __raw_writel(*data, cfgdata);
  43. else
  44. *data = __raw_readl(cfgdata);
  45. /* check for aborts */
  46. if (__raw_readl(intstat) & aborts) {
  47. /* clear abort status */
  48. __raw_writel(aborts, intstat);
  49. return -1;
  50. }
  51. return 0;
  52. }
  53. static int msc01_read_config_dword(struct pci_controller *hose, pci_dev_t dev,
  54. int where, u32 *value)
  55. {
  56. struct msc01_pci_controller *msc01 = hose_to_msc01(hose);
  57. *value = 0xffffffff;
  58. return msc01_config_access(msc01, PCI_ACCESS_READ, dev, where, value);
  59. }
  60. static int msc01_write_config_dword(struct pci_controller *hose, pci_dev_t dev,
  61. int where, u32 value)
  62. {
  63. struct msc01_pci_controller *gt = hose_to_msc01(hose);
  64. u32 data = value;
  65. return msc01_config_access(gt, PCI_ACCESS_WRITE, dev, where, &data);
  66. }
  67. void msc01_pci_init(void *base, unsigned long sys_bus, unsigned long sys_phys,
  68. unsigned long sys_size, unsigned long mem_bus,
  69. unsigned long mem_phys, unsigned long mem_size,
  70. unsigned long io_bus, unsigned long io_phys,
  71. unsigned long io_size)
  72. {
  73. static struct msc01_pci_controller global_msc01;
  74. struct msc01_pci_controller *msc01;
  75. struct pci_controller *hose;
  76. msc01 = &global_msc01;
  77. msc01->base = base;
  78. hose = &msc01->hose;
  79. hose->first_busno = 0;
  80. hose->last_busno = 0;
  81. /* System memory space */
  82. pci_set_region(&hose->regions[0], sys_bus, sys_phys, sys_size,
  83. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  84. /* PCI memory space */
  85. pci_set_region(&hose->regions[1], mem_bus, mem_phys, mem_size,
  86. PCI_REGION_MEM);
  87. /* PCI I/O space */
  88. pci_set_region(&hose->regions[2], io_bus, io_phys, io_size,
  89. PCI_REGION_IO);
  90. hose->region_count = 3;
  91. pci_set_ops(hose,
  92. pci_hose_read_config_byte_via_dword,
  93. pci_hose_read_config_word_via_dword,
  94. msc01_read_config_dword,
  95. pci_hose_write_config_byte_via_dword,
  96. pci_hose_write_config_word_via_dword,
  97. msc01_write_config_dword);
  98. pci_register_hose(hose);
  99. hose->last_busno = pci_hose_scan(hose);
  100. }