pci_mpc85xx.c 4.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * (C) Copyright 2019
  4. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  5. *
  6. */
  7. #include <common.h>
  8. #include <asm/cpm_85xx.h>
  9. #include <pci.h>
  10. #include <dm.h>
  11. #include <asm/fsl_law.h>
  12. struct mpc85xx_pci_priv {
  13. void __iomem *cfg_addr;
  14. void __iomem *cfg_data;
  15. };
  16. static int mpc85xx_pci_dm_read_config(const struct udevice *dev, pci_dev_t bdf,
  17. uint offset, ulong *value,
  18. enum pci_size_t size)
  19. {
  20. struct mpc85xx_pci_priv *priv = dev_get_priv(dev);
  21. u32 addr;
  22. addr = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
  23. out_be32(priv->cfg_addr, addr);
  24. sync();
  25. *value = pci_conv_32_to_size(in_le32(priv->cfg_data), offset, size);
  26. return 0;
  27. }
  28. static int mpc85xx_pci_dm_write_config(struct udevice *dev, pci_dev_t bdf,
  29. uint offset, ulong value,
  30. enum pci_size_t size)
  31. {
  32. struct mpc85xx_pci_priv *priv = dev_get_priv(dev);
  33. u32 addr;
  34. addr = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
  35. out_be32(priv->cfg_addr, addr);
  36. sync();
  37. out_le32(priv->cfg_data, pci_conv_size_to_32(0, value, offset, size));
  38. return 0;
  39. }
  40. static int
  41. mpc85xx_pci_dm_setup_laws(struct pci_region *io, struct pci_region *mem,
  42. struct pci_region *pre)
  43. {
  44. /*
  45. * Unfortunately we have defines for this addresse,
  46. * as we have to setup the TLB, and at this stage
  47. * we have no access to DT ... may we check here
  48. * if the value in the define is the same ?
  49. */
  50. if (mem)
  51. set_next_law(mem->phys_start, law_size_bits(mem->size),
  52. LAW_TRGT_IF_PCI);
  53. if (io)
  54. set_next_law(io->phys_start, law_size_bits(io->size),
  55. LAW_TRGT_IF_PCI);
  56. if (pre)
  57. set_next_law(pre->phys_start, law_size_bits(pre->size),
  58. LAW_TRGT_IF_PCI);
  59. return 0;
  60. }
  61. static int mpc85xx_pci_dm_probe(struct udevice *dev)
  62. {
  63. struct mpc85xx_pci_priv *priv = dev_get_priv(dev);
  64. struct pci_region *io;
  65. struct pci_region *mem;
  66. struct pci_region *pre;
  67. int count;
  68. ccsr_pcix_t *pcix;
  69. count = pci_get_regions(dev, &io, &mem, &pre);
  70. if (count != 2) {
  71. printf("%s: wrong count of regions %d only 2 allowed\n",
  72. __func__, count);
  73. return -EINVAL;
  74. }
  75. mpc85xx_pci_dm_setup_laws(io, mem, pre);
  76. pcix = priv->cfg_addr;
  77. /* BAR 1: memory */
  78. out_be32(&pcix->potar1, (mem->bus_start >> 12) & 0x000fffff);
  79. out_be32(&pcix->potear1, 0);
  80. out_be32(&pcix->powbar1, (mem->phys_start >> 12) & 0x000fffff);
  81. out_be32(&pcix->powbear1, 0);
  82. out_be32(&pcix->powar1, (POWAR_EN | POWAR_MEM_READ |
  83. POWAR_MEM_WRITE | (__ilog2(mem->size) - 1)));
  84. /* BAR 1: IO */
  85. out_be32(&pcix->potar2, (io->bus_start >> 12) & 0x000fffff);
  86. out_be32(&pcix->potear2, 0);
  87. out_be32(&pcix->powbar2, (io->phys_start >> 12) & 0x000fffff);
  88. out_be32(&pcix->powbear2, 0);
  89. out_be32(&pcix->powar2, (POWAR_EN | POWAR_IO_READ |
  90. POWAR_IO_WRITE | (__ilog2(io->size) - 1)));
  91. out_be32(&pcix->pitar1, 0);
  92. out_be32(&pcix->piwbar1, 0);
  93. out_be32(&pcix->piwar1, (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
  94. PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G));
  95. out_be32(&pcix->powar3, 0);
  96. out_be32(&pcix->powar4, 0);
  97. out_be32(&pcix->piwar2, 0);
  98. out_be32(&pcix->piwar3, 0);
  99. return 0;
  100. }
  101. static int mpc85xx_pci_dm_remove(struct udevice *dev)
  102. {
  103. return 0;
  104. }
  105. static int mpc85xx_pci_ofdata_to_platdata(struct udevice *dev)
  106. {
  107. struct mpc85xx_pci_priv *priv = dev_get_priv(dev);
  108. fdt_addr_t addr;
  109. addr = devfdt_get_addr_index(dev, 0);
  110. if (addr == FDT_ADDR_T_NONE)
  111. return -EINVAL;
  112. priv->cfg_addr = (void __iomem *)addr;
  113. addr += 4;
  114. priv->cfg_data = (void __iomem *)addr;
  115. return 0;
  116. }
  117. static const struct dm_pci_ops mpc85xx_pci_ops = {
  118. .read_config = mpc85xx_pci_dm_read_config,
  119. .write_config = mpc85xx_pci_dm_write_config,
  120. };
  121. static const struct udevice_id mpc85xx_pci_ids[] = {
  122. { .compatible = "fsl,mpc8540-pci" },
  123. { }
  124. };
  125. U_BOOT_DRIVER(mpc85xx_pci) = {
  126. .name = "mpc85xx_pci",
  127. .id = UCLASS_PCI,
  128. .of_match = mpc85xx_pci_ids,
  129. .ops = &mpc85xx_pci_ops,
  130. .probe = mpc85xx_pci_dm_probe,
  131. .remove = mpc85xx_pci_dm_remove,
  132. .ofdata_to_platdata = mpc85xx_pci_ofdata_to_platdata,
  133. .priv_auto_alloc_size = sizeof(struct mpc85xx_pci_priv),
  134. };