pci_gt64120.c 4.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
  4. *
  5. * Based on the Linux implementation.
  6. * Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc.
  7. * Authors: Carsten Langgaard <carstenl@mips.com>
  8. * Maciej W. Rozycki <macro@mips.com>
  9. */
  10. #include <common.h>
  11. #include <gt64120.h>
  12. #include <pci.h>
  13. #include <pci_gt64120.h>
  14. #include <asm/io.h>
  15. #define PCI_ACCESS_READ 0
  16. #define PCI_ACCESS_WRITE 1
  17. struct gt64120_regs {
  18. u8 unused_000[0xc18];
  19. u32 intrcause;
  20. u8 unused_c1c[0x0dc];
  21. u32 pci0_cfgaddr;
  22. u32 pci0_cfgdata;
  23. };
  24. struct gt64120_pci_controller {
  25. struct pci_controller hose;
  26. struct gt64120_regs *regs;
  27. };
  28. static inline struct gt64120_pci_controller *
  29. hose_to_gt64120(struct pci_controller *hose)
  30. {
  31. return container_of(hose, struct gt64120_pci_controller, hose);
  32. }
  33. #define GT_INTRCAUSE_ABORT_BITS \
  34. (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)
  35. static int gt_config_access(struct gt64120_pci_controller *gt,
  36. unsigned char access_type, pci_dev_t bdf,
  37. int where, u32 *data)
  38. {
  39. unsigned int bus = PCI_BUS(bdf);
  40. unsigned int dev = PCI_DEV(bdf);
  41. unsigned int devfn = PCI_DEV(bdf) << 3 | PCI_FUNC(bdf);
  42. u32 intr;
  43. u32 addr;
  44. u32 val;
  45. if (bus == 0 && dev >= 31) {
  46. /* Because of a bug in the galileo (for slot 31). */
  47. return -1;
  48. }
  49. if (access_type == PCI_ACCESS_WRITE)
  50. debug("PCI WR %02x:%02x.%x reg:%02d data:%08x\n",
  51. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), where, *data);
  52. /* Clear cause register bits */
  53. writel(~GT_INTRCAUSE_ABORT_BITS, &gt->regs->intrcause);
  54. addr = GT_PCI0_CFGADDR_CONFIGEN_BIT;
  55. addr |= bus << GT_PCI0_CFGADDR_BUSNUM_SHF;
  56. addr |= devfn << GT_PCI0_CFGADDR_FUNCTNUM_SHF;
  57. addr |= (where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF;
  58. /* Setup address */
  59. writel(addr, &gt->regs->pci0_cfgaddr);
  60. if (access_type == PCI_ACCESS_WRITE) {
  61. if (bus == 0 && dev == 0) {
  62. /*
  63. * The Galileo system controller is acting
  64. * differently than other devices.
  65. */
  66. val = *data;
  67. } else {
  68. val = cpu_to_le32(*data);
  69. }
  70. writel(val, &gt->regs->pci0_cfgdata);
  71. } else {
  72. val = readl(&gt->regs->pci0_cfgdata);
  73. if (bus == 0 && dev == 0) {
  74. /*
  75. * The Galileo system controller is acting
  76. * differently than other devices.
  77. */
  78. *data = val;
  79. } else {
  80. *data = le32_to_cpu(val);
  81. }
  82. }
  83. /* Check for master or target abort */
  84. intr = readl(&gt->regs->intrcause);
  85. if (intr & GT_INTRCAUSE_ABORT_BITS) {
  86. /* Error occurred, clear abort bits */
  87. writel(~GT_INTRCAUSE_ABORT_BITS, &gt->regs->intrcause);
  88. return -1;
  89. }
  90. if (access_type == PCI_ACCESS_READ)
  91. debug("PCI RD %02x:%02x.%x reg:%02d data:%08x\n",
  92. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), where, *data);
  93. return 0;
  94. }
  95. static int gt_read_config_dword(struct pci_controller *hose, pci_dev_t dev,
  96. int where, u32 *value)
  97. {
  98. struct gt64120_pci_controller *gt = hose_to_gt64120(hose);
  99. *value = 0xffffffff;
  100. return gt_config_access(gt, PCI_ACCESS_READ, dev, where, value);
  101. }
  102. static int gt_write_config_dword(struct pci_controller *hose, pci_dev_t dev,
  103. int where, u32 value)
  104. {
  105. struct gt64120_pci_controller *gt = hose_to_gt64120(hose);
  106. u32 data = value;
  107. return gt_config_access(gt, PCI_ACCESS_WRITE, dev, where, &data);
  108. }
  109. void gt64120_pci_init(void *regs, unsigned long sys_bus, unsigned long sys_phys,
  110. unsigned long sys_size, unsigned long mem_bus,
  111. unsigned long mem_phys, unsigned long mem_size,
  112. unsigned long io_bus, unsigned long io_phys,
  113. unsigned long io_size)
  114. {
  115. static struct gt64120_pci_controller global_gt;
  116. struct gt64120_pci_controller *gt;
  117. struct pci_controller *hose;
  118. gt = &global_gt;
  119. gt->regs = regs;
  120. hose = &gt->hose;
  121. hose->first_busno = 0;
  122. hose->last_busno = 0;
  123. /* System memory space */
  124. pci_set_region(&hose->regions[0], sys_bus, sys_phys, sys_size,
  125. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  126. /* PCI memory space */
  127. pci_set_region(&hose->regions[1], mem_bus, mem_phys, mem_size,
  128. PCI_REGION_MEM);
  129. /* PCI I/O space */
  130. pci_set_region(&hose->regions[2], io_bus, io_phys, io_size,
  131. PCI_REGION_IO);
  132. hose->region_count = 3;
  133. pci_set_ops(hose,
  134. pci_hose_read_config_byte_via_dword,
  135. pci_hose_read_config_word_via_dword,
  136. gt_read_config_dword,
  137. pci_hose_write_config_byte_via_dword,
  138. pci_hose_write_config_word_via_dword,
  139. gt_write_config_dword);
  140. pci_register_hose(hose);
  141. hose->last_busno = pci_hose_scan(hose);
  142. }