pci_ftpci100.c 8.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Faraday FTPCI100 PCI Bridge Controller Device Driver Implementation
  4. *
  5. * Copyright (C) 2011 Andes Technology Corporation
  6. * Gavin Guo, Andes Technology Corporation <gavinguo@andestech.com>
  7. * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
  8. */
  9. #include <common.h>
  10. #include <malloc.h>
  11. #include <pci.h>
  12. #include <faraday/ftpci100.h>
  13. #include <asm/io.h>
  14. #include <asm/types.h> /* u32, u16.... used by pci.h */
  15. struct ftpci100_data {
  16. unsigned int reg_base;
  17. unsigned int io_base;
  18. unsigned int mem_base;
  19. unsigned int mmio_base;
  20. unsigned int ndevs;
  21. };
  22. static struct pci_config devs[FTPCI100_MAX_FUNCTIONS];
  23. static struct pci_controller local_hose;
  24. static void setup_pci_bar(unsigned int bus, unsigned int dev, unsigned func,
  25. unsigned char header, struct ftpci100_data *priv)
  26. {
  27. struct pci_controller *hose = (struct pci_controller *)&local_hose;
  28. unsigned int i, tmp32, bar_no, iovsmem = 1;
  29. pci_dev_t dev_nu;
  30. /* A device is present, add an entry to the array */
  31. devs[priv->ndevs].bus = bus;
  32. devs[priv->ndevs].dev = dev;
  33. devs[priv->ndevs].func = func;
  34. dev_nu = PCI_BDF(bus, dev, func);
  35. if ((header & 0x7f) == 0x01)
  36. /* PCI-PCI Bridge */
  37. bar_no = 2;
  38. else
  39. bar_no = 6;
  40. /* Allocate address spaces by configuring BARs */
  41. for (i = 0; i < bar_no; i++) {
  42. pci_hose_write_config_dword(hose, dev_nu,
  43. PCI_BASE_ADDRESS_0 + i * 4, 0xffffffff);
  44. pci_hose_read_config_dword(hose, dev_nu,
  45. PCI_BASE_ADDRESS_0 + i * 4, &tmp32);
  46. if (tmp32 == 0x0)
  47. continue;
  48. /* IO space */
  49. if (tmp32 & 0x1) {
  50. iovsmem = 0;
  51. unsigned int size_mask = ~(tmp32 & 0xfffffffc);
  52. if (priv->io_base & size_mask)
  53. priv->io_base = (priv->io_base & ~size_mask) + \
  54. size_mask + 1;
  55. devs[priv->ndevs].bar[i].addr = priv->io_base;
  56. devs[priv->ndevs].bar[i].size = size_mask + 1;
  57. pci_hose_write_config_dword(hose, dev_nu,
  58. PCI_BASE_ADDRESS_0 + i * 4,
  59. priv->io_base);
  60. debug("Allocated IO address 0x%X-" \
  61. "0x%X for Bus %d, Device %d, Function %d\n",
  62. priv->io_base,
  63. priv->io_base + size_mask, bus, dev, func);
  64. priv->io_base += size_mask + 1;
  65. } else {
  66. /* Memory space */
  67. unsigned int is_64bit = ((tmp32 & 0x6) == 0x4);
  68. unsigned int is_pref = tmp32 & 0x8;
  69. unsigned int size_mask = ~(tmp32 & 0xfffffff0);
  70. unsigned int alloc_base;
  71. unsigned int *addr_mem_base;
  72. if (is_pref)
  73. addr_mem_base = &priv->mem_base;
  74. else
  75. addr_mem_base = &priv->mmio_base;
  76. alloc_base = *addr_mem_base;
  77. if (alloc_base & size_mask)
  78. alloc_base = (alloc_base & ~size_mask) \
  79. + size_mask + 1;
  80. pci_hose_write_config_dword(hose, dev_nu,
  81. PCI_BASE_ADDRESS_0 + i * 4, alloc_base);
  82. debug("Allocated %s address 0x%X-" \
  83. "0x%X for Bus %d, Device %d, Function %d\n",
  84. is_pref ? "MEM" : "MMIO", alloc_base,
  85. alloc_base + size_mask, bus, dev, func);
  86. devs[priv->ndevs].bar[i].addr = alloc_base;
  87. devs[priv->ndevs].bar[i].size = size_mask + 1;
  88. debug("BAR address BAR size\n");
  89. debug("%010x %08d\n",
  90. devs[priv->ndevs].bar[0].addr,
  91. devs[priv->ndevs].bar[0].size);
  92. alloc_base += size_mask + 1;
  93. *addr_mem_base = alloc_base;
  94. if (is_64bit) {
  95. i++;
  96. pci_hose_write_config_dword(hose, dev_nu,
  97. PCI_BASE_ADDRESS_0 + i * 4, 0x0);
  98. }
  99. }
  100. }
  101. /* Enable Bus Master, Memory Space, and IO Space */
  102. pci_hose_read_config_dword(hose, dev_nu, PCI_CACHE_LINE_SIZE, &tmp32);
  103. pci_hose_write_config_dword(hose, dev_nu, PCI_CACHE_LINE_SIZE, 0x08);
  104. pci_hose_read_config_dword(hose, dev_nu, PCI_CACHE_LINE_SIZE, &tmp32);
  105. pci_hose_read_config_dword(hose, dev_nu, PCI_COMMAND, &tmp32);
  106. tmp32 &= 0xffff;
  107. if (iovsmem == 0)
  108. tmp32 |= 0x5;
  109. else
  110. tmp32 |= 0x6;
  111. pci_hose_write_config_dword(hose, dev_nu, PCI_COMMAND, tmp32);
  112. }
  113. static void pci_bus_scan(struct ftpci100_data *priv)
  114. {
  115. struct pci_controller *hose = (struct pci_controller *)&local_hose;
  116. unsigned int bus, dev, func;
  117. pci_dev_t dev_nu;
  118. unsigned int data32;
  119. unsigned int tmp;
  120. unsigned char header;
  121. unsigned char int_pin;
  122. unsigned int niobars;
  123. unsigned int nmbars;
  124. priv->ndevs = 1;
  125. nmbars = 0;
  126. niobars = 0;
  127. for (bus = 0; bus < MAX_BUS_NUM; bus++)
  128. for (dev = 0; dev < MAX_DEV_NUM; dev++)
  129. for (func = 0; func < MAX_FUN_NUM; func++) {
  130. dev_nu = PCI_BDF(bus, dev, func);
  131. pci_hose_read_config_dword(hose, dev_nu,
  132. PCI_VENDOR_ID, &data32);
  133. /*
  134. * some broken boards return 0 or ~0,
  135. * if a slot is empty.
  136. */
  137. if (data32 == 0xffffffff ||
  138. data32 == 0x00000000 ||
  139. data32 == 0x0000ffff ||
  140. data32 == 0xffff0000)
  141. continue;
  142. pci_hose_read_config_dword(hose, dev_nu,
  143. PCI_HEADER_TYPE, &tmp);
  144. header = (unsigned char)tmp;
  145. setup_pci_bar(bus, dev, func, header, priv);
  146. devs[priv->ndevs].v_id = (u16)(data32 & \
  147. 0x0000ffff);
  148. devs[priv->ndevs].d_id = (u16)((data32 & \
  149. 0xffff0000) >> 16);
  150. /* Figure out what INTX# line the card uses */
  151. pci_hose_read_config_byte(hose, dev_nu,
  152. PCI_INTERRUPT_PIN, &int_pin);
  153. /* assign the appropriate irq line */
  154. if (int_pin > PCI_IRQ_LINES) {
  155. printf("more irq lines than expect\n");
  156. } else if (int_pin != 0) {
  157. /* This device uses an interrupt line */
  158. devs[priv->ndevs].pin = int_pin;
  159. }
  160. pci_hose_read_config_dword(hose, dev_nu,
  161. PCI_CLASS_DEVICE, &data32);
  162. debug("%06d %03d %03d " \
  163. "%04d %08x %08x " \
  164. "%03d %08x %06d %08x\n",
  165. priv->ndevs, devs[priv->ndevs].bus,
  166. devs[priv->ndevs].dev,
  167. devs[priv->ndevs].func,
  168. devs[priv->ndevs].d_id,
  169. devs[priv->ndevs].v_id,
  170. devs[priv->ndevs].pin,
  171. devs[priv->ndevs].bar[0].addr,
  172. devs[priv->ndevs].bar[0].size,
  173. data32 >> 8);
  174. priv->ndevs++;
  175. }
  176. }
  177. static void ftpci_preinit(struct ftpci100_data *priv)
  178. {
  179. struct ftpci100_ahbc *ftpci100;
  180. struct pci_controller *hose = (struct pci_controller *)&local_hose;
  181. u32 pci_config_addr;
  182. u32 pci_config_data;
  183. priv->reg_base = CONFIG_FTPCI100_BASE;
  184. priv->io_base = CONFIG_FTPCI100_BASE + CONFIG_FTPCI100_IO_SIZE;
  185. priv->mmio_base = CONFIG_FTPCI100_MEM_BASE;
  186. priv->mem_base = CONFIG_FTPCI100_MEM_BASE + CONFIG_FTPCI100_MEM_SIZE;
  187. ftpci100 = (struct ftpci100_ahbc *)priv->reg_base;
  188. pci_config_addr = (u32) &ftpci100->conf;
  189. pci_config_data = (u32) &ftpci100->data;
  190. /* print device name */
  191. printf("FTPCI100\n");
  192. /* dump basic configuration */
  193. debug("%s: Config addr is %08X, data port is %08X\n",
  194. __func__, pci_config_addr, pci_config_data);
  195. /* PCI memory space */
  196. pci_set_region(hose->regions + 0,
  197. CONFIG_PCI_MEM_BUS,
  198. CONFIG_PCI_MEM_PHYS,
  199. CONFIG_PCI_MEM_SIZE,
  200. PCI_REGION_MEM);
  201. hose->region_count++;
  202. /* PCI IO space */
  203. pci_set_region(hose->regions + 1,
  204. CONFIG_PCI_IO_BUS,
  205. CONFIG_PCI_IO_PHYS,
  206. CONFIG_PCI_IO_SIZE,
  207. PCI_REGION_IO);
  208. hose->region_count++;
  209. #if defined(CONFIG_PCI_SYS_BUS)
  210. /* PCI System Memory space */
  211. pci_set_region(hose->regions + 2,
  212. CONFIG_PCI_SYS_BUS,
  213. CONFIG_PCI_SYS_PHYS,
  214. CONFIG_PCI_SYS_SIZE,
  215. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  216. hose->region_count++;
  217. #endif
  218. /* setup indirect read/write function */
  219. pci_setup_indirect(hose, pci_config_addr, pci_config_data);
  220. /* register hose */
  221. pci_register_hose(hose);
  222. }
  223. void pci_ftpci_init(void)
  224. {
  225. struct ftpci100_data *priv = NULL;
  226. struct pci_controller *hose = (struct pci_controller *)&local_hose;
  227. pci_dev_t bridge_num;
  228. struct pci_device_id bridge_ids[] = {
  229. {FTPCI100_BRIDGE_VENDORID, FTPCI100_BRIDGE_DEVICEID},
  230. {0, 0}
  231. };
  232. priv = malloc(sizeof(struct ftpci100_data));
  233. if (!priv) {
  234. printf("%s(): failed to malloc priv\n", __func__);
  235. return;
  236. }
  237. memset(priv, 0, sizeof(struct ftpci100_data));
  238. ftpci_preinit(priv);
  239. debug("Device bus dev func deviceID vendorID pin address" \
  240. " size class\n");
  241. pci_bus_scan(priv);
  242. /*
  243. * Setup the PCI Bridge Window to 1GB,
  244. * it will cause USB OHCI Host controller Unrecoverable Error
  245. * if it is not set.
  246. */
  247. bridge_num = pci_find_devices(bridge_ids, 0);
  248. if (bridge_num == -1) {
  249. printf("PCI Bridge not found\n");
  250. return;
  251. }
  252. pci_hose_write_config_dword(hose, bridge_num, PCI_MEM_BASE_SIZE1,
  253. FTPCI100_BASE_ADR_SIZE(1024));
  254. }