pci_common.c 8.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2014 Google, Inc
  4. *
  5. * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  6. * Andreas Heppel <aheppel@sysgo.de>
  7. *
  8. * (C) Copyright 2002, 2003
  9. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  10. */
  11. #include <common.h>
  12. #include <dm.h>
  13. #include <env.h>
  14. #include <errno.h>
  15. #include <pci.h>
  16. #include <asm/io.h>
  17. const char *pci_class_str(u8 class)
  18. {
  19. switch (class) {
  20. case PCI_CLASS_NOT_DEFINED:
  21. return "Build before PCI Rev2.0";
  22. break;
  23. case PCI_BASE_CLASS_STORAGE:
  24. return "Mass storage controller";
  25. break;
  26. case PCI_BASE_CLASS_NETWORK:
  27. return "Network controller";
  28. break;
  29. case PCI_BASE_CLASS_DISPLAY:
  30. return "Display controller";
  31. break;
  32. case PCI_BASE_CLASS_MULTIMEDIA:
  33. return "Multimedia device";
  34. break;
  35. case PCI_BASE_CLASS_MEMORY:
  36. return "Memory controller";
  37. break;
  38. case PCI_BASE_CLASS_BRIDGE:
  39. return "Bridge device";
  40. break;
  41. case PCI_BASE_CLASS_COMMUNICATION:
  42. return "Simple comm. controller";
  43. break;
  44. case PCI_BASE_CLASS_SYSTEM:
  45. return "Base system peripheral";
  46. break;
  47. case PCI_BASE_CLASS_INPUT:
  48. return "Input device";
  49. break;
  50. case PCI_BASE_CLASS_DOCKING:
  51. return "Docking station";
  52. break;
  53. case PCI_BASE_CLASS_PROCESSOR:
  54. return "Processor";
  55. break;
  56. case PCI_BASE_CLASS_SERIAL:
  57. return "Serial bus controller";
  58. break;
  59. case PCI_BASE_CLASS_INTELLIGENT:
  60. return "Intelligent controller";
  61. break;
  62. case PCI_BASE_CLASS_SATELLITE:
  63. return "Satellite controller";
  64. break;
  65. case PCI_BASE_CLASS_CRYPT:
  66. return "Cryptographic device";
  67. break;
  68. case PCI_BASE_CLASS_SIGNAL_PROCESSING:
  69. return "DSP";
  70. break;
  71. case PCI_CLASS_OTHERS:
  72. return "Does not fit any class";
  73. break;
  74. default:
  75. return "???";
  76. break;
  77. };
  78. }
  79. __weak int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
  80. {
  81. /*
  82. * Check if pci device should be skipped in configuration
  83. */
  84. if (dev == PCI_BDF(hose->first_busno, 0, 0)) {
  85. #if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE) /* don't skip host bridge */
  86. /*
  87. * Only skip configuration if "pciconfighost" is not set
  88. */
  89. if (env_get("pciconfighost") == NULL)
  90. return 1;
  91. #else
  92. return 1;
  93. #endif
  94. }
  95. return 0;
  96. }
  97. #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
  98. /* Get a virtual address associated with a BAR region */
  99. void *pci_map_bar(pci_dev_t pdev, int bar, int flags)
  100. {
  101. pci_addr_t pci_bus_addr;
  102. u32 bar_response;
  103. /* read BAR address */
  104. pci_read_config_dword(pdev, bar, &bar_response);
  105. pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
  106. /*
  107. * Pass "0" as the length argument to pci_bus_to_virt. The arg
  108. * isn't actualy used on any platform because u-boot assumes a static
  109. * linear mapping. In the future, this could read the BAR size
  110. * and pass that as the size if needed.
  111. */
  112. return pci_bus_to_virt(pdev, pci_bus_addr, flags, 0, MAP_NOCACHE);
  113. }
  114. void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
  115. u32 addr_and_ctrl)
  116. {
  117. int bar;
  118. bar = PCI_BASE_ADDRESS_0 + barnum * 4;
  119. pci_hose_write_config_dword(hose, dev, bar, addr_and_ctrl);
  120. }
  121. u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum)
  122. {
  123. u32 addr;
  124. int bar;
  125. bar = PCI_BASE_ADDRESS_0 + barnum * 4;
  126. pci_hose_read_config_dword(hose, dev, bar, &addr);
  127. if (addr & PCI_BASE_ADDRESS_SPACE_IO)
  128. return addr & PCI_BASE_ADDRESS_IO_MASK;
  129. else
  130. return addr & PCI_BASE_ADDRESS_MEM_MASK;
  131. }
  132. int __pci_hose_bus_to_phys(struct pci_controller *hose,
  133. pci_addr_t bus_addr,
  134. unsigned long flags,
  135. unsigned long skip_mask,
  136. phys_addr_t *pa)
  137. {
  138. struct pci_region *res;
  139. int i;
  140. for (i = 0; i < hose->region_count; i++) {
  141. res = &hose->regions[i];
  142. if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
  143. continue;
  144. if (res->flags & skip_mask)
  145. continue;
  146. if (bus_addr >= res->bus_start &&
  147. (bus_addr - res->bus_start) < res->size) {
  148. *pa = (bus_addr - res->bus_start + res->phys_start);
  149. return 0;
  150. }
  151. }
  152. return 1;
  153. }
  154. phys_addr_t pci_hose_bus_to_phys(struct pci_controller *hose,
  155. pci_addr_t bus_addr,
  156. unsigned long flags)
  157. {
  158. phys_addr_t phys_addr = 0;
  159. int ret;
  160. if (!hose) {
  161. puts("pci_hose_bus_to_phys: invalid hose\n");
  162. return phys_addr;
  163. }
  164. /*
  165. * if PCI_REGION_MEM is set we do a two pass search with preference
  166. * on matches that don't have PCI_REGION_SYS_MEMORY set
  167. */
  168. if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
  169. ret = __pci_hose_bus_to_phys(hose, bus_addr,
  170. flags, PCI_REGION_SYS_MEMORY, &phys_addr);
  171. if (!ret)
  172. return phys_addr;
  173. }
  174. ret = __pci_hose_bus_to_phys(hose, bus_addr, flags, 0, &phys_addr);
  175. if (ret)
  176. puts("pci_hose_bus_to_phys: invalid physical address\n");
  177. return phys_addr;
  178. }
  179. int __pci_hose_phys_to_bus(struct pci_controller *hose,
  180. phys_addr_t phys_addr,
  181. unsigned long flags,
  182. unsigned long skip_mask,
  183. pci_addr_t *ba)
  184. {
  185. struct pci_region *res;
  186. pci_addr_t bus_addr;
  187. int i;
  188. for (i = 0; i < hose->region_count; i++) {
  189. res = &hose->regions[i];
  190. if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
  191. continue;
  192. if (res->flags & skip_mask)
  193. continue;
  194. bus_addr = phys_addr - res->phys_start + res->bus_start;
  195. if (bus_addr >= res->bus_start &&
  196. (bus_addr - res->bus_start) < res->size) {
  197. *ba = bus_addr;
  198. return 0;
  199. }
  200. }
  201. return 1;
  202. }
  203. /*
  204. * pci_hose_phys_to_bus(): Convert physical address to bus address
  205. * @hose: PCI hose of the root PCI controller
  206. * @phys_addr: physical address to convert
  207. * @flags: flags of pci regions
  208. * @return bus address if OK, 0 on error
  209. */
  210. pci_addr_t pci_hose_phys_to_bus(struct pci_controller *hose,
  211. phys_addr_t phys_addr,
  212. unsigned long flags)
  213. {
  214. pci_addr_t bus_addr = 0;
  215. int ret;
  216. if (!hose) {
  217. puts("pci_hose_phys_to_bus: invalid hose\n");
  218. return bus_addr;
  219. }
  220. /*
  221. * if PCI_REGION_MEM is set we do a two pass search with preference
  222. * on matches that don't have PCI_REGION_SYS_MEMORY set
  223. */
  224. if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
  225. ret = __pci_hose_phys_to_bus(hose, phys_addr,
  226. flags, PCI_REGION_SYS_MEMORY, &bus_addr);
  227. if (!ret)
  228. return bus_addr;
  229. }
  230. ret = __pci_hose_phys_to_bus(hose, phys_addr, flags, 0, &bus_addr);
  231. if (ret)
  232. puts("pci_hose_phys_to_bus: invalid physical address\n");
  233. return bus_addr;
  234. }
  235. pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
  236. {
  237. struct pci_device_id ids[2] = { {}, {0, 0} };
  238. ids[0].vendor = vendor;
  239. ids[0].device = device;
  240. return pci_find_devices(ids, index);
  241. }
  242. pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum,
  243. struct pci_device_id *ids, int *indexp)
  244. {
  245. int found_multi = 0;
  246. u16 vendor, device;
  247. u8 header_type;
  248. pci_dev_t bdf;
  249. int i;
  250. for (bdf = PCI_BDF(busnum, 0, 0);
  251. bdf < PCI_BDF(busnum + 1, 0, 0);
  252. bdf += PCI_BDF(0, 0, 1)) {
  253. if (pci_skip_dev(hose, bdf))
  254. continue;
  255. if (!PCI_FUNC(bdf)) {
  256. pci_read_config_byte(bdf, PCI_HEADER_TYPE,
  257. &header_type);
  258. found_multi = header_type & 0x80;
  259. } else {
  260. if (!found_multi)
  261. continue;
  262. }
  263. pci_read_config_word(bdf, PCI_VENDOR_ID, &vendor);
  264. pci_read_config_word(bdf, PCI_DEVICE_ID, &device);
  265. for (i = 0; ids[i].vendor != 0; i++) {
  266. if (vendor == ids[i].vendor &&
  267. device == ids[i].device) {
  268. if ((*indexp) <= 0)
  269. return bdf;
  270. (*indexp)--;
  271. }
  272. }
  273. }
  274. return -1;
  275. }
  276. pci_dev_t pci_find_class(uint find_class, int index)
  277. {
  278. int bus;
  279. int devnum;
  280. pci_dev_t bdf;
  281. uint32_t class;
  282. for (bus = 0; bus <= pci_last_busno(); bus++) {
  283. for (devnum = 0; devnum < PCI_MAX_PCI_DEVICES - 1; devnum++) {
  284. pci_read_config_dword(PCI_BDF(bus, devnum, 0),
  285. PCI_CLASS_REVISION, &class);
  286. if (class >> 16 == 0xffff)
  287. continue;
  288. for (bdf = PCI_BDF(bus, devnum, 0);
  289. bdf <= PCI_BDF(bus, devnum,
  290. PCI_MAX_PCI_FUNCTIONS - 1);
  291. bdf += PCI_BDF(0, 0, 1)) {
  292. pci_read_config_dword(bdf, PCI_CLASS_REVISION,
  293. &class);
  294. class >>= 8;
  295. if (class != find_class)
  296. continue;
  297. /*
  298. * Decrement the index. We want to return the
  299. * correct device, so index is 0 for the first
  300. * matching device, 1 for the second, etc.
  301. */
  302. if (index) {
  303. index--;
  304. continue;
  305. }
  306. /* Return index'th controller. */
  307. return bdf;
  308. }
  309. }
  310. }
  311. return -ENODEV;
  312. }
  313. #endif /* !CONFIG_DM_PCI || CONFIG_DM_PCI_COMPAT */