pci_auto_old.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * PCI autoconfiguration library (legacy version, do not change)
  4. *
  5. * Author: Matt Porter <mporter@mvista.com>
  6. *
  7. * Copyright 2000 MontaVista Software Inc.
  8. */
  9. #include <common.h>
  10. #include <errno.h>
  11. #include <pci.h>
  12. /*
  13. * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
  14. * and change pci_auto.c.
  15. */
  16. /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
  17. #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
  18. #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
  19. #endif
  20. /*
  21. *
  22. */
  23. void pciauto_setup_device(struct pci_controller *hose,
  24. pci_dev_t dev, int bars_num,
  25. struct pci_region *mem,
  26. struct pci_region *prefetch,
  27. struct pci_region *io)
  28. {
  29. u32 bar_response;
  30. pci_size_t bar_size;
  31. u16 cmdstat = 0;
  32. int bar, bar_nr = 0;
  33. #ifndef CONFIG_PCI_ENUM_ONLY
  34. u8 header_type;
  35. int rom_addr;
  36. pci_addr_t bar_value;
  37. struct pci_region *bar_res;
  38. int found_mem64 = 0;
  39. #endif
  40. u16 class;
  41. pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
  42. cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
  43. for (bar = PCI_BASE_ADDRESS_0;
  44. bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
  45. /* Tickle the BAR and get the response */
  46. #ifndef CONFIG_PCI_ENUM_ONLY
  47. pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
  48. #endif
  49. pci_hose_read_config_dword(hose, dev, bar, &bar_response);
  50. /* If BAR is not implemented go to the next BAR */
  51. if (!bar_response)
  52. continue;
  53. #ifndef CONFIG_PCI_ENUM_ONLY
  54. found_mem64 = 0;
  55. #endif
  56. /* Check the BAR type and set our address mask */
  57. if (bar_response & PCI_BASE_ADDRESS_SPACE) {
  58. bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
  59. & 0xffff) + 1;
  60. #ifndef CONFIG_PCI_ENUM_ONLY
  61. bar_res = io;
  62. #endif
  63. debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
  64. bar_nr, (unsigned long long)bar_size);
  65. } else {
  66. if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
  67. PCI_BASE_ADDRESS_MEM_TYPE_64) {
  68. u32 bar_response_upper;
  69. u64 bar64;
  70. #ifndef CONFIG_PCI_ENUM_ONLY
  71. pci_hose_write_config_dword(hose, dev, bar + 4,
  72. 0xffffffff);
  73. #endif
  74. pci_hose_read_config_dword(hose, dev, bar + 4,
  75. &bar_response_upper);
  76. bar64 = ((u64)bar_response_upper << 32) | bar_response;
  77. bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
  78. #ifndef CONFIG_PCI_ENUM_ONLY
  79. found_mem64 = 1;
  80. #endif
  81. } else {
  82. bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
  83. }
  84. #ifndef CONFIG_PCI_ENUM_ONLY
  85. if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
  86. bar_res = prefetch;
  87. else
  88. bar_res = mem;
  89. debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
  90. bar_nr, bar_res == prefetch ? "Prf" : "Mem",
  91. (unsigned long long)bar_size);
  92. #endif
  93. }
  94. #ifndef CONFIG_PCI_ENUM_ONLY
  95. if (pciauto_region_allocate(bar_res, bar_size,
  96. &bar_value, found_mem64) == 0) {
  97. /* Write it out and update our limit */
  98. pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
  99. if (found_mem64) {
  100. bar += 4;
  101. #ifdef CONFIG_SYS_PCI_64BIT
  102. pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
  103. #else
  104. /*
  105. * If we are a 64-bit decoder then increment to the
  106. * upper 32 bits of the bar and force it to locate
  107. * in the lower 4GB of memory.
  108. */
  109. pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
  110. #endif
  111. }
  112. }
  113. #endif
  114. cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
  115. PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
  116. debug("\n");
  117. bar_nr++;
  118. }
  119. #ifndef CONFIG_PCI_ENUM_ONLY
  120. /* Configure the expansion ROM address */
  121. pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
  122. header_type &= 0x7f;
  123. if (header_type != PCI_HEADER_TYPE_CARDBUS) {
  124. rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
  125. PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
  126. pci_hose_write_config_dword(hose, dev, rom_addr, 0xfffffffe);
  127. pci_hose_read_config_dword(hose, dev, rom_addr, &bar_response);
  128. if (bar_response) {
  129. bar_size = -(bar_response & ~1);
  130. debug("PCI Autoconfig: ROM, size=%#x, ",
  131. (unsigned int)bar_size);
  132. if (pciauto_region_allocate(mem, bar_size,
  133. &bar_value, false) == 0) {
  134. pci_hose_write_config_dword(hose, dev, rom_addr,
  135. bar_value);
  136. }
  137. cmdstat |= PCI_COMMAND_MEMORY;
  138. debug("\n");
  139. }
  140. }
  141. #endif
  142. /* PCI_COMMAND_IO must be set for VGA device */
  143. pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
  144. if (class == PCI_CLASS_DISPLAY_VGA)
  145. cmdstat |= PCI_COMMAND_IO;
  146. pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
  147. pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
  148. CONFIG_SYS_PCI_CACHE_LINE_SIZE);
  149. pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
  150. }
  151. void pciauto_prescan_setup_bridge(struct pci_controller *hose,
  152. pci_dev_t dev, int sub_bus)
  153. {
  154. struct pci_region *pci_mem;
  155. struct pci_region *pci_prefetch;
  156. struct pci_region *pci_io;
  157. u16 cmdstat, prefechable_64;
  158. pci_mem = hose->pci_mem;
  159. pci_prefetch = hose->pci_prefetch;
  160. pci_io = hose->pci_io;
  161. pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
  162. pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
  163. &prefechable_64);
  164. prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
  165. /* Configure bus number registers */
  166. pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
  167. PCI_BUS(dev) - hose->first_busno);
  168. pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
  169. sub_bus - hose->first_busno);
  170. pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
  171. if (pci_mem) {
  172. /* Round memory allocator to 1MB boundary */
  173. pciauto_region_align(pci_mem, 0x100000);
  174. /* Set up memory and I/O filter limits, assume 32-bit I/O space */
  175. pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
  176. (pci_mem->bus_lower & 0xfff00000) >> 16);
  177. cmdstat |= PCI_COMMAND_MEMORY;
  178. }
  179. if (pci_prefetch) {
  180. /* Round memory allocator to 1MB boundary */
  181. pciauto_region_align(pci_prefetch, 0x100000);
  182. /* Set up memory and I/O filter limits, assume 32-bit I/O space */
  183. pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
  184. (pci_prefetch->bus_lower & 0xfff00000) >> 16);
  185. if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
  186. #ifdef CONFIG_SYS_PCI_64BIT
  187. pci_hose_write_config_dword(hose, dev,
  188. PCI_PREF_BASE_UPPER32,
  189. pci_prefetch->bus_lower >> 32);
  190. #else
  191. pci_hose_write_config_dword(hose, dev,
  192. PCI_PREF_BASE_UPPER32,
  193. 0x0);
  194. #endif
  195. cmdstat |= PCI_COMMAND_MEMORY;
  196. } else {
  197. /* We don't support prefetchable memory for now, so disable */
  198. pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
  199. pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
  200. if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
  201. pci_hose_write_config_word(hose, dev, PCI_PREF_BASE_UPPER32, 0x0);
  202. pci_hose_write_config_word(hose, dev, PCI_PREF_LIMIT_UPPER32, 0x0);
  203. }
  204. }
  205. if (pci_io) {
  206. /* Round I/O allocator to 4KB boundary */
  207. pciauto_region_align(pci_io, 0x1000);
  208. pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
  209. (pci_io->bus_lower & 0x0000f000) >> 8);
  210. pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
  211. (pci_io->bus_lower & 0xffff0000) >> 16);
  212. cmdstat |= PCI_COMMAND_IO;
  213. }
  214. /* Enable memory and I/O accesses, enable bus master */
  215. pci_hose_write_config_word(hose, dev, PCI_COMMAND,
  216. cmdstat | PCI_COMMAND_MASTER);
  217. }
  218. void pciauto_postscan_setup_bridge(struct pci_controller *hose,
  219. pci_dev_t dev, int sub_bus)
  220. {
  221. struct pci_region *pci_mem;
  222. struct pci_region *pci_prefetch;
  223. struct pci_region *pci_io;
  224. pci_mem = hose->pci_mem;
  225. pci_prefetch = hose->pci_prefetch;
  226. pci_io = hose->pci_io;
  227. /* Configure bus number registers */
  228. pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
  229. sub_bus - hose->first_busno);
  230. if (pci_mem) {
  231. /* Round memory allocator to 1MB boundary */
  232. pciauto_region_align(pci_mem, 0x100000);
  233. pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
  234. (pci_mem->bus_lower - 1) >> 16);
  235. }
  236. if (pci_prefetch) {
  237. u16 prefechable_64;
  238. pci_hose_read_config_word(hose, dev,
  239. PCI_PREF_MEMORY_LIMIT,
  240. &prefechable_64);
  241. prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
  242. /* Round memory allocator to 1MB boundary */
  243. pciauto_region_align(pci_prefetch, 0x100000);
  244. pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
  245. (pci_prefetch->bus_lower - 1) >> 16);
  246. if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
  247. #ifdef CONFIG_SYS_PCI_64BIT
  248. pci_hose_write_config_dword(hose, dev,
  249. PCI_PREF_LIMIT_UPPER32,
  250. (pci_prefetch->bus_lower - 1) >> 32);
  251. #else
  252. pci_hose_write_config_dword(hose, dev,
  253. PCI_PREF_LIMIT_UPPER32,
  254. 0x0);
  255. #endif
  256. }
  257. if (pci_io) {
  258. /* Round I/O allocator to 4KB boundary */
  259. pciauto_region_align(pci_io, 0x1000);
  260. pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
  261. ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
  262. pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
  263. ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
  264. }
  265. }
  266. /*
  267. * HJF: Changed this to return int. I think this is required
  268. * to get the correct result when scanning bridges
  269. */
  270. int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
  271. {
  272. struct pci_region *pci_mem;
  273. struct pci_region *pci_prefetch;
  274. struct pci_region *pci_io;
  275. unsigned int sub_bus = PCI_BUS(dev);
  276. unsigned short class;
  277. int n;
  278. pci_mem = hose->pci_mem;
  279. pci_prefetch = hose->pci_prefetch;
  280. pci_io = hose->pci_io;
  281. pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
  282. switch (class) {
  283. case PCI_CLASS_BRIDGE_PCI:
  284. debug("PCI Autoconfig: Found P2P bridge, device %d\n",
  285. PCI_DEV(dev));
  286. pciauto_setup_device(hose, dev, 2, pci_mem,
  287. pci_prefetch, pci_io);
  288. /* Passing in current_busno allows for sibling P2P bridges */
  289. hose->current_busno++;
  290. pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
  291. /*
  292. * need to figure out if this is a subordinate bridge on the bus
  293. * to be able to properly set the pri/sec/sub bridge registers.
  294. */
  295. n = pci_hose_scan_bus(hose, hose->current_busno);
  296. /* figure out the deepest we've gone for this leg */
  297. sub_bus = max((unsigned int)n, sub_bus);
  298. pciauto_postscan_setup_bridge(hose, dev, sub_bus);
  299. sub_bus = hose->current_busno;
  300. break;
  301. case PCI_CLASS_BRIDGE_CARDBUS:
  302. /*
  303. * just do a minimal setup of the bridge,
  304. * let the OS take care of the rest
  305. */
  306. pciauto_setup_device(hose, dev, 0, pci_mem,
  307. pci_prefetch, pci_io);
  308. debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
  309. PCI_DEV(dev));
  310. hose->current_busno++;
  311. break;
  312. #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
  313. case PCI_CLASS_BRIDGE_OTHER:
  314. debug("PCI Autoconfig: Skipping bridge device %d\n",
  315. PCI_DEV(dev));
  316. break;
  317. #endif
  318. #if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) && \
  319. !defined(CONFIG_TARGET_CADDY2)
  320. case PCI_CLASS_BRIDGE_OTHER:
  321. /*
  322. * The host/PCI bridge 1 seems broken in 8349 - it presents
  323. * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
  324. * device claiming resources io/mem/irq.. we only allow for
  325. * the PIMMR window to be allocated (BAR0 - 1MB size)
  326. */
  327. debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
  328. pciauto_setup_device(hose, dev, 0, hose->pci_mem,
  329. hose->pci_prefetch, hose->pci_io);
  330. break;
  331. #endif
  332. case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
  333. debug("PCI AutoConfig: Found PowerPC device\n");
  334. default:
  335. pciauto_setup_device(hose, dev, 6, pci_mem,
  336. pci_prefetch, pci_io);
  337. break;
  338. }
  339. return sub_bus;
  340. }