pci.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  4. * Andreas Heppel <aheppel@sysgo.de>
  5. *
  6. * (C) Copyright 2002, 2003
  7. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  8. */
  9. /*
  10. * Old PCI routines
  11. *
  12. * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
  13. * and change pci-uclass.c.
  14. */
  15. #include <common.h>
  16. #include <init.h>
  17. #include <command.h>
  18. #include <env.h>
  19. #include <errno.h>
  20. #include <asm/processor.h>
  21. #include <asm/io.h>
  22. #include <pci.h>
  23. DECLARE_GLOBAL_DATA_PTR;
  24. #define PCI_HOSE_OP(rw, size, type) \
  25. int pci_hose_##rw##_config_##size(struct pci_controller *hose, \
  26. pci_dev_t dev, \
  27. int offset, type value) \
  28. { \
  29. return hose->rw##_##size(hose, dev, offset, value); \
  30. }
  31. PCI_HOSE_OP(read, byte, u8 *)
  32. PCI_HOSE_OP(read, word, u16 *)
  33. PCI_HOSE_OP(read, dword, u32 *)
  34. PCI_HOSE_OP(write, byte, u8)
  35. PCI_HOSE_OP(write, word, u16)
  36. PCI_HOSE_OP(write, dword, u32)
  37. #define PCI_OP(rw, size, type, error_code) \
  38. int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \
  39. { \
  40. struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \
  41. \
  42. if (!hose) \
  43. { \
  44. error_code; \
  45. return -1; \
  46. } \
  47. \
  48. return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
  49. }
  50. PCI_OP(read, byte, u8 *, *value = 0xff)
  51. PCI_OP(read, word, u16 *, *value = 0xffff)
  52. PCI_OP(read, dword, u32 *, *value = 0xffffffff)
  53. PCI_OP(write, byte, u8, )
  54. PCI_OP(write, word, u16, )
  55. PCI_OP(write, dword, u32, )
  56. #define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \
  57. int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
  58. pci_dev_t dev, \
  59. int offset, type val) \
  60. { \
  61. u32 val32; \
  62. \
  63. if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
  64. *val = -1; \
  65. return -1; \
  66. } \
  67. \
  68. *val = (val32 >> ((offset & (int)off_mask) * 8)); \
  69. \
  70. return 0; \
  71. }
  72. #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \
  73. int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
  74. pci_dev_t dev, \
  75. int offset, type val) \
  76. { \
  77. u32 val32, mask, ldata, shift; \
  78. \
  79. if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
  80. return -1; \
  81. \
  82. shift = ((offset & (int)off_mask) * 8); \
  83. ldata = (((unsigned long)val) & val_mask) << shift; \
  84. mask = val_mask << shift; \
  85. val32 = (val32 & ~mask) | ldata; \
  86. \
  87. if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
  88. return -1; \
  89. \
  90. return 0; \
  91. }
  92. PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
  93. PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
  94. PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
  95. PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
  96. /*
  97. *
  98. */
  99. static struct pci_controller* hose_head;
  100. struct pci_controller *pci_get_hose_head(void)
  101. {
  102. if (gd->hose)
  103. return gd->hose;
  104. return hose_head;
  105. }
  106. void pci_register_hose(struct pci_controller* hose)
  107. {
  108. struct pci_controller **phose = &hose_head;
  109. while(*phose)
  110. phose = &(*phose)->next;
  111. hose->next = NULL;
  112. *phose = hose;
  113. }
  114. struct pci_controller *pci_bus_to_hose(int bus)
  115. {
  116. struct pci_controller *hose;
  117. for (hose = pci_get_hose_head(); hose; hose = hose->next) {
  118. if (bus >= hose->first_busno && bus <= hose->last_busno)
  119. return hose;
  120. }
  121. printf("pci_bus_to_hose() failed\n");
  122. return NULL;
  123. }
  124. struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr)
  125. {
  126. struct pci_controller *hose;
  127. for (hose = pci_get_hose_head(); hose; hose = hose->next) {
  128. if (hose->cfg_addr == cfg_addr)
  129. return hose;
  130. }
  131. return NULL;
  132. }
  133. int pci_last_busno(void)
  134. {
  135. struct pci_controller *hose = pci_get_hose_head();
  136. if (!hose)
  137. return -1;
  138. while (hose->next)
  139. hose = hose->next;
  140. return hose->last_busno;
  141. }
  142. pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
  143. {
  144. struct pci_controller * hose;
  145. pci_dev_t bdf;
  146. int bus;
  147. for (hose = pci_get_hose_head(); hose; hose = hose->next) {
  148. for (bus = hose->first_busno; bus <= hose->last_busno; bus++) {
  149. bdf = pci_hose_find_devices(hose, bus, ids, &index);
  150. if (bdf != -1)
  151. return bdf;
  152. }
  153. }
  154. return -1;
  155. }
  156. static int pci_hose_config_device(struct pci_controller *hose, pci_dev_t dev,
  157. ulong io, pci_addr_t mem, ulong command)
  158. {
  159. u32 bar_response;
  160. unsigned int old_command;
  161. pci_addr_t bar_value;
  162. pci_size_t bar_size;
  163. unsigned char pin;
  164. int bar, found_mem64;
  165. debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io,
  166. (u64)mem, command);
  167. pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0);
  168. for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
  169. pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
  170. pci_hose_read_config_dword(hose, dev, bar, &bar_response);
  171. if (!bar_response)
  172. continue;
  173. found_mem64 = 0;
  174. /* Check the BAR type and set our address mask */
  175. if (bar_response & PCI_BASE_ADDRESS_SPACE) {
  176. bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
  177. /* round up region base address to a multiple of size */
  178. io = ((io - 1) | (bar_size - 1)) + 1;
  179. bar_value = io;
  180. /* compute new region base address */
  181. io = io + bar_size;
  182. } else {
  183. if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
  184. PCI_BASE_ADDRESS_MEM_TYPE_64) {
  185. u32 bar_response_upper;
  186. u64 bar64;
  187. pci_hose_write_config_dword(hose, dev, bar + 4,
  188. 0xffffffff);
  189. pci_hose_read_config_dword(hose, dev, bar + 4,
  190. &bar_response_upper);
  191. bar64 = ((u64)bar_response_upper << 32) | bar_response;
  192. bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
  193. found_mem64 = 1;
  194. } else {
  195. bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
  196. }
  197. /* round up region base address to multiple of size */
  198. mem = ((mem - 1) | (bar_size - 1)) + 1;
  199. bar_value = mem;
  200. /* compute new region base address */
  201. mem = mem + bar_size;
  202. }
  203. /* Write it out and update our limit */
  204. pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value);
  205. if (found_mem64) {
  206. bar += 4;
  207. #ifdef CONFIG_SYS_PCI_64BIT
  208. pci_hose_write_config_dword(hose, dev, bar,
  209. (u32)(bar_value >> 32));
  210. #else
  211. pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
  212. #endif
  213. }
  214. }
  215. /* Configure Cache Line Size Register */
  216. pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
  217. /* Configure Latency Timer */
  218. pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
  219. /* Disable interrupt line, if device says it wants to use interrupts */
  220. pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
  221. if (pin != 0) {
  222. pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
  223. PCI_INTERRUPT_LINE_DISABLE);
  224. }
  225. pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command);
  226. pci_hose_write_config_dword(hose, dev, PCI_COMMAND,
  227. (old_command & 0xffff0000) | command);
  228. return 0;
  229. }
  230. /*
  231. *
  232. */
  233. struct pci_config_table *pci_find_config(struct pci_controller *hose,
  234. unsigned short class,
  235. unsigned int vendor,
  236. unsigned int device,
  237. unsigned int bus,
  238. unsigned int dev,
  239. unsigned int func)
  240. {
  241. struct pci_config_table *table;
  242. for (table = hose->config_table; table && table->vendor; table++) {
  243. if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
  244. (table->device == PCI_ANY_ID || table->device == device) &&
  245. (table->class == PCI_ANY_ID || table->class == class) &&
  246. (table->bus == PCI_ANY_ID || table->bus == bus) &&
  247. (table->dev == PCI_ANY_ID || table->dev == dev) &&
  248. (table->func == PCI_ANY_ID || table->func == func)) {
  249. return table;
  250. }
  251. }
  252. return NULL;
  253. }
  254. void pci_cfgfunc_config_device(struct pci_controller *hose,
  255. pci_dev_t dev,
  256. struct pci_config_table *entry)
  257. {
  258. pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1],
  259. entry->priv[2]);
  260. }
  261. void pci_cfgfunc_do_nothing(struct pci_controller *hose,
  262. pci_dev_t dev, struct pci_config_table *entry)
  263. {
  264. }
  265. /*
  266. * HJF: Changed this to return int. I think this is required
  267. * to get the correct result when scanning bridges
  268. */
  269. extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
  270. #ifdef CONFIG_PCI_SCAN_SHOW
  271. __weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
  272. {
  273. if (dev == PCI_BDF(hose->first_busno, 0, 0))
  274. return 0;
  275. return 1;
  276. }
  277. #endif /* CONFIG_PCI_SCAN_SHOW */
  278. int pci_hose_scan_bus(struct pci_controller *hose, int bus)
  279. {
  280. unsigned int sub_bus, found_multi = 0;
  281. unsigned short vendor, device, class;
  282. unsigned char header_type;
  283. #ifndef CONFIG_PCI_PNP
  284. struct pci_config_table *cfg;
  285. #endif
  286. pci_dev_t dev;
  287. #ifdef CONFIG_PCI_SCAN_SHOW
  288. static int indent = 0;
  289. #endif
  290. sub_bus = bus;
  291. for (dev = PCI_BDF(bus,0,0);
  292. dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
  293. PCI_MAX_PCI_FUNCTIONS - 1);
  294. dev += PCI_BDF(0, 0, 1)) {
  295. if (pci_skip_dev(hose, dev))
  296. continue;
  297. if (PCI_FUNC(dev) && !found_multi)
  298. continue;
  299. pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
  300. pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
  301. if (vendor == 0xffff || vendor == 0x0000)
  302. continue;
  303. if (!PCI_FUNC(dev))
  304. found_multi = header_type & 0x80;
  305. debug("PCI Scan: Found Bus %d, Device %d, Function %d\n",
  306. PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
  307. pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
  308. pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
  309. #ifdef CONFIG_PCI_FIXUP_DEV
  310. board_pci_fixup_dev(hose, dev, vendor, device, class);
  311. #endif
  312. #ifdef CONFIG_PCI_SCAN_SHOW
  313. indent++;
  314. /* Print leading space, including bus indentation */
  315. printf("%*c", indent + 1, ' ');
  316. if (pci_print_dev(hose, dev)) {
  317. printf("%02x:%02x.%-*x - %04x:%04x - %s\n",
  318. PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev),
  319. vendor, device, pci_class_str(class >> 8));
  320. }
  321. #endif
  322. #ifdef CONFIG_PCI_PNP
  323. sub_bus = max((unsigned int)pciauto_config_device(hose, dev),
  324. sub_bus);
  325. #else
  326. cfg = pci_find_config(hose, class, vendor, device,
  327. PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
  328. if (cfg) {
  329. cfg->config_device(hose, dev, cfg);
  330. sub_bus = max(sub_bus,
  331. (unsigned int)hose->current_busno);
  332. }
  333. #endif
  334. #ifdef CONFIG_PCI_SCAN_SHOW
  335. indent--;
  336. #endif
  337. if (hose->fixup_irq)
  338. hose->fixup_irq(hose, dev);
  339. }
  340. return sub_bus;
  341. }
  342. int pci_hose_scan(struct pci_controller *hose)
  343. {
  344. #if defined(CONFIG_PCI_BOOTDELAY)
  345. char *s;
  346. int i;
  347. if (!gd->pcidelay_done) {
  348. /* wait "pcidelay" ms (if defined)... */
  349. s = env_get("pcidelay");
  350. if (s) {
  351. int val = simple_strtoul(s, NULL, 10);
  352. for (i = 0; i < val; i++)
  353. udelay(1000);
  354. }
  355. gd->pcidelay_done = 1;
  356. }
  357. #endif /* CONFIG_PCI_BOOTDELAY */
  358. #ifdef CONFIG_PCI_SCAN_SHOW
  359. puts("PCI:\n");
  360. #endif
  361. /*
  362. * Start scan at current_busno.
  363. * PCIe will start scan at first_busno+1.
  364. */
  365. /* For legacy support, ensure current >= first */
  366. if (hose->first_busno > hose->current_busno)
  367. hose->current_busno = hose->first_busno;
  368. #ifdef CONFIG_PCI_PNP
  369. pciauto_config_init(hose);
  370. #endif
  371. return pci_hose_scan_bus(hose, hose->current_busno);
  372. }
  373. void pci_init(void)
  374. {
  375. hose_head = NULL;
  376. /* allow env to disable pci init/enum */
  377. if (env_get("pcidisable") != NULL)
  378. return;
  379. /* now call board specific pci_init()... */
  380. pci_init_board();
  381. }
  382. /* Returns the address of the requested capability structure within the
  383. * device's PCI configuration space or 0 in case the device does not
  384. * support it.
  385. * */
  386. int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
  387. int cap)
  388. {
  389. int pos;
  390. u8 hdr_type;
  391. pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type);
  392. pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F);
  393. if (pos)
  394. pos = pci_find_cap(hose, dev, pos, cap);
  395. return pos;
  396. }
  397. /* Find the header pointer to the Capabilities*/
  398. int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
  399. u8 hdr_type)
  400. {
  401. u16 status;
  402. pci_hose_read_config_word(hose, dev, PCI_STATUS, &status);
  403. if (!(status & PCI_STATUS_CAP_LIST))
  404. return 0;
  405. switch (hdr_type) {
  406. case PCI_HEADER_TYPE_NORMAL:
  407. case PCI_HEADER_TYPE_BRIDGE:
  408. return PCI_CAPABILITY_LIST;
  409. case PCI_HEADER_TYPE_CARDBUS:
  410. return PCI_CB_CAPABILITY_LIST;
  411. default:
  412. return 0;
  413. }
  414. }
  415. int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap)
  416. {
  417. int ttl = PCI_FIND_CAP_TTL;
  418. u8 id;
  419. u8 next_pos;
  420. while (ttl--) {
  421. pci_hose_read_config_byte(hose, dev, pos, &next_pos);
  422. if (next_pos < CAP_START_POS)
  423. break;
  424. next_pos &= ~3;
  425. pos = (int) next_pos;
  426. pci_hose_read_config_byte(hose, dev,
  427. pos + PCI_CAP_LIST_ID, &id);
  428. if (id == 0xff)
  429. break;
  430. if (id == cap)
  431. return pos;
  432. pos += PCI_CAP_LIST_NEXT;
  433. }
  434. return 0;
  435. }
  436. /**
  437. * pci_find_next_ext_capability - Find an extended capability
  438. *
  439. * Returns the address of the next matching extended capability structure
  440. * within the device's PCI configuration space or 0 if the device does
  441. * not support it. Some capabilities can occur several times, e.g., the
  442. * vendor-specific capability, and this provides a way to find them all.
  443. */
  444. int pci_find_next_ext_capability(struct pci_controller *hose, pci_dev_t dev,
  445. int start, int cap)
  446. {
  447. u32 header;
  448. int ttl, pos = PCI_CFG_SPACE_SIZE;
  449. /* minimum 8 bytes per capability */
  450. ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
  451. if (start)
  452. pos = start;
  453. pci_hose_read_config_dword(hose, dev, pos, &header);
  454. if (header == 0xffffffff || header == 0)
  455. return 0;
  456. while (ttl-- > 0) {
  457. if (PCI_EXT_CAP_ID(header) == cap && pos != start)
  458. return pos;
  459. pos = PCI_EXT_CAP_NEXT(header);
  460. if (pos < PCI_CFG_SPACE_SIZE)
  461. break;
  462. pci_hose_read_config_dword(hose, dev, pos, &header);
  463. if (header == 0xffffffff || header == 0)
  464. break;
  465. }
  466. return 0;
  467. }
  468. /**
  469. * pci_hose_find_ext_capability - Find an extended capability
  470. *
  471. * Returns the address of the requested extended capability structure
  472. * within the device's PCI configuration space or 0 if the device does
  473. * not support it.
  474. */
  475. int pci_hose_find_ext_capability(struct pci_controller *hose, pci_dev_t dev,
  476. int cap)
  477. {
  478. return pci_find_next_ext_capability(hose, dev, 0, cap);
  479. }