pci-uclass.c 36 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2014 Google, Inc
  4. * Written by Simon Glass <sjg@chromium.org>
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <malloc.h>
  10. #include <pci.h>
  11. #include <asm/io.h>
  12. #include <dm/device-internal.h>
  13. #include <dm/lists.h>
  14. #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
  15. #include <asm/fsp/fsp_support.h>
  16. #endif
  17. #include "pci_internal.h"
  18. DECLARE_GLOBAL_DATA_PTR;
  19. int pci_get_bus(int busnum, struct udevice **busp)
  20. {
  21. int ret;
  22. ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
  23. /* Since buses may not be numbered yet try a little harder with bus 0 */
  24. if (ret == -ENODEV) {
  25. ret = uclass_first_device_err(UCLASS_PCI, busp);
  26. if (ret)
  27. return ret;
  28. ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
  29. }
  30. return ret;
  31. }
  32. struct udevice *pci_get_controller(struct udevice *dev)
  33. {
  34. while (device_is_on_pci_bus(dev))
  35. dev = dev->parent;
  36. return dev;
  37. }
  38. pci_dev_t dm_pci_get_bdf(const struct udevice *dev)
  39. {
  40. struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
  41. struct udevice *bus = dev->parent;
  42. /*
  43. * This error indicates that @dev is a device on an unprobed PCI bus.
  44. * The bus likely has bus=seq == -1, so the PCI_ADD_BUS() macro below
  45. * will produce a bad BDF>
  46. *
  47. * A common cause of this problem is that this function is called in the
  48. * ofdata_to_platdata() method of @dev. Accessing the PCI bus in that
  49. * method is not allowed, since it has not yet been probed. To fix this,
  50. * move that access to the probe() method of @dev instead.
  51. */
  52. if (!device_active(bus))
  53. log_err("PCI: Device '%s' on unprobed bus '%s'\n", dev->name,
  54. bus->name);
  55. return PCI_ADD_BUS(bus->seq, pplat->devfn);
  56. }
  57. /**
  58. * pci_get_bus_max() - returns the bus number of the last active bus
  59. *
  60. * @return last bus number, or -1 if no active buses
  61. */
  62. static int pci_get_bus_max(void)
  63. {
  64. struct udevice *bus;
  65. struct uclass *uc;
  66. int ret = -1;
  67. ret = uclass_get(UCLASS_PCI, &uc);
  68. uclass_foreach_dev(bus, uc) {
  69. if (bus->seq > ret)
  70. ret = bus->seq;
  71. }
  72. debug("%s: ret=%d\n", __func__, ret);
  73. return ret;
  74. }
  75. int pci_last_busno(void)
  76. {
  77. return pci_get_bus_max();
  78. }
  79. int pci_get_ff(enum pci_size_t size)
  80. {
  81. switch (size) {
  82. case PCI_SIZE_8:
  83. return 0xff;
  84. case PCI_SIZE_16:
  85. return 0xffff;
  86. default:
  87. return 0xffffffff;
  88. }
  89. }
  90. static void pci_dev_find_ofnode(struct udevice *bus, phys_addr_t bdf,
  91. ofnode *rnode)
  92. {
  93. struct fdt_pci_addr addr;
  94. ofnode node;
  95. int ret;
  96. dev_for_each_subnode(node, bus) {
  97. ret = ofnode_read_pci_addr(node, FDT_PCI_SPACE_CONFIG, "reg",
  98. &addr);
  99. if (ret)
  100. continue;
  101. if (PCI_MASK_BUS(addr.phys_hi) != PCI_MASK_BUS(bdf))
  102. continue;
  103. *rnode = node;
  104. break;
  105. }
  106. };
  107. int pci_bus_find_devfn(const struct udevice *bus, pci_dev_t find_devfn,
  108. struct udevice **devp)
  109. {
  110. struct udevice *dev;
  111. for (device_find_first_child(bus, &dev);
  112. dev;
  113. device_find_next_child(&dev)) {
  114. struct pci_child_platdata *pplat;
  115. pplat = dev_get_parent_platdata(dev);
  116. if (pplat && pplat->devfn == find_devfn) {
  117. *devp = dev;
  118. return 0;
  119. }
  120. }
  121. return -ENODEV;
  122. }
  123. int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
  124. {
  125. struct udevice *bus;
  126. int ret;
  127. ret = pci_get_bus(PCI_BUS(bdf), &bus);
  128. if (ret)
  129. return ret;
  130. return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
  131. }
  132. static int pci_device_matches_ids(struct udevice *dev,
  133. struct pci_device_id *ids)
  134. {
  135. struct pci_child_platdata *pplat;
  136. int i;
  137. pplat = dev_get_parent_platdata(dev);
  138. if (!pplat)
  139. return -EINVAL;
  140. for (i = 0; ids[i].vendor != 0; i++) {
  141. if (pplat->vendor == ids[i].vendor &&
  142. pplat->device == ids[i].device)
  143. return i;
  144. }
  145. return -EINVAL;
  146. }
  147. int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
  148. int *indexp, struct udevice **devp)
  149. {
  150. struct udevice *dev;
  151. /* Scan all devices on this bus */
  152. for (device_find_first_child(bus, &dev);
  153. dev;
  154. device_find_next_child(&dev)) {
  155. if (pci_device_matches_ids(dev, ids) >= 0) {
  156. if ((*indexp)-- <= 0) {
  157. *devp = dev;
  158. return 0;
  159. }
  160. }
  161. }
  162. return -ENODEV;
  163. }
  164. int pci_find_device_id(struct pci_device_id *ids, int index,
  165. struct udevice **devp)
  166. {
  167. struct udevice *bus;
  168. /* Scan all known buses */
  169. for (uclass_first_device(UCLASS_PCI, &bus);
  170. bus;
  171. uclass_next_device(&bus)) {
  172. if (!pci_bus_find_devices(bus, ids, &index, devp))
  173. return 0;
  174. }
  175. *devp = NULL;
  176. return -ENODEV;
  177. }
  178. static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
  179. unsigned int device, int *indexp,
  180. struct udevice **devp)
  181. {
  182. struct pci_child_platdata *pplat;
  183. struct udevice *dev;
  184. for (device_find_first_child(bus, &dev);
  185. dev;
  186. device_find_next_child(&dev)) {
  187. pplat = dev_get_parent_platdata(dev);
  188. if (pplat->vendor == vendor && pplat->device == device) {
  189. if (!(*indexp)--) {
  190. *devp = dev;
  191. return 0;
  192. }
  193. }
  194. }
  195. return -ENODEV;
  196. }
  197. int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
  198. struct udevice **devp)
  199. {
  200. struct udevice *bus;
  201. /* Scan all known buses */
  202. for (uclass_first_device(UCLASS_PCI, &bus);
  203. bus;
  204. uclass_next_device(&bus)) {
  205. if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
  206. return device_probe(*devp);
  207. }
  208. *devp = NULL;
  209. return -ENODEV;
  210. }
  211. int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
  212. {
  213. struct udevice *dev;
  214. /* Scan all known buses */
  215. for (pci_find_first_device(&dev);
  216. dev;
  217. pci_find_next_device(&dev)) {
  218. struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
  219. if (pplat->class == find_class && !index--) {
  220. *devp = dev;
  221. return device_probe(*devp);
  222. }
  223. }
  224. *devp = NULL;
  225. return -ENODEV;
  226. }
  227. int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
  228. unsigned long value, enum pci_size_t size)
  229. {
  230. struct dm_pci_ops *ops;
  231. ops = pci_get_ops(bus);
  232. if (!ops->write_config)
  233. return -ENOSYS;
  234. return ops->write_config(bus, bdf, offset, value, size);
  235. }
  236. int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
  237. u32 clr, u32 set)
  238. {
  239. ulong val;
  240. int ret;
  241. ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32);
  242. if (ret)
  243. return ret;
  244. val &= ~clr;
  245. val |= set;
  246. return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
  247. }
  248. int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
  249. enum pci_size_t size)
  250. {
  251. struct udevice *bus;
  252. int ret;
  253. ret = pci_get_bus(PCI_BUS(bdf), &bus);
  254. if (ret)
  255. return ret;
  256. return pci_bus_write_config(bus, bdf, offset, value, size);
  257. }
  258. int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
  259. enum pci_size_t size)
  260. {
  261. struct udevice *bus;
  262. for (bus = dev; device_is_on_pci_bus(bus);)
  263. bus = bus->parent;
  264. return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
  265. size);
  266. }
  267. int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
  268. {
  269. return pci_write_config(bdf, offset, value, PCI_SIZE_32);
  270. }
  271. int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
  272. {
  273. return pci_write_config(bdf, offset, value, PCI_SIZE_16);
  274. }
  275. int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
  276. {
  277. return pci_write_config(bdf, offset, value, PCI_SIZE_8);
  278. }
  279. int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
  280. {
  281. return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
  282. }
  283. int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
  284. {
  285. return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
  286. }
  287. int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
  288. {
  289. return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
  290. }
  291. int pci_bus_read_config(const struct udevice *bus, pci_dev_t bdf, int offset,
  292. unsigned long *valuep, enum pci_size_t size)
  293. {
  294. struct dm_pci_ops *ops;
  295. ops = pci_get_ops(bus);
  296. if (!ops->read_config)
  297. return -ENOSYS;
  298. return ops->read_config(bus, bdf, offset, valuep, size);
  299. }
  300. int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
  301. enum pci_size_t size)
  302. {
  303. struct udevice *bus;
  304. int ret;
  305. ret = pci_get_bus(PCI_BUS(bdf), &bus);
  306. if (ret)
  307. return ret;
  308. return pci_bus_read_config(bus, bdf, offset, valuep, size);
  309. }
  310. int dm_pci_read_config(const struct udevice *dev, int offset,
  311. unsigned long *valuep, enum pci_size_t size)
  312. {
  313. const struct udevice *bus;
  314. for (bus = dev; device_is_on_pci_bus(bus);)
  315. bus = bus->parent;
  316. return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
  317. size);
  318. }
  319. int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
  320. {
  321. unsigned long value;
  322. int ret;
  323. ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
  324. if (ret)
  325. return ret;
  326. *valuep = value;
  327. return 0;
  328. }
  329. int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
  330. {
  331. unsigned long value;
  332. int ret;
  333. ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
  334. if (ret)
  335. return ret;
  336. *valuep = value;
  337. return 0;
  338. }
  339. int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
  340. {
  341. unsigned long value;
  342. int ret;
  343. ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
  344. if (ret)
  345. return ret;
  346. *valuep = value;
  347. return 0;
  348. }
  349. int dm_pci_read_config8(const struct udevice *dev, int offset, u8 *valuep)
  350. {
  351. unsigned long value;
  352. int ret;
  353. ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
  354. if (ret)
  355. return ret;
  356. *valuep = value;
  357. return 0;
  358. }
  359. int dm_pci_read_config16(const struct udevice *dev, int offset, u16 *valuep)
  360. {
  361. unsigned long value;
  362. int ret;
  363. ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
  364. if (ret)
  365. return ret;
  366. *valuep = value;
  367. return 0;
  368. }
  369. int dm_pci_read_config32(const struct udevice *dev, int offset, u32 *valuep)
  370. {
  371. unsigned long value;
  372. int ret;
  373. ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
  374. if (ret)
  375. return ret;
  376. *valuep = value;
  377. return 0;
  378. }
  379. int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
  380. {
  381. u8 val;
  382. int ret;
  383. ret = dm_pci_read_config8(dev, offset, &val);
  384. if (ret)
  385. return ret;
  386. val &= ~clr;
  387. val |= set;
  388. return dm_pci_write_config8(dev, offset, val);
  389. }
  390. int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
  391. {
  392. u16 val;
  393. int ret;
  394. ret = dm_pci_read_config16(dev, offset, &val);
  395. if (ret)
  396. return ret;
  397. val &= ~clr;
  398. val |= set;
  399. return dm_pci_write_config16(dev, offset, val);
  400. }
  401. int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
  402. {
  403. u32 val;
  404. int ret;
  405. ret = dm_pci_read_config32(dev, offset, &val);
  406. if (ret)
  407. return ret;
  408. val &= ~clr;
  409. val |= set;
  410. return dm_pci_write_config32(dev, offset, val);
  411. }
  412. static void set_vga_bridge_bits(struct udevice *dev)
  413. {
  414. struct udevice *parent = dev->parent;
  415. u16 bc;
  416. while (parent->seq != 0) {
  417. dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
  418. bc |= PCI_BRIDGE_CTL_VGA;
  419. dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
  420. parent = parent->parent;
  421. }
  422. }
  423. int pci_auto_config_devices(struct udevice *bus)
  424. {
  425. struct pci_controller *hose = bus->uclass_priv;
  426. struct pci_child_platdata *pplat;
  427. unsigned int sub_bus;
  428. struct udevice *dev;
  429. int ret;
  430. sub_bus = bus->seq;
  431. debug("%s: start\n", __func__);
  432. pciauto_config_init(hose);
  433. for (ret = device_find_first_child(bus, &dev);
  434. !ret && dev;
  435. ret = device_find_next_child(&dev)) {
  436. unsigned int max_bus;
  437. int ret;
  438. debug("%s: device %s\n", __func__, dev->name);
  439. if (dev_read_bool(dev, "pci,no-autoconfig"))
  440. continue;
  441. ret = dm_pciauto_config_device(dev);
  442. if (ret < 0)
  443. return ret;
  444. max_bus = ret;
  445. sub_bus = max(sub_bus, max_bus);
  446. pplat = dev_get_parent_platdata(dev);
  447. if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
  448. set_vga_bridge_bits(dev);
  449. }
  450. debug("%s: done\n", __func__);
  451. return sub_bus;
  452. }
  453. int pci_generic_mmap_write_config(
  454. const struct udevice *bus,
  455. int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
  456. void **addrp),
  457. pci_dev_t bdf,
  458. uint offset,
  459. ulong value,
  460. enum pci_size_t size)
  461. {
  462. void *address;
  463. if (addr_f(bus, bdf, offset, &address) < 0)
  464. return 0;
  465. switch (size) {
  466. case PCI_SIZE_8:
  467. writeb(value, address);
  468. return 0;
  469. case PCI_SIZE_16:
  470. writew(value, address);
  471. return 0;
  472. case PCI_SIZE_32:
  473. writel(value, address);
  474. return 0;
  475. default:
  476. return -EINVAL;
  477. }
  478. }
  479. int pci_generic_mmap_read_config(
  480. const struct udevice *bus,
  481. int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
  482. void **addrp),
  483. pci_dev_t bdf,
  484. uint offset,
  485. ulong *valuep,
  486. enum pci_size_t size)
  487. {
  488. void *address;
  489. if (addr_f(bus, bdf, offset, &address) < 0) {
  490. *valuep = pci_get_ff(size);
  491. return 0;
  492. }
  493. switch (size) {
  494. case PCI_SIZE_8:
  495. *valuep = readb(address);
  496. return 0;
  497. case PCI_SIZE_16:
  498. *valuep = readw(address);
  499. return 0;
  500. case PCI_SIZE_32:
  501. *valuep = readl(address);
  502. return 0;
  503. default:
  504. return -EINVAL;
  505. }
  506. }
  507. int dm_pci_hose_probe_bus(struct udevice *bus)
  508. {
  509. int sub_bus;
  510. int ret;
  511. debug("%s\n", __func__);
  512. sub_bus = pci_get_bus_max() + 1;
  513. debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
  514. dm_pciauto_prescan_setup_bridge(bus, sub_bus);
  515. ret = device_probe(bus);
  516. if (ret) {
  517. debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
  518. ret);
  519. return ret;
  520. }
  521. if (sub_bus != bus->seq) {
  522. printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
  523. __func__, bus->name, bus->seq, sub_bus);
  524. return -EPIPE;
  525. }
  526. sub_bus = pci_get_bus_max();
  527. dm_pciauto_postscan_setup_bridge(bus, sub_bus);
  528. return sub_bus;
  529. }
  530. /**
  531. * pci_match_one_device - Tell if a PCI device structure has a matching
  532. * PCI device id structure
  533. * @id: single PCI device id structure to match
  534. * @find: the PCI device id structure to match against
  535. *
  536. * Returns true if the finding pci_device_id structure matched or false if
  537. * there is no match.
  538. */
  539. static bool pci_match_one_id(const struct pci_device_id *id,
  540. const struct pci_device_id *find)
  541. {
  542. if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
  543. (id->device == PCI_ANY_ID || id->device == find->device) &&
  544. (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
  545. (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
  546. !((id->class ^ find->class) & id->class_mask))
  547. return true;
  548. return false;
  549. }
  550. /**
  551. * pci_find_and_bind_driver() - Find and bind the right PCI driver
  552. *
  553. * This only looks at certain fields in the descriptor.
  554. *
  555. * @parent: Parent bus
  556. * @find_id: Specification of the driver to find
  557. * @bdf: Bus/device/function addreess - see PCI_BDF()
  558. * @devp: Returns a pointer to the device created
  559. * @return 0 if OK, -EPERM if the device is not needed before relocation and
  560. * therefore was not created, other -ve value on error
  561. */
  562. static int pci_find_and_bind_driver(struct udevice *parent,
  563. struct pci_device_id *find_id,
  564. pci_dev_t bdf, struct udevice **devp)
  565. {
  566. struct pci_driver_entry *start, *entry;
  567. ofnode node = ofnode_null();
  568. const char *drv;
  569. int n_ents;
  570. int ret;
  571. char name[30], *str;
  572. bool bridge;
  573. *devp = NULL;
  574. debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
  575. find_id->vendor, find_id->device);
  576. /* Determine optional OF node */
  577. pci_dev_find_ofnode(parent, bdf, &node);
  578. if (ofnode_valid(node) && !ofnode_is_available(node)) {
  579. debug("%s: Ignoring disabled device\n", __func__);
  580. return -EPERM;
  581. }
  582. start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
  583. n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
  584. for (entry = start; entry != start + n_ents; entry++) {
  585. const struct pci_device_id *id;
  586. struct udevice *dev;
  587. const struct driver *drv;
  588. for (id = entry->match;
  589. id->vendor || id->subvendor || id->class_mask;
  590. id++) {
  591. if (!pci_match_one_id(id, find_id))
  592. continue;
  593. drv = entry->driver;
  594. /*
  595. * In the pre-relocation phase, we only bind devices
  596. * whose driver has the DM_FLAG_PRE_RELOC set, to save
  597. * precious memory space as on some platforms as that
  598. * space is pretty limited (ie: using Cache As RAM).
  599. */
  600. if (!(gd->flags & GD_FLG_RELOC) &&
  601. !(drv->flags & DM_FLAG_PRE_RELOC))
  602. return -EPERM;
  603. /*
  604. * We could pass the descriptor to the driver as
  605. * platdata (instead of NULL) and allow its bind()
  606. * method to return -ENOENT if it doesn't support this
  607. * device. That way we could continue the search to
  608. * find another driver. For now this doesn't seem
  609. * necesssary, so just bind the first match.
  610. */
  611. ret = device_bind_ofnode(parent, drv, drv->name, NULL,
  612. node, &dev);
  613. if (ret)
  614. goto error;
  615. debug("%s: Match found: %s\n", __func__, drv->name);
  616. dev->driver_data = id->driver_data;
  617. *devp = dev;
  618. return 0;
  619. }
  620. }
  621. bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
  622. /*
  623. * In the pre-relocation phase, we only bind bridge devices to save
  624. * precious memory space as on some platforms as that space is pretty
  625. * limited (ie: using Cache As RAM).
  626. */
  627. if (!(gd->flags & GD_FLG_RELOC) && !bridge)
  628. return -EPERM;
  629. /* Bind a generic driver so that the device can be used */
  630. sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf),
  631. PCI_FUNC(bdf));
  632. str = strdup(name);
  633. if (!str)
  634. return -ENOMEM;
  635. drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
  636. ret = device_bind_driver_to_node(parent, drv, str, node, devp);
  637. if (ret) {
  638. debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
  639. free(str);
  640. return ret;
  641. }
  642. debug("%s: No match found: bound generic driver instead\n", __func__);
  643. return 0;
  644. error:
  645. debug("%s: No match found: error %d\n", __func__, ret);
  646. return ret;
  647. }
  648. int pci_bind_bus_devices(struct udevice *bus)
  649. {
  650. ulong vendor, device;
  651. ulong header_type;
  652. pci_dev_t bdf, end;
  653. bool found_multi;
  654. int ret;
  655. found_multi = false;
  656. end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
  657. PCI_MAX_PCI_FUNCTIONS - 1);
  658. for (bdf = PCI_BDF(bus->seq, 0, 0); bdf <= end;
  659. bdf += PCI_BDF(0, 0, 1)) {
  660. struct pci_child_platdata *pplat;
  661. struct udevice *dev;
  662. ulong class;
  663. if (!PCI_FUNC(bdf))
  664. found_multi = false;
  665. if (PCI_FUNC(bdf) && !found_multi)
  666. continue;
  667. /* Check only the first access, we don't expect problems */
  668. ret = pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
  669. PCI_SIZE_16);
  670. if (ret)
  671. goto error;
  672. if (vendor == 0xffff || vendor == 0x0000)
  673. continue;
  674. pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
  675. &header_type, PCI_SIZE_8);
  676. if (!PCI_FUNC(bdf))
  677. found_multi = header_type & 0x80;
  678. debug("%s: bus %d/%s: found device %x, function %d", __func__,
  679. bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
  680. pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
  681. PCI_SIZE_16);
  682. pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
  683. PCI_SIZE_32);
  684. class >>= 8;
  685. /* Find this device in the device tree */
  686. ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
  687. debug(": find ret=%d\n", ret);
  688. /* If nothing in the device tree, bind a device */
  689. if (ret == -ENODEV) {
  690. struct pci_device_id find_id;
  691. ulong val;
  692. memset(&find_id, '\0', sizeof(find_id));
  693. find_id.vendor = vendor;
  694. find_id.device = device;
  695. find_id.class = class;
  696. if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
  697. pci_bus_read_config(bus, bdf,
  698. PCI_SUBSYSTEM_VENDOR_ID,
  699. &val, PCI_SIZE_32);
  700. find_id.subvendor = val & 0xffff;
  701. find_id.subdevice = val >> 16;
  702. }
  703. ret = pci_find_and_bind_driver(bus, &find_id, bdf,
  704. &dev);
  705. }
  706. if (ret == -EPERM)
  707. continue;
  708. else if (ret)
  709. return ret;
  710. /* Update the platform data */
  711. pplat = dev_get_parent_platdata(dev);
  712. pplat->devfn = PCI_MASK_BUS(bdf);
  713. pplat->vendor = vendor;
  714. pplat->device = device;
  715. pplat->class = class;
  716. }
  717. return 0;
  718. error:
  719. printf("Cannot read bus configuration: %d\n", ret);
  720. return ret;
  721. }
  722. static void decode_regions(struct pci_controller *hose, ofnode parent_node,
  723. ofnode node)
  724. {
  725. int pci_addr_cells, addr_cells, size_cells;
  726. int cells_per_record;
  727. const u32 *prop;
  728. int len;
  729. int i;
  730. prop = ofnode_get_property(node, "ranges", &len);
  731. if (!prop) {
  732. debug("%s: Cannot decode regions\n", __func__);
  733. return;
  734. }
  735. pci_addr_cells = ofnode_read_simple_addr_cells(node);
  736. addr_cells = ofnode_read_simple_addr_cells(parent_node);
  737. size_cells = ofnode_read_simple_size_cells(node);
  738. /* PCI addresses are always 3-cells */
  739. len /= sizeof(u32);
  740. cells_per_record = pci_addr_cells + addr_cells + size_cells;
  741. hose->region_count = 0;
  742. debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
  743. cells_per_record);
  744. for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) {
  745. u64 pci_addr, addr, size;
  746. int space_code;
  747. u32 flags;
  748. int type;
  749. int pos;
  750. if (len < cells_per_record)
  751. break;
  752. flags = fdt32_to_cpu(prop[0]);
  753. space_code = (flags >> 24) & 3;
  754. pci_addr = fdtdec_get_number(prop + 1, 2);
  755. prop += pci_addr_cells;
  756. addr = fdtdec_get_number(prop, addr_cells);
  757. prop += addr_cells;
  758. size = fdtdec_get_number(prop, size_cells);
  759. prop += size_cells;
  760. debug("%s: region %d, pci_addr=%llx, addr=%llx, size=%llx, space_code=%d\n",
  761. __func__, hose->region_count, pci_addr, addr, size, space_code);
  762. if (space_code & 2) {
  763. type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
  764. PCI_REGION_MEM;
  765. } else if (space_code & 1) {
  766. type = PCI_REGION_IO;
  767. } else {
  768. continue;
  769. }
  770. if (!IS_ENABLED(CONFIG_SYS_PCI_64BIT) &&
  771. type == PCI_REGION_MEM && upper_32_bits(pci_addr)) {
  772. debug(" - beyond the 32-bit boundary, ignoring\n");
  773. continue;
  774. }
  775. pos = -1;
  776. for (i = 0; i < hose->region_count; i++) {
  777. if (hose->regions[i].flags == type)
  778. pos = i;
  779. }
  780. if (pos == -1)
  781. pos = hose->region_count++;
  782. debug(" - type=%d, pos=%d\n", type, pos);
  783. pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
  784. }
  785. /* Add a region for our local memory */
  786. #ifdef CONFIG_NR_DRAM_BANKS
  787. bd_t *bd = gd->bd;
  788. if (!bd)
  789. return;
  790. for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
  791. if (hose->region_count == MAX_PCI_REGIONS) {
  792. pr_err("maximum number of regions parsed, aborting\n");
  793. break;
  794. }
  795. if (bd->bi_dram[i].size) {
  796. pci_set_region(hose->regions + hose->region_count++,
  797. bd->bi_dram[i].start,
  798. bd->bi_dram[i].start,
  799. bd->bi_dram[i].size,
  800. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  801. }
  802. }
  803. #else
  804. phys_addr_t base = 0, size;
  805. size = gd->ram_size;
  806. #ifdef CONFIG_SYS_SDRAM_BASE
  807. base = CONFIG_SYS_SDRAM_BASE;
  808. #endif
  809. if (gd->pci_ram_top && gd->pci_ram_top < base + size)
  810. size = gd->pci_ram_top - base;
  811. if (size)
  812. pci_set_region(hose->regions + hose->region_count++, base,
  813. base, size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  814. #endif
  815. return;
  816. }
  817. static int pci_uclass_pre_probe(struct udevice *bus)
  818. {
  819. struct pci_controller *hose;
  820. debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
  821. bus->parent->name);
  822. hose = bus->uclass_priv;
  823. /* For bridges, use the top-level PCI controller */
  824. if (!device_is_on_pci_bus(bus)) {
  825. hose->ctlr = bus;
  826. decode_regions(hose, dev_ofnode(bus->parent), dev_ofnode(bus));
  827. } else {
  828. struct pci_controller *parent_hose;
  829. parent_hose = dev_get_uclass_priv(bus->parent);
  830. hose->ctlr = parent_hose->bus;
  831. }
  832. hose->bus = bus;
  833. hose->first_busno = bus->seq;
  834. hose->last_busno = bus->seq;
  835. hose->skip_auto_config_until_reloc =
  836. dev_read_bool(bus, "u-boot,skip-auto-config-until-reloc");
  837. return 0;
  838. }
  839. static int pci_uclass_post_probe(struct udevice *bus)
  840. {
  841. struct pci_controller *hose = dev_get_uclass_priv(bus);
  842. int ret;
  843. debug("%s: probing bus %d\n", __func__, bus->seq);
  844. ret = pci_bind_bus_devices(bus);
  845. if (ret)
  846. return ret;
  847. if (CONFIG_IS_ENABLED(PCI_PNP) && ll_boot_init() &&
  848. (!hose->skip_auto_config_until_reloc ||
  849. (gd->flags & GD_FLG_RELOC))) {
  850. ret = pci_auto_config_devices(bus);
  851. if (ret < 0)
  852. return log_msg_ret("pci auto-config", ret);
  853. }
  854. #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
  855. /*
  856. * Per Intel FSP specification, we should call FSP notify API to
  857. * inform FSP that PCI enumeration has been done so that FSP will
  858. * do any necessary initialization as required by the chipset's
  859. * BIOS Writer's Guide (BWG).
  860. *
  861. * Unfortunately we have to put this call here as with driver model,
  862. * the enumeration is all done on a lazy basis as needed, so until
  863. * something is touched on PCI it won't happen.
  864. *
  865. * Note we only call this 1) after U-Boot is relocated, and 2)
  866. * root bus has finished probing.
  867. */
  868. if ((gd->flags & GD_FLG_RELOC) && bus->seq == 0 && ll_boot_init()) {
  869. ret = fsp_init_phase_pci();
  870. if (ret)
  871. return ret;
  872. }
  873. #endif
  874. return 0;
  875. }
  876. static int pci_uclass_child_post_bind(struct udevice *dev)
  877. {
  878. struct pci_child_platdata *pplat;
  879. if (!dev_of_valid(dev))
  880. return 0;
  881. pplat = dev_get_parent_platdata(dev);
  882. /* Extract vendor id and device id if available */
  883. ofnode_read_pci_vendev(dev_ofnode(dev), &pplat->vendor, &pplat->device);
  884. /* Extract the devfn from fdt_pci_addr */
  885. pplat->devfn = pci_get_devfn(dev);
  886. return 0;
  887. }
  888. static int pci_bridge_read_config(const struct udevice *bus, pci_dev_t bdf,
  889. uint offset, ulong *valuep,
  890. enum pci_size_t size)
  891. {
  892. struct pci_controller *hose = bus->uclass_priv;
  893. return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
  894. }
  895. static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
  896. uint offset, ulong value,
  897. enum pci_size_t size)
  898. {
  899. struct pci_controller *hose = bus->uclass_priv;
  900. return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
  901. }
  902. static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
  903. {
  904. struct udevice *dev;
  905. int ret = 0;
  906. /*
  907. * Scan through all the PCI controllers. On x86 there will only be one
  908. * but that is not necessarily true on other hardware.
  909. */
  910. do {
  911. device_find_first_child(bus, &dev);
  912. if (dev) {
  913. *devp = dev;
  914. return 0;
  915. }
  916. ret = uclass_next_device(&bus);
  917. if (ret)
  918. return ret;
  919. } while (bus);
  920. return 0;
  921. }
  922. int pci_find_next_device(struct udevice **devp)
  923. {
  924. struct udevice *child = *devp;
  925. struct udevice *bus = child->parent;
  926. int ret;
  927. /* First try all the siblings */
  928. *devp = NULL;
  929. while (child) {
  930. device_find_next_child(&child);
  931. if (child) {
  932. *devp = child;
  933. return 0;
  934. }
  935. }
  936. /* We ran out of siblings. Try the next bus */
  937. ret = uclass_next_device(&bus);
  938. if (ret)
  939. return ret;
  940. return bus ? skip_to_next_device(bus, devp) : 0;
  941. }
  942. int pci_find_first_device(struct udevice **devp)
  943. {
  944. struct udevice *bus;
  945. int ret;
  946. *devp = NULL;
  947. ret = uclass_first_device(UCLASS_PCI, &bus);
  948. if (ret)
  949. return ret;
  950. return skip_to_next_device(bus, devp);
  951. }
  952. ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
  953. {
  954. switch (size) {
  955. case PCI_SIZE_8:
  956. return (value >> ((offset & 3) * 8)) & 0xff;
  957. case PCI_SIZE_16:
  958. return (value >> ((offset & 2) * 8)) & 0xffff;
  959. default:
  960. return value;
  961. }
  962. }
  963. ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
  964. enum pci_size_t size)
  965. {
  966. uint off_mask;
  967. uint val_mask, shift;
  968. ulong ldata, mask;
  969. switch (size) {
  970. case PCI_SIZE_8:
  971. off_mask = 3;
  972. val_mask = 0xff;
  973. break;
  974. case PCI_SIZE_16:
  975. off_mask = 2;
  976. val_mask = 0xffff;
  977. break;
  978. default:
  979. return value;
  980. }
  981. shift = (offset & off_mask) * 8;
  982. ldata = (value & val_mask) << shift;
  983. mask = val_mask << shift;
  984. value = (old & ~mask) | ldata;
  985. return value;
  986. }
  987. int pci_get_regions(struct udevice *dev, struct pci_region **iop,
  988. struct pci_region **memp, struct pci_region **prefp)
  989. {
  990. struct udevice *bus = pci_get_controller(dev);
  991. struct pci_controller *hose = dev_get_uclass_priv(bus);
  992. int i;
  993. *iop = NULL;
  994. *memp = NULL;
  995. *prefp = NULL;
  996. for (i = 0; i < hose->region_count; i++) {
  997. switch (hose->regions[i].flags) {
  998. case PCI_REGION_IO:
  999. if (!*iop || (*iop)->size < hose->regions[i].size)
  1000. *iop = hose->regions + i;
  1001. break;
  1002. case PCI_REGION_MEM:
  1003. if (!*memp || (*memp)->size < hose->regions[i].size)
  1004. *memp = hose->regions + i;
  1005. break;
  1006. case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
  1007. if (!*prefp || (*prefp)->size < hose->regions[i].size)
  1008. *prefp = hose->regions + i;
  1009. break;
  1010. }
  1011. }
  1012. return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
  1013. }
  1014. u32 dm_pci_read_bar32(const struct udevice *dev, int barnum)
  1015. {
  1016. u32 addr;
  1017. int bar;
  1018. bar = PCI_BASE_ADDRESS_0 + barnum * 4;
  1019. dm_pci_read_config32(dev, bar, &addr);
  1020. /*
  1021. * If we get an invalid address, return this so that comparisons with
  1022. * FDT_ADDR_T_NONE work correctly
  1023. */
  1024. if (addr == 0xffffffff)
  1025. return addr;
  1026. else if (addr & PCI_BASE_ADDRESS_SPACE_IO)
  1027. return addr & PCI_BASE_ADDRESS_IO_MASK;
  1028. else
  1029. return addr & PCI_BASE_ADDRESS_MEM_MASK;
  1030. }
  1031. void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
  1032. {
  1033. int bar;
  1034. bar = PCI_BASE_ADDRESS_0 + barnum * 4;
  1035. dm_pci_write_config32(dev, bar, addr);
  1036. }
  1037. static int _dm_pci_bus_to_phys(struct udevice *ctlr,
  1038. pci_addr_t bus_addr, unsigned long flags,
  1039. unsigned long skip_mask, phys_addr_t *pa)
  1040. {
  1041. struct pci_controller *hose = dev_get_uclass_priv(ctlr);
  1042. struct pci_region *res;
  1043. int i;
  1044. if (hose->region_count == 0) {
  1045. *pa = bus_addr;
  1046. return 0;
  1047. }
  1048. for (i = 0; i < hose->region_count; i++) {
  1049. res = &hose->regions[i];
  1050. if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
  1051. continue;
  1052. if (res->flags & skip_mask)
  1053. continue;
  1054. if (bus_addr >= res->bus_start &&
  1055. (bus_addr - res->bus_start) < res->size) {
  1056. *pa = (bus_addr - res->bus_start + res->phys_start);
  1057. return 0;
  1058. }
  1059. }
  1060. return 1;
  1061. }
  1062. phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
  1063. unsigned long flags)
  1064. {
  1065. phys_addr_t phys_addr = 0;
  1066. struct udevice *ctlr;
  1067. int ret;
  1068. /* The root controller has the region information */
  1069. ctlr = pci_get_controller(dev);
  1070. /*
  1071. * if PCI_REGION_MEM is set we do a two pass search with preference
  1072. * on matches that don't have PCI_REGION_SYS_MEMORY set
  1073. */
  1074. if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
  1075. ret = _dm_pci_bus_to_phys(ctlr, bus_addr,
  1076. flags, PCI_REGION_SYS_MEMORY,
  1077. &phys_addr);
  1078. if (!ret)
  1079. return phys_addr;
  1080. }
  1081. ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr);
  1082. if (ret)
  1083. puts("pci_hose_bus_to_phys: invalid physical address\n");
  1084. return phys_addr;
  1085. }
  1086. int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
  1087. unsigned long flags, unsigned long skip_mask,
  1088. pci_addr_t *ba)
  1089. {
  1090. struct pci_region *res;
  1091. struct udevice *ctlr;
  1092. pci_addr_t bus_addr;
  1093. int i;
  1094. struct pci_controller *hose;
  1095. /* The root controller has the region information */
  1096. ctlr = pci_get_controller(dev);
  1097. hose = dev_get_uclass_priv(ctlr);
  1098. if (hose->region_count == 0) {
  1099. *ba = phys_addr;
  1100. return 0;
  1101. }
  1102. for (i = 0; i < hose->region_count; i++) {
  1103. res = &hose->regions[i];
  1104. if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
  1105. continue;
  1106. if (res->flags & skip_mask)
  1107. continue;
  1108. bus_addr = phys_addr - res->phys_start + res->bus_start;
  1109. if (bus_addr >= res->bus_start &&
  1110. (bus_addr - res->bus_start) < res->size) {
  1111. *ba = bus_addr;
  1112. return 0;
  1113. }
  1114. }
  1115. return 1;
  1116. }
  1117. pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
  1118. unsigned long flags)
  1119. {
  1120. pci_addr_t bus_addr = 0;
  1121. int ret;
  1122. /*
  1123. * if PCI_REGION_MEM is set we do a two pass search with preference
  1124. * on matches that don't have PCI_REGION_SYS_MEMORY set
  1125. */
  1126. if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
  1127. ret = _dm_pci_phys_to_bus(dev, phys_addr, flags,
  1128. PCI_REGION_SYS_MEMORY, &bus_addr);
  1129. if (!ret)
  1130. return bus_addr;
  1131. }
  1132. ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr);
  1133. if (ret)
  1134. puts("pci_hose_phys_to_bus: invalid physical address\n");
  1135. return bus_addr;
  1136. }
  1137. static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags,
  1138. int ea_off)
  1139. {
  1140. int ea_cnt, i, entry_size;
  1141. int bar_id = (bar - PCI_BASE_ADDRESS_0) >> 2;
  1142. u32 ea_entry;
  1143. phys_addr_t addr;
  1144. /* EA capability structure header */
  1145. dm_pci_read_config32(dev, ea_off, &ea_entry);
  1146. ea_cnt = (ea_entry >> 16) & PCI_EA_NUM_ENT_MASK;
  1147. ea_off += PCI_EA_FIRST_ENT;
  1148. for (i = 0; i < ea_cnt; i++, ea_off += entry_size) {
  1149. /* Entry header */
  1150. dm_pci_read_config32(dev, ea_off, &ea_entry);
  1151. entry_size = ((ea_entry & PCI_EA_ES) + 1) << 2;
  1152. if (((ea_entry & PCI_EA_BEI) >> 4) != bar_id)
  1153. continue;
  1154. /* Base address, 1st DW */
  1155. dm_pci_read_config32(dev, ea_off + 4, &ea_entry);
  1156. addr = ea_entry & PCI_EA_FIELD_MASK;
  1157. if (ea_entry & PCI_EA_IS_64) {
  1158. /* Base address, 2nd DW, skip over 4B MaxOffset */
  1159. dm_pci_read_config32(dev, ea_off + 12, &ea_entry);
  1160. addr |= ((u64)ea_entry) << 32;
  1161. }
  1162. /* size ignored for now */
  1163. return map_physmem(addr, flags, 0);
  1164. }
  1165. return 0;
  1166. }
  1167. void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
  1168. {
  1169. pci_addr_t pci_bus_addr;
  1170. u32 bar_response;
  1171. int ea_off;
  1172. /*
  1173. * if the function supports Enhanced Allocation use that instead of
  1174. * BARs
  1175. */
  1176. ea_off = dm_pci_find_capability(dev, PCI_CAP_ID_EA);
  1177. if (ea_off)
  1178. return dm_pci_map_ea_bar(dev, bar, flags, ea_off);
  1179. /* read BAR address */
  1180. dm_pci_read_config32(dev, bar, &bar_response);
  1181. pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
  1182. /*
  1183. * Pass "0" as the length argument to pci_bus_to_virt. The arg
  1184. * isn't actualy used on any platform because u-boot assumes a static
  1185. * linear mapping. In the future, this could read the BAR size
  1186. * and pass that as the size if needed.
  1187. */
  1188. return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE);
  1189. }
  1190. static int _dm_pci_find_next_capability(struct udevice *dev, u8 pos, int cap)
  1191. {
  1192. int ttl = PCI_FIND_CAP_TTL;
  1193. u8 id;
  1194. u16 ent;
  1195. dm_pci_read_config8(dev, pos, &pos);
  1196. while (ttl--) {
  1197. if (pos < PCI_STD_HEADER_SIZEOF)
  1198. break;
  1199. pos &= ~3;
  1200. dm_pci_read_config16(dev, pos, &ent);
  1201. id = ent & 0xff;
  1202. if (id == 0xff)
  1203. break;
  1204. if (id == cap)
  1205. return pos;
  1206. pos = (ent >> 8);
  1207. }
  1208. return 0;
  1209. }
  1210. int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap)
  1211. {
  1212. return _dm_pci_find_next_capability(dev, start + PCI_CAP_LIST_NEXT,
  1213. cap);
  1214. }
  1215. int dm_pci_find_capability(struct udevice *dev, int cap)
  1216. {
  1217. u16 status;
  1218. u8 header_type;
  1219. u8 pos;
  1220. dm_pci_read_config16(dev, PCI_STATUS, &status);
  1221. if (!(status & PCI_STATUS_CAP_LIST))
  1222. return 0;
  1223. dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
  1224. if ((header_type & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
  1225. pos = PCI_CB_CAPABILITY_LIST;
  1226. else
  1227. pos = PCI_CAPABILITY_LIST;
  1228. return _dm_pci_find_next_capability(dev, pos, cap);
  1229. }
  1230. int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap)
  1231. {
  1232. u32 header;
  1233. int ttl;
  1234. int pos = PCI_CFG_SPACE_SIZE;
  1235. /* minimum 8 bytes per capability */
  1236. ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
  1237. if (start)
  1238. pos = start;
  1239. dm_pci_read_config32(dev, pos, &header);
  1240. /*
  1241. * If we have no capabilities, this is indicated by cap ID,
  1242. * cap version and next pointer all being 0.
  1243. */
  1244. if (header == 0)
  1245. return 0;
  1246. while (ttl--) {
  1247. if (PCI_EXT_CAP_ID(header) == cap)
  1248. return pos;
  1249. pos = PCI_EXT_CAP_NEXT(header);
  1250. if (pos < PCI_CFG_SPACE_SIZE)
  1251. break;
  1252. dm_pci_read_config32(dev, pos, &header);
  1253. }
  1254. return 0;
  1255. }
  1256. int dm_pci_find_ext_capability(struct udevice *dev, int cap)
  1257. {
  1258. return dm_pci_find_next_ext_capability(dev, 0, cap);
  1259. }
  1260. int dm_pci_flr(struct udevice *dev)
  1261. {
  1262. int pcie_off;
  1263. u32 cap;
  1264. /* look for PCI Express Capability */
  1265. pcie_off = dm_pci_find_capability(dev, PCI_CAP_ID_EXP);
  1266. if (!pcie_off)
  1267. return -ENOENT;
  1268. /* check FLR capability */
  1269. dm_pci_read_config32(dev, pcie_off + PCI_EXP_DEVCAP, &cap);
  1270. if (!(cap & PCI_EXP_DEVCAP_FLR))
  1271. return -ENOENT;
  1272. dm_pci_clrset_config16(dev, pcie_off + PCI_EXP_DEVCTL, 0,
  1273. PCI_EXP_DEVCTL_BCR_FLR);
  1274. /* wait 100ms, per PCI spec */
  1275. mdelay(100);
  1276. return 0;
  1277. }
  1278. UCLASS_DRIVER(pci) = {
  1279. .id = UCLASS_PCI,
  1280. .name = "pci",
  1281. .flags = DM_UC_FLAG_SEQ_ALIAS,
  1282. .post_bind = dm_scan_fdt_dev,
  1283. .pre_probe = pci_uclass_pre_probe,
  1284. .post_probe = pci_uclass_post_probe,
  1285. .child_post_bind = pci_uclass_child_post_bind,
  1286. .per_device_auto_alloc_size = sizeof(struct pci_controller),
  1287. .per_child_platdata_auto_alloc_size =
  1288. sizeof(struct pci_child_platdata),
  1289. };
  1290. static const struct dm_pci_ops pci_bridge_ops = {
  1291. .read_config = pci_bridge_read_config,
  1292. .write_config = pci_bridge_write_config,
  1293. };
  1294. static const struct udevice_id pci_bridge_ids[] = {
  1295. { .compatible = "pci-bridge" },
  1296. { }
  1297. };
  1298. U_BOOT_DRIVER(pci_bridge_drv) = {
  1299. .name = "pci_bridge_drv",
  1300. .id = UCLASS_PCI,
  1301. .of_match = pci_bridge_ids,
  1302. .ops = &pci_bridge_ops,
  1303. };
  1304. UCLASS_DRIVER(pci_generic) = {
  1305. .id = UCLASS_PCI_GENERIC,
  1306. .name = "pci_generic",
  1307. };
  1308. static const struct udevice_id pci_generic_ids[] = {
  1309. { .compatible = "pci-generic" },
  1310. { }
  1311. };
  1312. U_BOOT_DRIVER(pci_generic_drv) = {
  1313. .name = "pci_generic_drv",
  1314. .id = UCLASS_PCI_GENERIC,
  1315. .of_match = pci_generic_ids,
  1316. };
  1317. void pci_init(void)
  1318. {
  1319. struct udevice *bus;
  1320. /*
  1321. * Enumerate all known controller devices. Enumeration has the side-
  1322. * effect of probing them, so PCIe devices will be enumerated too.
  1323. */
  1324. for (uclass_first_device_check(UCLASS_PCI, &bus);
  1325. bus;
  1326. uclass_next_device_check(&bus)) {
  1327. ;
  1328. }
  1329. }